74AHC1G14; 74AHCT1G14
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1 Rev May 29 Product data sheet 1. General description 2. Features 3. pplications 74HC1G14 and 74HCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt trigger action. These devices are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The HC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The HCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. Symmetrical output impedance High noise immunity ESD protection: HBM JESD22-114E: exceeds 2 V MM JESD : exceeds 2 V CDM JESD22-C11C: exceeds 1 V Low power dissipation Balanced propagation delays SOT353-1 and SOT753 package options Specified from 4 C to +125 C Wave and pulse shapers stable multivibrators Monostable multivibrators 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC1G14GW 4 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; SOT HCT1G14GW 74HC1G14GV 4 C to +125 C SC-74 body width 1.25 mm plastic surface-mounted package; 5 leads SOT753 74HCT1G14GV
2 5. Marking Table 2. Marking codes Type number 74HC1G14GW 74HCT1G14GW 74HC1G14GV 74HCT1G14GV Marking code F CF 14 C14 6. Functional diagram Y Y mna23 mna24 mna25 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 7. Pinning information 7.1 Pinning 74HC1G14 74HCT1G14 n.c. 1 5 V CC 2 GND 3 4 Y 1aaf87 Fig 4. Pin configuration 7.2 Pin description Table 3. Pin description Symbol Pin Description n.c. 1 not connected 2 data input GND 3 ground ( V) Y 4 data output V CC 5 supply voltage Product data sheet Rev May 29 2 of 15
3 8. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level Input L H Output Y H L 9. Limiting values Table 5. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6134). Symbol Parameter Conditions Min Max Unit V CC supply voltage V V I input voltage V I IK input clamping current V I <.5 V 2 - m I OK output clamping current V O <.5 V or V O >V CC +.5 V [1] - ±2 m I O output current.5 V < V O <V CC +.5 V - ±25 m I CC supply current - 75 m I GND ground current 75 - m T stg storage temperature C P tot total power dissipation T amb = 4 C to +125 C [2] - 25 mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For both TSSOP5 and SC-74 packages: above 87.5 C the value of P tot derates linearly with 4. mw/k. 1. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = V). Symbol Parameter Conditions 74HC1G14 74HCT1G14 Unit Min Typ Max Min Typ Max V CC supply voltage V V I input voltage V V O output voltage - V CC - V CC V T amb ambient temperature C Product data sheet Rev May 29 3 of 15
4 11. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = V). Symbol Parameter Conditions 25 C 4 C to +85 C 4 C to +125 C Unit Min Typ Max Min Max Min Max For type 74HC1G14 V OH HIGH-level V I = V T+ or V T output voltage I O = 5 µ; V CC = 2. V V I O = 5 µ; V CC = 3. V V I O = 5 µ; V CC = 4.5 V V I O = 4. m; V CC = 3. V V I O = 8. m; V CC = 4.5 V V V OL LOW-level V I = V T+ or V T output voltage I O = 5 µ; V CC = 2. V V I O = 5 µ; V CC = 3. V V I O = 5 µ; V CC = 4.5 V V I O = 4. m; V CC = 3. V V I O = 8. m; V CC = 4.5 V V I I input leakage current V I = 5.5 V or GND; V CC = V to 5.5 V µ I CC supply current V I =V CC or GND; I O = ; µ V CC = 5.5 V C I input capacitance pf For type 74HCT1G14 V OH HIGH-level V I = V T+ or V T ; V CC = 4.5 V output voltage I O = 5 µ V I O = 8. m V V OL LOW-level V I = V T+ or V T ; V CC = 4.5 V output voltage I O = 5 µ V I O = 8. m V I I input leakage current V I = 5.5 V or GND; V CC = V to 5.5 V I CC supply current V I =V CC or GND; I O = ; V CC = 5.5 V I CC C I additional supply current input capacitance per input pin; V I = 3.4 V; other inputs at V CC or GND; I O = ; V CC = 5.5 V µ µ m pf Product data sheet Rev May 29 4 of 15
5 11.1 Transfer characteristics Table 8. Transfer characteristics t recommended operating conditions; voltages are referenced to GND (ground = V). See Figure 7 and Figure 8. Symbol Parameter Conditions 25 C 4 C to +85 C 4 C to +125 C Unit For type 74HC1G14 V T+ positive-going threshold voltage V T V H negative-going threshold voltage hysteresis voltage For type 74HCT1G14 V T+ positive-going threshold voltage V T V H negative-going threshold voltage hysteresis voltage Min Typ Max Min Max Min Max V CC = 3. V V V CC = 4.5 V V V CC = 5.5 V V V CC = 3. V V V CC = 4.5 V V V CC = 5.5 V V V CC = 3. V V V CC = 4.5 V V V CC = 5.5 V V V CC = 4.5 V V V CC = 5.5 V V V CC = 4.5 V V V CC = 5.5 V V V CC = 4.5 V V V CC = 5.5 V V Product data sheet Rev May 29 5 of 15
6 12. Dynamic characteristics Table 9. Dynamic characteristics GND = V; t r = t f 3. ns. For waveform see Figure 5. For test circuit see Figure 6. Symbol Parameter Conditions 25 C 4 C to +85 C 4 C to +125 C Unit For type 74HC1G14 t pd propagation to Y; [1] delay V CC = 3. V to 3.6 V [2] C PD power dissipation capacitance For type 74HCT1G14 t pd C PD propagation delay power dissipation capacitance [1] t pd is the same as t PLH and t PHL. [2] Typical values are measured at V CC = 3.3 V. [3] Typical values are measured at V CC = 5. V. [4] C PD is used to determine the dynamic power dissipation P D (µw). P D =C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in Volts. Min Typ Max Min Max Min Max C L = 15 pf ns C L = 5 pf ns V CC = 4.5 V to 5.5 V [3] C L = 15 pf ns C L = 5 pf ns per buffer; [4] pf C L =5pF;f=1 MHz; V I = GND to V CC [1] to Y; V CC = 4.5 V to 5.5 V [3] C L = 15 pf ns C L = 5 pf ns per buffer; V I = GND to V CC [4] pf Product data sheet Rev May 29 6 of 15
7 13. Waveforms input V M V CC t PHL t PLH PULSE GENERTOR V I DUT V O Y output V M RT CL mna33 mna11 The test data is given in Table 1 Test data is given in Table 9. Definitions for test circuit: C L = Load capacitance. R T = Termination resistance should be equal to output impedance Z o of the pulse generator. Fig 5. The input () to output (Y) propagation delays Fig 6. Load circuitry for switching times Table 1. Test data Type number Input Output V I V M V M 74HC1G14 GND to V CC.5 V CC.5 V CC 74HCT1G14 GND to 3. V 1.5 V.5 V CC 13.1 Transfer characteristic waveforms V O V I V T+ V T VH V H V I V O V T V T+ mna26 mna27 Fig 7. Transfer characteristic Fig 8. The definitions of V T+, V T and V H Product data sheet Rev May 29 7 of 15
8 1.5 I CC (m) mna41 5 I CC (m) 4 mna V I (V) V 5 I (V) Fig 9. Typical 74HC1G14 transfer characteristics; V CC = 3. V Fig 1. Typical 74HC1G14 transfer characteristics; V CC = 4.5 V 8 mna43 I CC (m) V 6 I (V) Fig 11. Typical 74HC1G14 transfer characteristics; V CC = 5.5 V Product data sheet Rev May 29 8 of 15
9 5 I CC (m) 4 mna44 8 I CC (m) 6 mna V 5 I (V) 2 4 V 6 I (V) Fig 12. Typical 74HCT1G14 transfer characteristics; V CC = 4.5 V Fig 13. Typical 74HCT1G14 transfer characteristics; V CC = 5.5 V 14. pplication information The slow input rise and fall times cause additional power dissipation, which can be calculated using the following formula: P add =f i (t r I CC(V) +t f I CC(V) ) V CC where: P add = additional power dissipation (µw); f i = input frequency (MHz); t r = input rise time (ns); 1 % to 9 %; t f = input fall time (ns); 9 % to 1 %; I CC(V) = average additional supply current (µ). verage additional I CC differs with positive or negative input transitions, as shown in Figure 14 and Figure 15. For 74HC1G14 and 74HCT1G14 used in relaxation oscillator circuit, see Figure 16. Note to the application information: 1. ll values given are typical unless otherwise specified. Product data sheet Rev May 29 9 of 15
10 2 mna36 2 mna58 I CC(V) (µ) I CC(V) (µ) 15 positive-going edge 15 positive-going edge negative-going edge negative-going edge V CC (V) 2 4 V 6 CC (V) Fig 14. verage additional I CC for 74HC1G14 Schmitt trigger devices; linear change of V I between.1v CC to.9v CC Fig 15. verage additional I CC for 74HCT1G14 Schmitt trigger devices; linear change of V I between.1v CC to.9v CC R C mna35 For 74HC1G14: f 1 1 = -- T RC For 74HCT1G14: 1 1 f = -- T RC Fig 16. Relaxation oscillator using the 74HC1G14 and 74HCT1G14 Product data sheet Rev May 29 1 of 15
11 15. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 D E X c y H E v M Z ( 3 ) θ 1 3 e b p e 1 w M detail X L p L mm scale DIMENSIONS (mm are the original dimensions) UNIT max. 1 mm b p c D (1) E (1) e e 1 H E L L p v w y Z (1) θ Note 1. Plastic or metal protrusions of.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT353-1 MO-23 SC-88 EUROPEN PROJECTION ISSUE DTE Fig 17. Package outline SOT353-1 (TSSOP5) Product data sheet Rev May of 15
12 Plastic surface-mounted package; 5 leads SOT753 D B E X y H E v M 5 4 Q 1 c Lp e bp w M B detail X 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT 1 bp c D E e H E L p Q v w y mm OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT753 SC Fig 18. Package outline SOT753 (SC-74) Product data sheet Rev May of 15
13 16. bbreviations Table 11. cronym CDM CMOS DUT ESD HBM MM TTL bbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 17. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes Product data sheet - 74HC_HCT1G14_5 Modifications: Table 7: the conditions for HIGH-level output voltage and LOW-level output voltage have been changed. 74HC_HCT1G14_ Product data sheet - 74HC_HCT1G14_4 74HC_HCT1G14_ Product specification - 74HC_HCT1G14_3 74HC_HCT1G14_ Product specification - 74HC_HCT1G14_2 74HC_HCT1G14_ Product specification - 74HC_HCT1G14_1 74HC_HCT1G14_ Product specification - - Product data sheet Rev May of 15
14 18. Legal information 18.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Product data sheet Rev May of 15
15 2. Contents 1 General description Features pplications Ordering information Marking Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Transfer characteristics Dynamic characteristics Waveforms Transfer characteristic waveforms pplication information Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 18 May 29 Document identifier:
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Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops
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Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output
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Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current
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Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 06 5 November 2009 Product data sheet 1. General description The is a with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9),
More information74HC1G125; 74HCT1G125
Rev. 6 6 September 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number 74HC1G125GW 74HCT1G125GW 74HC1G125GV 74HCT1G125GV
More informationSingle Schmitt trigger buffer
Rev. 10 29 June 2012 Product data sheet 1. General description The provides a buffer function with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined
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Rev. 2 10 June 2016 Product data sheet 1. General description The provides six inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined,
More information74HC132-Q100; 74HCT132-Q100
Rev. 3 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW
More information74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.
Rev. 1 18 November 2013 Product data sheet 1. General description The provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
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Rev. 04 19 March 2008 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate MOS device that complies with JEDE standard no. 7. It is pin compatible with
More information74LVT125; 74LVTH General description. 2. Features. 3. Quick reference data. 3.3 V quad buffer; 3-state
Rev. 06 6 March 2006 Product data sheet. General description 2. Features 3. Quick reference data The is a high-performance BiCMOS product designed for V CC operation at 3.3 V. This device combines low
More information74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate
Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
More information74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate
8-input NND gate Rev. 6 27 December 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-input NND gate. Inputs include clamp diodes. This enables
More information74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger
Rev. 4 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors
More information74HC154; 74HCT to-16 line decoder/demultiplexer
Rev. 06 2 February 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The
More informationThe 74LV08 provides a quad 2-input AND function.
Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.
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Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output
More information74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.
Rev. 1 20 March 2013 Product data sheet 1. General description The is a triple 3-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators
More information74HC03-Q100; 74HCT03-Q100
Rev. 1 4 July 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NND gate with open-drain outputs. Inputs include clamp diodes that enable
More information74HC151-Q100; 74HCT151-Q100
Rev. 2 11 February 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0
More information74AHC14-Q100; 74AHCT14-Q100
Rev. 9 July 202 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
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Rev. 3 28 January 2019 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package The provides a buffer function with Schmitt
More information74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate
Rev. 4 17 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use
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Rev. 04 17 March 2009 Product data sheet 1. General description The is a for liquid crystal and LED displays. It has four address inputs (D0 to D3), an active LOW latch enable input (LE), an active HIGH
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Rev. 1 9 October 2014 Product data sheet 1. General description The is a dual inverter with Schmitt-trigger inputs. It transforms slowly changing input signals into sharply defined, jitter-free output
More informationLow-power 2-input NAND Schmitt trigger
Rev. 5 29 June 2012 Product data sheet 1. General description The provides the single 2-input NND Schmitt trigger function which accept standard input signals. They are capable of transforming slowly changing
More information74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.
Rev. 3 27 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
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Rev. 5 26 November 2018 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package 74HC3G04DP 74HCT3G04DP 74HC3G04DC 74HCT3G04DC
More informationThe 74LVC10A provides three 3-input NAND functions.
Triple 3-input NND gate Rev. 5 7 November 20 Product data sheet. General description The provides three 3-input NND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows
More information74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate
Rev. 3 3 September 2012 Product data sheet 1. General description 2. Features and benefits The is a dual 4-input NND gate. Inputs include clamp diodes. This enables the use of current limiting resistors
More information74AHC30-Q100; 74AHCT30-Q100
Rev. 1 20 November 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky
More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
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Rev. 3 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each
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Rev. 3 5 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current
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Rev. 1 16 July 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC08-Q100; 7 4HCT08-Q100 is a quad 2-input ND gate. Inputs include clamp diodes. This
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Rev. 2 12 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH
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Rev. 6 26 July 2018 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package 74HC2G02DP 74HCT2G02DP 74HC2G02DC 74HCT2G02DC
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Rev. 8 23 September 2015 Product data sheet 1. General description The provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the
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Rev. 02 18 October 2007 Product data sheet 1. General description 2. Features The is an octal -type transparent latch featuring separate -type inputs for each latch and 3-state true outputs for bus-oriented
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Rev. 03 20 December 2006 Product data sheet 1. General description 2. Features 3. Applications The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The is
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Rev. 14 15 December 2016 Product data sheet 1. General description The provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply
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Rev. 1 28 November 2017 Product data sheet 1 General description 2 Features and benefits The provides the single buffer function. This device ensures a very low static and dynamic power consumption across
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Rev. 7 4 July 2012 Product data sheet 1. General description The provides a single -input ND gate. The input can be driven from either. V or 5 V devices. This feature allows the use of this device in a
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Rev. 3 15 September 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a 9-bit parity generator or checker. Both even and odd parity outputs are available.
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Rev. 6 0 November 20 Product data sheet. General description The provides six inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low wired-or
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Rev. 04 16 June 2006 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
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Rev. 03 8 January 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4017. The is a 5-stage Johnson decade counter with
More informationSingle D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.
Rev. 12 5 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH
More information74HC32-Q100; 74HCT32-Q100
Rev. 1 1 ugust 2012 Product data sheet 1. General description The is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages
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