74HC3G14; 74HCT3G14. Triple inverting Schmitt trigger. The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device.
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1 Rev. 3 8 May 29 Product data sheet 1. General description 2. Features 3. pplications 4. Ordering information The is a high-speed Si-gate CMOS device. The provides three inverting buffers with Schmitt trigger inputs which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Wide supply voltage range from 2. V to 6. V High noise immunity Low power dissipation Balanced propagation delays Unlimited input rise and fall times Multiple package options ESD protection: HBM JESD22-114E exceeds 2 V MM JESD exceeds 2 V Specified from 4 C to+85 C and 4 C to +125 C Wave and pulse shaper for highly noisy environments stable multivibrators Monostable multivibrators Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC3G14DP 4 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; SOT HCT3G14DP 74HC3G14DC 4 C to +125 C VSSOP8 body width 3 mm; lead length.5 mm plastic very thin shrink small outline package; 8 leads; SOT HCT3G14DC 74HC3G14GD 74HCT3G14GD 4 C to +125 C XSON8U body width 2.3 mm plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body mm SOT996-2
2 5. Marking Table 2. Marking Type number 74HC3G14DP 74HCT3G14DP 74HC3G14DC 74HCT3G14DC 74HC3G14GD 74HCT3G14GD Marking code H14 T14 H14 T14 H14 T14 6. Functional diagram 1 1Y 3Y 3 2 2Y Y 1aah728 1aah729 mna25 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one Schmitt trigger) 7. Pinning information 7.1 Pinning 74HC3G14 74HCT3G14 74HC3G14 74HCT3G14 1 3Y V CC 1Y V CC Y Y 3 GND 4 5 2Y GND 4 5 2Y 1aak36 1aak35 Transparent top view Fig 4. Pin configuration SOT55-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8U) Product data sheet Rev. 3 8 May 29 2 of 18
3 7.2 Pin description Table 3. Pin description Symbol Pin Description 1, 2, 3 1, 3, 6 data input GND 4 ground ( V) 1Y, 2Y, 3Y 7, 5, 2 data output V CC 8 supply voltage 8. Functional description Table 4. Function table [1] Input n L H Output ny H L [1] H = HIGH voltage level; L = LOW voltage level. 9. Limiting values Table 5. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6134). Voltages are referenced to GND (ground = V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I <.5 V or V I >V CC +.5 V [1] - ±2 m I OK output clamping current V O <.5 V or V O >V CC +.5 V [1] - ±2 m I O output current V O =.5 V to V CC +.5 V [1] - ±25 m I CC supply current [1] - +5 m I GND ground current [1] 5 - m T stg storage temperature C P tot total power dissipation [2] - 3 mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 C the value of P tot derates linearly with 2.5 mw/k. For VSSOP8 package: above 11 C the value of P tot derates linearly with 8 mw/k. For XSON8U package: above 118 C the value of P tot derates linearly with 7.8 mw/k. Product data sheet Rev. 3 8 May 29 3 of 18
4 1. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = V). Symbol Parameter Conditions 74HC3G14 74HCT3G14 Unit Min Typ Max Min Typ Max V CC supply voltage V V I input voltage - V CC - V CC V V O output voltage - V CC - V CC V T amb ambient temperature C 11. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = V). ll typical values are measured at T amb =25 C. Symbol Parameter Conditions 25 C 4 C to +85 C 4 C to +125 C Unit Min Typ Max Min Max Min Max 74HC3G14 V OH HIGH-level V I = V T+ or V T output voltage I O = 2 µ; V CC = 2. V V I O = 2 µ; V CC = 4.5 V V I O = 2 µ; V CC = 6. V V I O = 4. m; V CC = 4.5 V V I O = 5.2 m; V CC = 6. V V V OL LOW-level V I = V T+ or V T output voltage I O = 2 µ; V CC = 2. V V I O = 2 µ; V CC = 4.5 V V I O = 2 µ; V CC = 6. V V I O = 4. m; V CC = 4.5 V V I O = 5.2 m; V CC = 6. V V I I input leakage current V I =V CC or GND; V CC = 6. V - - ±.1 - ±1. - ±1. µ I CC supply current per input pin; V CC = 6. V; µ V I =V CC or GND; I O =; C I input capacitance pf 74HCT3G14 V OH HIGH-level V I = V T+ or V T output voltage I O = 2 µ; V CC = 4.5 V V I O = 4. m; V CC = 4.5 V V V OL LOW-level V I = V IH or V IL output voltage I O = 2 µ; V CC = 4.5 V V I O = 4. m; V CC = 4.5 V V I I input leakage current V I =V CC or GND; V CC = 5.5 V - - ±.1 - ±1. - ±1. µ Product data sheet Rev. 3 8 May 29 4 of 18
5 Table 7. Static characteristics continued Voltages are referenced to GND (ground = V). ll typical values are measured at T amb =25 C. Symbol Parameter Conditions 25 C 4 C to +85 C 4 C to +125 C Unit I CC supply current per input pin; V CC = 5.5 V; V I =V CC or GND; I O =; I CC C I additional supply current input capacitance per input; V CC = 4.5 V to 5.5 V; V I =V CC 2.1 V; I O = Min Typ Max Min Max Min Max µ µ pf Table 8. Transfer characteristics Voltages are referenced to GND (ground = V); for test circuit see Figure 11. Symbol Parameter Conditions 25 C 4 C to +125 C Unit 74HC3G14 V T+ positive-going threshold voltage V T negative-going threshold voltage Min Typ Max Min Max (85 C) Max (125 C) see Figure 6, Figure 7 V CC = 2. V V V CC = 4.5 V V V CC = 6. V V see Figure 6, Figure 7 V CC = 2. V V V CC = 4.5 V V V CC = 6. V V V H hysteresis voltage (V T+ V T ); see Figure 6, Figure 7 and Figure 9 V CC = 2. V V V CC = 4.5 V V V CC = 6. V V 74HCT3G14 V T+ positive-going see Figure 6, Figure 7 threshold voltage V CC = 4.5 V V V CC = 5.5 V V V T negative-going threshold voltage see Figure 6, Figure 7 V CC = 4.5 V V V CC = 5.5 V V V H hysteresis voltage (V T+ V T ); see Figure 6, Figure 7 and Figure 8 V CC = 4.5 V V V CC = 5.5 V V Product data sheet Rev. 3 8 May 29 5 of 18
6 11.1 Waveforms transfer characteristics V O V I V T+ V T VH V H V T+ V I V O V T mna27 mna28 Fig 6. Transfer characteristic Fig 7. Definition of V T+, V T and V H 2. mna31 3. mna32 I CC (m) I CC (m) V 5. I (V) V I (V) a. V CC = 4.5 V. b. V CC = 5.5 V. Fig 8. Typical 74HCT3G14 transfer characteristics Product data sheet Rev. 3 8 May 29 6 of 18
7 1 mna28 1. mna29 I CC (µ) I CC (m) V 2. I (V) 2.5 V 5. I (V) a. V CC = 2. V b. V CC = 4.5 V 1.6 mna3 I CC (m) V I (V) c. V CC = 6. V Fig 9. Typical 74HC3G14 transfer characteristics Product data sheet Rev. 3 8 May 29 7 of 18
8 12. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = V); for test circuit see Figure 11. Symbol Parameter Conditions 25 C 4 C to +125 C Unit Min Typ Max Min Max (85 C) Max (125 C) 74HC3G14 t pd propagation delay n to ny; see Figure 1 [1] V CC = 2. V ns V CC = 4.5 V ns V CC = 6. V ns t t transition time ny; see Figure 1 [2] V CC = 2. V ns V CC = 4.5 V ns V CC = 6. V ns C PD power dissipation capacitance V I = GND to V CC [3] pf 74HCT3G14 t pd propagation delay n to ny; see Figure 1 [1] V CC = 4.5 V ns t t transition time ny; see Figure 1 [2] V CC = 4.5 V ns C PD power dissipation capacitance V I = GND to V CC 1.5 V [3] pf [1] t pd is the same as t PLH and t PHL [2] t t is the same as t TLH and t THL [3] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+Σ(C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; Σ(C L V 2 CC f o ) = sum of the outputs. Product data sheet Rev. 3 8 May 29 8 of 18
9 13. Waveforms n input V I GND V M V M t PHL t PLH V OH ny output V OL 9 % V M V M 1 % t THL t TLH mna722 Fig 1. Measurement points are given in Table 1. V OL and V OH are typical voltage output levels that occur with the output load. The data input (n) to output (ny) propagation delays and output transition times Table 1. Measurement points Type Input Output V M V M 74HC3G14.5V CC.5V CC 74HCT3G V 1.3 V Product data sheet Rev. 3 8 May 29 9 of 18
10 V I negative pulse V 9 % V M 1 % t W V M t f t r t r t f V I positive pulse V 1 % 9 % V M t W V M V CC V CC G VI DUT VO RL S1 open RT CL 1aad983 Fig 11. Test data is given in Table 11. Definitions for test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistance. S1 = Test selection switch. Test circuit for measuring switching times Table 11. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH 74HC3G14 GND to V CC 6 ns 5 pf 1 kω open 74HCT3G14 GND to 3. V 6 ns 5 pf 1 kω open Product data sheet Rev. 3 8 May 29 1 of 18
11 14. pplication information The slow input rise and fall times cause additional power dissipation, which can be calculated using the following formula: P add =f i (t r I CC(V) +t f I CC(V) ) V CC where: P add = additional power dissipation (µw); f i = input frequency (MHz); t r = input rise time (ns); 1 % to 9 %; t f = input fall time (ns); 9 % to 1 %; I CC(V) = average additional supply current (µ). I CC(V) differs with positive or negative input transitions, as shown in Figure 12 and Figure 13. n example of a relaxation circuit using the 74HC3G14/74HCT3G14 is shown in Figure mna36 I CC(V) (µ) 15 positive-going edge 1 5 negative-going edge V CC (V) Fig 12. linear change of V I between.1v CC to.9v CC. I CC(V) as a function of V CC for 74HC3G14 Product data sheet Rev. 3 8 May of 18
12 2 mna58 I CC(V) (µ) 15 positive-going edge 1 5 negative-going edge 2 4 V 6 CC (V) Fig 13. linear change of V I between.1v CC to.9v CC. I CC(V) as a function of V CC for 74HCT3G14 R C mna35 For 74HC3G14: f 1 1 = -- T RC Fig 14. For 74HCT3G14: Relaxation oscillator 1 1 f = -- T RC Product data sheet Rev. 3 8 May of 18
13 15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length.5 mm SOT55-2 D E X c y H E v M Z ( 3 ) pin 1 index L p θ L 1 4 detail X e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT max. 1 mm b p c D (1) E (1) e H E L L p v w y Z (1) θ Note 1. Plastic or metal protrusions of.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT Fig 15. Package outline SOT55-2 (TSSOP8) Product data sheet Rev. 3 8 May of 18
14 VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E X c y H E v M Z 8 5 Q 2 1 pin 1 index ( 3 ) L p θ 1 4 detail X L e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT max. 1 mm b p c D (1) E (2) e H E L L p Q v w y Z (1) θ Notes 1. Plastic or metal protrusions of.15 mm maximum per side are not included. 2. Plastic or metal protrusions of.25 mm maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT765-1 MO Fig 16. Package outline SOT765-1 (VSSOP8) Product data sheet Rev. 3 8 May of 18
15 XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x.5 mm SOT996-2 D B E 1 detail X terminal 1 index area L 1 e 1 e b 1 4 v M w M C C B y 1 C C y L 2 L 8 5 X DIMENSIONS (mm are the original dimensions) UNIT max mm b D E e e 1 L L mm scale L 2 v w y y 1.1 OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT EUROPEN PROJECTION ISSUE DTE Fig 17. Package outline SOT996-2 (XSON8U) Product data sheet Rev. 3 8 May of 18
16 16. bbreviations Table 12. cronym CMOS DUT ESD HBM MM bbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model 17. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 2958 Product data sheet - 74HC_HCT3G14_2 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. dded type number 74HC3G14GD and 74HCT3G14GD (XSON8U package) 74HC_HCT3G14_ Product specification - 74HC_HCT3G14_1 74HC_HCT3G14_ Product specification - - Product data sheet Rev. 3 8 May of 18
17 18. Legal information 18.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Product data sheet Rev. 3 8 May of 18
18 2. Contents 1 General description Features pplications Ordering information Marking Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Waveforms transfer characteristics Dynamic characteristics Waveforms pplication information Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 8 May 29 Document identifier:
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Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
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Rev. 3 27 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
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Rev. 06 6 March 2006 Product data sheet. General description 2. Features 3. Quick reference data The is a high-performance BiCMOS product designed for V CC operation at 3.3 V. This device combines low
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Rev. 03 20 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
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Rev. 2 14 March 2014 Product data sheet 1. General description The is a dual inverter with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface
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Rev. 4 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops
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Rev. 1 18 November 2013 Product data sheet 1. General description The provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
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Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 3 3 September 2012 Product data sheet 1. General description 2. Features and benefits The is a dual 4-input NND gate. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.
More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 07 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and
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Rev. 10 29 June 2012 Product data sheet 1. General description The provides a buffer function with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined
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Rev. 5 29 June 2012 Product data sheet 1. General description The provides the single 2-input NND Schmitt trigger function which accept standard input signals. They are capable of transforming slowly changing
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Rev. 8 2 November 20 Product data sheet. General description 2. Features and benefits 3. pplications The is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP),
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