74AHC14; 74AHCT14. Hex inverting Schmitt trigger
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- Aubrey Ellis
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1 Rev May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7. The provides six inverting buffers with Schmitt-trigger action. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Balanced propagation delays ll inputs have Schmitt-trigger actions Inputs accept voltages higher than V CC Input levels: For 74HC4: CMOS level For 74HCT4: TTL level ESD protection: HBM EI/JESD22-4E exceeds 2000 V MM EI/JESD22-5- exceeds 200 V CDM EI/JESD22-C0C exceeds 000 V Multiple package options Specified from 40 C to +85 C and from 40 C to +25 C
2 3. Ordering information Table. Type number Ordering information Package 4. Functional diagram Temperature range Name Description Version 74HC4 74HC4D 40 C to +25 C SO4 plastic small outline package; 4 leads; body width 3.9 mm 74HC4PW 40 C to +25 C TSSOP4 plastic thin shrink small outline package; 4 leads; body width 4.4 mm 74HC4BQ 40 C to +25 C DHVQFN4 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body mm 74HCT4 74HCT4D 40 C to +25 C SO4 plastic small outline package; 4 leads; body width 3.9 mm 74HCT4PW 40 C to +25 C TSSOP4 plastic thin shrink small outline package; 4 leads; body width 4.4 mm 74HCT4BQ 40 C to +25 C DHVQFN4 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body mm SOT08- SOT402- SOT762- SOT08- SOT402- SOT Y 2 2 2Y Y Y Y Y Y mna204 00aac497 mna025 Fig. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one Schmitt-trigger) Product data sheet Rev May of 6
3 5. Pinning information 5. Pinning terminal index area VCC Y V CC Y Y 2 2Y Y 5 5Y 2Y 3 3Y GND () Y 4 3Y GND Y GND 4Y 00aac499 00aac498 Transparent top view () The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO4 and TSSOP4 Fig 5. Pin configuration DHVQFN4 5.2 Pin description Table 2. Pin description Symbol Pin Description data input Y 2 data output 2 3 data input 2 2Y 4 data output data input 3 3Y 6 data output 3 GND 7 ground (0 V) 4Y 8 data output data input 4 5Y 0 data output 5 5 data input 5 6Y 2 data output data input 6 V CC 4 supply voltage Product data sheet Rev May of 6
4 6. Functional description Table 3. Function table [] Input n L H Output ny H L [] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V V I input voltage V I IK input clamping current V I < 0.5 V [] 20 - m I OK output clamping current V O < 0.5 V or V O >V CC V [] m I O output current V O = 0.5 V to (V CC V) m I CC supply current m I GND ground current 75 - m T stg storage temperature C P tot total power dissipation T amb = 40 C to +25 C [2] mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO4 packages: above 70 C the value of P tot derates linearly at 8 mw/k. For TSSOP4 packages: above 60 C the value of P tot derates linearly at 5.5 mw/k. For DHVQFN4 packages: above 60 C the value of P tot derates linearly at 4.5 mw/k. 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 74HC4 V CC supply voltage V V I input voltage V V O output voltage 0 - V CC V T amb ambient temperature C 74HCT4 V CC supply voltage V V I input voltage V V O output voltage 0 - V CC V T amb ambient temperature C Product data sheet Rev May of 6
5 9. Static characteristics Table 6. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit 74HC4 V OH HIGH-level output voltage V OL I I LOW-level output voltage input leakage current Min Typ Max Min Max Min Max V I = V T+ or V T I O = 50 µ; V CC = 2.0 V V I O = 50 µ; V CC = 3.0 V V I O = 50 µ; V CC = 4.5 V V I O = 4.0 m; V CC = 3.0 V V I O = 8.0 m; V CC = 4.5 V V V I = V T+ or V T I O = 50 µ; V CC = 2.0 V V I O = 50 µ; V CC = 3.0 V V I O = 50 µ; V CC = 4.5 V V I O = 4.0 m; V CC = 3.0 V V I O = 8.0 m; V CC = 4.5 V V V I = 5.5 V or GND; µ V CC = 0 V to 5.5 V µ I CC supply current V I =V CC or GND; I O = 0 ; V CC = 5.5 V C I input capacitance C O output capacitance 74HCT4 V OH HIGH-level output voltage V OL I I LOW-level output voltage input leakage current pf pf V I = V T+ or V T I O = 50 µ; V CC = 4.5 V V I O = 8.0 m; V CC = 4.5 V V V I = V T+ or V T I O = 50 µ; V CC = 4.5 V V I O = 8.0 m; V CC = 4.5 V V V I = 5.5 V or GND; µ V CC = 0 V to 5.5 V µ I CC supply current V I =V CC or GND; I O = 0 ; V CC = 5.5 V I CC C I C O additional supply current input capacitance output capacitance per input pin; V I =V CC 2. V; other pins at V CC or GND; I O =0; V CC = 4.5 V to 5.5 V m pf pf Product data sheet Rev May of 6
6 0. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max Min Max 74HC4 t pd propagation n to ny; see Figure 6 [2] delay V CC = 3.0 V to 3.6 V C L = 5 pf ns C L = 50 pf ns V CC = 4.5 V to 5.5 V C L = 5 pf ns C L = 50 pf ns C PD power dissipation capacitance f i = MHz; V I = GND to V CC [3] pf 74HCT4 t pd propagation n to ny; see Figure 6 [2] delay V CC = 4.5 V to 5.5 V C L = 5 pf ns C L = 50 pf ns C PD power dissipation capacitance f i = MHz; V I = GND to V CC [3] pf [] Typical values are measured at nominal supply voltage (V CC = 3.3 V and V CC = 5.0 V). [2] t pd is the same as t PLH and t PHL. [3] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V CC 2 f i N+Σ(C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; Σ(C L V 2 CC f o ) = sum of the outputs. Product data sheet Rev May of 6
7 . Waveforms V I n input GND t PHL t PLH V OH ny output V OL mna344 Fig 6. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Input to output propagation delays Table 8. Measurement points Type Input Output 74HC4 0.5 V CC 0.5 V CC 74HCT4.5 V 0.5 V CC V I 90 % negative pulse GND 0 % t f t W t r V I positive pulse 0 % GND t r 90 % t W t f V CC G VI DUT VO RT CL 00aah768 Fig 7. Test data is given in Table 9. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator C L = Load capacitance including jig and probe capacitance Load circuitry for measuring switching times Product data sheet Rev May of 6
8 Table 9. Test data Type Input Load Test V I t r, t f C L 74HC4 V CC 3.0 ns 50 pf, 5 pf t PLH, t PHL 74HCT4 3.0 V 3.0 ns 50 pf, 5 pf t PLH, t PHL 2. Transfer characteristics Table 0. Transfer characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Figure 8 and Figure 9. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit 74HC4 V T+ positive-going threshold voltage V T V H negative-going threshold voltage hysteresis voltage 74HCT4 V T+ positive-going threshold voltage V T negative-going threshold voltage V H hysteresis voltage 3. Transfer characteristics waveforms Min Typ Max Min Max Min Max V CC = 3.0 V V V CC = 4.5 V V V CC = 5.5 V V V CC = 3.0 V V V CC = 4.5 V V V CC = 5.5 V V V CC = 3.0 V V V CC = 4.5 V V V CC = 5.5 V V V CC = 4.5 V V V CC = 5.5 V V V CC = 4.5 V V V CC = 5.5 V V V CC = 4.5 V V V CC = 5.5 V V V O V I V T+ V T VH V H V T+ V I V O V T mna207 mna208 Fig 8. Transfer characteristics Fig 9. Transfer characteristics definitions Product data sheet Rev May of 6
9 .5 I CC (m) mna4 5 I CC (m) 4 mna V I (V) V 5 I (V) a. V CC = 3.0 V b. V CC = 4.5 V 6 mna43 I CC (m) V 6 I (V) Fig 0. c. V CC = 5.5 V Typical 74HC transfer characteristics Product data sheet Rev May of 6
10 6 mna44 8 mna45 I CC (m) I CC (m) V 5 I (V) V 6 I (V) a. V CC = 4.5 V b. V CC = 5.5 V Fig. Typical 74HCT transfer characteristics 4. pplication information R C mna035 For 74HC4: f = -- T RC Fig 2. For 74HCT4: Relaxation oscillator f = -- T RC Product data sheet Rev May of 6
11 5. Package outline SO4: plastic small outline package; 4 leads; body width 3.9 mm SOT08- D E X c y H E v M Z 4 8 Q pin index 2 ( ) 3 θ L p 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D () E () e H () E L L p Q v w y Z Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT08-076E06 MS Fig 3. Package outline SOT08- (SO4) Product data sheet Rev May 2009 of 6
12 TSSOP4: plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT402- D E X c y H E v M Z 4 8 pin index 2 Q ( ) 3 θ 7 e b p w M detail X L p L mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm θ o 8 o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402- MO-53 EUROPEN PROJECTION ISSUE DTE Fig 4. Package outline SOT402- (TSSOP4) Product data sheet Rev May of 6
13 DHVQFN4: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body 2.5 x 3 x 0.85 mm SOT762- D B E c terminal index area detail X terminal index area e e b 2 6 v M w M C C B y C C y L 7 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () E h e e L v w y y mm Note. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig 5. Package outline SOT762- (DHVQFN4) Product data sheet Rev May of 6
14 6. bbreviations Table. cronym CDM CMOS DUT ESD HBM LSTTL MM bbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model 7. Revision history Table 2. Revision history Document ID Release date Data sheet status Change notice Supersedes Product data sheet - 74HC_HCT4_4 Modifications: Table 6: the conditions for HIGH-level output voltage and LOW-level output voltage have been changed. 74HC_HCT4_ Product data sheet - 74HC_HCT4_3 74HC_HCT4_ Product specification - 74HC_HCT4_2 74HC_HCT4_ Product specification - 74HC_HCT4_N_ 74HC_HCT4_N_ 9990 Preliminary specification - - Product data sheet Rev May of 6
15 8. Legal information 8. Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 8.3 Disclaimers General Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia accepts no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6034) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Nexperia. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 8.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 9. Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Product data sheet Rev May of 6
16 20. Contents General description Features Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Transfer characteristics Transfer characteristics waveforms pplication information Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Date of release: 04 May 2009
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Rev. 03 31 January 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).
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Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW
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Rev. 3 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 05 23 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed, Si-gate CMOS device. The provides one non-inverting buffer/line driver with 3-state
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Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
More informationThe 74LVC10A provides three 3-input NAND functions.
Triple 3-input NND gate Rev. 5 7 November 20 Product data sheet. General description The provides three 3-input NND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows
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Rev. 3 27 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
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Rev. 05 13 July 2009 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
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Rev. 03 20 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
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Rev. 6 0 November 20 Product data sheet. General description The provides six inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low wired-or
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Rev. 5 7 February 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. This device provides three inverting buffers with Schmitt trigger action. This device is capable
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Rev. 03 8 January 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4017. The is a 5-stage Johnson decade counter with
More information74LVC14A-Q100. Hex inverting Schmitt trigger with 5 V tolerant input
Rev. 2 10 June 2016 Product data sheet 1. General description The provides six inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined,
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Rev. 1 4 July 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NND gate with open-drain outputs. Inputs include clamp diodes that enable
More informationINTEGRATED CIRCUITS DATA SHEET. 74HC04; 74HCT04 Hex inverter. Product specification Supersedes data of 1993 Sep Jul 23
INTEGRTED CIRCUITS DT SHEET Supersedes data of 993 Sep 0 2003 Jul 23 FETURES Complies with JEDEC standard no. 8- ESD protection: HBM EI/JESD22-4- exceeds 2000 V MM EI/JESD22-5- exceeds 200 V. Specified
More informationDual JK flip-flop with reset; negative-edge trigger
Rev. 04 19 March 2008 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate MOS device that complies with JEDE standard no. 7. It is pin compatible with
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Rev. 1 11 November 2013 Product data sheet 1. General description The is a dual 2-input ND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to s in
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Rev. 03 6 September 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky
More information74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.
Rev. 1 2 November 2015 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. The provides two buffers. 2. Features and benefits 3. Ordering information Wide supply voltage
More information74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger
Rev. 4 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors
More information74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate
Rev. 4 17 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use
More information74HC1G32-Q100; 74HCT1G32-Q100
Rev. 1 8 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G32-Q100 and 74HCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input
More information74HC1G02-Q100; 74HCT1G02-Q100
Rev. 1 7 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G02-Q100 and 74HCT1G02-Q100 are high speed Si-gate CMOS devices. They provide a 2-input
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Rev. 2 11 February 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0
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Rev. 3 3 September 2012 Product data sheet 1. General description 2. Features and benefits The is a dual 4-input NND gate. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 02 18 October 2007 Product data sheet 1. General description 2. Features The is an octal -type transparent latch featuring separate -type inputs for each latch and 3-state true outputs for bus-oriented
More informationThe 74LV08 provides a quad 2-input AND function.
Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.
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Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops
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Rev. 4 8 November 2011 Product data sheet 1. General description The are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with
More information74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate
Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current
More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 07 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and
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Rev. 30 July 202 Product data sheet. General description The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
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Rev. 03 21 pril 2009 Product data sheet 1. General description 2. Features 3. pplications The is an 8 stage serial shift register with a storage register and 3-state outputs. Both the shift and storage
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Rev. 1 20 March 2013 Product data sheet 1. General description The is a triple 3-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators
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Rev. 06 5 November 2009 Product data sheet 1. General description The is a with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9),
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Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output
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Rev. 02 28 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is
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Rev. 1 18 November 2013 Product data sheet 1. General description The provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
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Rev. 6 2 September 20 Product data sheet. General description 2. Features and benefits 3. Ordering information Table. Ordering information Type number Package The provides four 2-input OR gates. Inputs
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Rev. 03 4 February 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164.
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Rev. 6 27 December 212 Product data sheet 1. General description 2. Features and benefits 3. pplications 74HC1G14 and 74HCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function
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Rev. 5 2 February 2016 Product data sheet 1. General description The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn causes the outputs
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