74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

Size: px
Start display at page:

Download "74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset"

Transcription

1 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The are dual retriggerable monostable multivibrators with output pulse width control by three methods: 1. The basic pulse time is programmed by selection of an external resistor (R EXT ) and capacitor (C EXT ). 2. Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (na) or the active HIGH-going edge input (nb). By repeating this process, the output pulse period (nq = HIGH, nq = LOW) can be made as long as desired. Alternatively an output delay can be terminated at any time by a LOW-going edge on input nrd, which also inhibits the triggering. 3. An internal connection from nrd to the input gates makes it possible to trigger the circuit by a HIGH-going signal at input nrd as shown in the function table. Schmitt-trigger action in the na and nb inputs, makes the circuit highly tolerant to slower input rise and fall times. The is identical to the 74HC423; 74HCT423 but can be triggered via the reset input. DC triggered from active HIGH or active LOW inputs Retriggerable for very long pulses up to 100 % duty factor Direct reset terminates output pulse Schmitt-trigger action on all inputs except for the reset input ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V Specified from 40 C to+85 C and from 40 C to +125 C

2 3. Ordering information Table 1. Type number Ordering information Package Temperature range Name Description Version 74HC123 74HC123N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil); long body 74HC123D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm 74HC123DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm 74HC123PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm 74HC123BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body mm 74HCT123 74HCT123N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil); long body 74HCT123D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm 74HCT123DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm 74HCT123PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT38-1 SOT109-1 SOT338-1 SOT403-1 SOT763-1 SOT38-1 SOT109-1 SOT338-1 SOT403-1 Product data sheet 2 of 28

3 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC V - ±20 ma I OK output clamping current V O < 0.5 V or V O >V CC V - ±20 ma I O output current except for pins nrext/cext; V O = 0.5 V to (V CC V) [1] For DIP16 package: P tot derates linearly with 12 mw/k above 70 C. [2] For SO16 package: P tot derates linearly with 8 mw/k above 70 C. [3] For SSOP16 and TSSOP16 packages: P tot derates linearly with 5.5 mw/k above 60 C. [4] For DHVQFN16 package: P tot derates linearly with 4.5 mw/k above 60 C. 8. Recommended operating conditions - ±25 ma I CC quiescent supply current - 50 ma I GND ground current - 50 ma T stg storage temperature C P tot total power dissipation DIP16 package [1] mw SO16 package [2] mw SSOP16 package [3] mw TSSOP16 package [3] mw DHVQFN16 package [4] mw Table 5. Recommended operating conditions 74HC123 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V t r, t f input rise and fall time nrd input V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns T amb ambient temperature C 74HCT123 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V t r, t f input rise and fall time nrd input; V CC = 4.5 V ns T amb ambient temperature C Product data sheet 7 of 28

4 9. Static characteristics Table 6. Static characteristics 74HC123 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). T amb =25 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I =V IH or V IL I O = 20 µa; V CC = 2.0 V V I O = 20 µa; V CC = 4.5 V V I O = 20 µa; V CC = 6.0 V V I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V V OL LOW-state output voltage V I =V IH or V IL I O =20µA; V CC = 2.0 V V I O =20µA; V CC = 4.5 V V I O =20µA; V CC = 6.0 V V I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±0.1 µa I CC quiescent supply current V I =V CC or GND; I O = 0 A; V CC = 6.0 V µa C i input capacitance pf T amb = 40 C to +85 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I =V IH or V IL I O = 20 µa; V CC = 2.0 V V I O = 20 µa; V CC = 4.5 V V I O = 20 µa; V CC = 6.0 V V I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V Product data sheet 8 of 28

5 Table 6. Static characteristics 74HC123 continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). V OL LOW-state output voltage V I =V IH or V IL I O =20µA; V CC = 2.0 V V I O =20µA; V CC = 4.5 V V I O =20µA; V CC = 6.0 V V I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±1.0 µa I CC quiescent supply current V I =V CC or GND; I O = 0 A; V CC = 6.0 V µa T amb = 40 C to +125 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I =V IH or V IL I O = 20 µa; V CC = 2.0 V V I O = 20 µa; V CC = 4.5 V V I O = 20 µa; V CC = 6.0 V V I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V V OL LOW-state output voltage V I =V IH or V IL I O =20µA; V CC = 2.0 V V I O =20µA; V CC = 4.5 V V I O =20µA; V CC = 6.0 V V I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±1.0 µa I CC quiescent supply current V I =V CC or GND; I O = 0 A; V CC = 6.0 V µa Table 7. Static characteristics 74HCT123 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). T amb =25 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O = 20 µa V I O = 4 ma V Product data sheet 9 of 28

6 Table 7. Static characteristics 74HCT123 continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). V OL LOW-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O =20µA V I O = 4.0 ma V I LI input leakage current V I =V CC or GND; V CC = 5.5 V - - ±0.1 µa I CC quiescent supply current V I =V CC or GND; I O = 0 A; V CC = 5.5 V µa I CC additional quiescent supply current per input pin; V I =V CC 2.1 V and other inputs at V CC or GND; I O =0A; V CC = 4.5 V to 5.5 V pins na, nb µa pin nrd µa C i input capacitance pf T amb = 40 C to +85 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O = 20 µa V I O = 4.0 ma V V OL LOW-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O =20µA V I O = 4.0 ma V I LI input leakage current V I =V CC or GND; V CC = 5.5 V - - ±1.0 µa I CC quiescent supply current V I =V CC or GND; I O = 0 A; V CC = 5.5 V µa I CC additional quiescent supply current per input pin; V I =V CC 2.1 V and other inputs at V CC or GND; I O =0A; V CC = 4.5 V to 5.5 V pins na, nb µa pin nrd µa T amb = 40 C to +125 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O = 20 µa V I O = 4 ma V V OL LOW-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O =20µA V I O = 4.0 ma V I LI input leakage current V I =V CC or GND; V CC = 5.5 V - - ±1.0 µa I CC quiescent supply current V I =V CC or GND; I O = 0 A; V CC = 5.5 V µa Product data sheet 10 of 28

7 Table 7. Static characteristics 74HCT123 continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). I CC additional quiescent supply current 10. Dynamic characteristics per input pin; V I =V CC 2.1 V and other inputs at V CC or GND; I O =0A; V CC = 4.5 V to 5.5 V pins na, nb µa pin nrd µa Table 8. Dynamic characteristics 74HC123 Voltages are referenced to GND (ground = 0 V); C L = 50 pf unless otherwise specified. For test circuit see Figure 12. T amb = 25 C t PHL, t PLH propagation delay C EXT = 0 pf; R EXT = 5 kω; see Figure 9 nrd, na, nb to nq or nq V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5 V; C L = 15 pf ns V CC = 6.0 V ns nrd (reset) to nq or nq V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5 V; C L = 15 pf ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W pulse width na LOW see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns nb HIGH see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns nrd LOW see Figure 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns nq HIGH and nq LOW V CC = 5.0 V; see Figure 10 and 11 [1] C EXT = 100 nf; R EXT = 10 kω µs C EXT = 0 pf; R EXT = 5 kω ns Product data sheet 11 of 28

8 Table 8. Dynamic characteristics 74HC123 continued Voltages are referenced to GND (ground = 0 V); C L = 50 pf unless otherwise specified. For test circuit see Figure 12. t rt retrigger time na, nb C EXT = 0 pf; R EXT = 5 kω; V CC = 5.0 V; see Figure 10 R EXT external timing resistor see Figure 7 [2][3] ns V CC = 2.0 V kω V CC = 5.0 V kω C EXT external timing capacitor V CC = 5.0 V; see Figure 7 [3] no limits pf C PD power dissipation capacitance per monostable [4][5] pf T amb = 40 C to +85 C t PHL, t PLH propagation delay C EXT = 0 pf; R EXT = 5 kω; see Figure 9 nrd, na, nb to nq or nq V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns nrd (reset) to nq or nq V CC = 2.0 V ns t THL, t TLH output transition time see Figure 9 t W pulse width na LOW see Figure 10 nb HIGH see Figure 10 nrd LOW see Figure 11 V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet 12 of 28

9 Table 8. Dynamic characteristics 74HC123 continued Voltages are referenced to GND (ground = 0 V); C L = 50 pf unless otherwise specified. For test circuit see Figure 12. T amb = 40 C to +125 C t PHL, t PLH propagation delay C EXT = 0 pf; R EXT = 5 kω; see Figure 9 nrd, na, nb to nq or nq V CC = 2.0 V ns [1] For other R EXT and C EXT combinations see Figure 7. If C EXT > 10 nf, the next formula is valid. t W =K R EXT C EXT, where: t W = typical output pulse width in ns; R EXT = external resistor in kω; C EXT = external capacitor in pf; K = constant = 0.45 for V CC = 5.0 V and 0.55 for V CC = 2.0 V. The inherent test jig and pin capacitance at pins 15 and 7 (nrext/cext) is approximately 7 pf. [2] The time to retrigger the monostable multivibrator depends on the values of R EXT and C EXT. The output pulse width will only be extended when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If C EXT >10 pf, the next formula (at V CC = 5.0 V) for the setup time of a retrigger pulse is valid: t rt = R EXT C EXT R EXT 1.05, where: t rt = retrigger time in ns; C EXT = external capacitor in pf; R EXT = external resistor in kω. The inherent test jig and pin capacitance at pins 15 and 7 (nrext/cext) is 7 pf. [3] When the device is powered-up, initiate the device via a reset pulse, when C EXT <50pF. V CC = 4.5 V ns V CC = 6.0 V ns nrd (reset) to nq or nq V CC = 2.0 V ns t THL, t TLH output transition time see Figure 9 t W pulse width na LOW see Figure 10 nb HIGH see Figure 10 nrd LOW see Figure 11 V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet 13 of 28

10 [4] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i + (C L V 2 CC f o ) C EXT V 2 CC f o +D 16 V CC where: f i = input frequency in MHz; f o = output frequency in MHz; D = duty factor in %; C L = output load capacitance in pf; V CC = supply voltage in V; C EXT = timing capacitance in pf; (C L V 2 CC f o ) sum of outputs. [5] The condition is V I = GND to V CC. Table 9. Dynamic characteristics 74HCT123 Voltages are referenced to GND (ground = 0 V); C L = 50 pf unless otherwise specified. For test circuit see Figure 12. T amb = 25 C t PHL propagation delay C EXT = 0 pf; R EXT = 5 kω; see Figure 9 nrd, na, nb to nq V CC = 4.5 V ns V CC = 5 V; C L =15pF ns nrd (reset) to nq V CC = 4.5 V ns V CC = 5 V; C L =15pF ns t PLH propagation delay C EXT = 0 pf; R EXT = 5 kω; see Figure 9 nrd, na, nb to nq V CC = 4.5 V ns V CC = 5 V; C L =15pF ns nrd (reset) to nq V CC = 4.5 V ns V CC = 5 V; C L =15pF ns t THL, t TLH output transition time V CC = 4.5 V; see Figure ns t W pulse width V CC = 4.5 V na LOW see Figure ns nb HIGH see Figure ns nrd LOW see Figure ns nq HIGH and nq LOW V CC = 5.0 V; see Figure 10 and 11 [1] C EXT = 100 nf; R EXT = 10 kω µs C EXT = 0 pf; R EXT = 5 kω ns t rt retrigger time na, nb C EXT = 0 pf; R EXT = 5 kω; V CC = 5.0 V; [2][3] ns see Figure 10 R EXT external timing resistor V CC = 5.0 V; see Figure kω C EXT external timing capacitor V CC = 5.0 V; see Figure 7 [3] no limits pf C PD power dissipation capacitance per monostable [4][5] pf T amb = 40 C to +85 C t PHL propagation delay C EXT = 0 pf; R EXT = 5 kω; see Figure 9 nrd, na, nb to nq V CC = 4.5 V ns nrd (reset) to nq V CC = 4.5 V ns Product data sheet 14 of 28

11 Table 9. Dynamic characteristics 74HCT123 continued Voltages are referenced to GND (ground = 0 V); C L = 50 pf unless otherwise specified. For test circuit see Figure 12. t PLH propagation delay C EXT = 0 pf; R EXT = 5 kω; see Figure 9 nrd, na, nb to nq V CC = 4.5 V ns nrd (reset) to nq V CC = 4.5 V ns t THL, t TLH output transition time V CC = 4.5 V ns t W pulse width V CC = 4.5 V T amb = 40 C to +125 C na LOW see Figure ns nb HIGH see Figure ns nrd LOW see Figure ns t PHL propagation delay C EXT = 0 pf; R EXT = 5 kω; see Figure 9 nrd, na, nb to nq V CC = 4.5 V ns nrd to nq (reset) V CC = 4.5 V ns t PLH propagation delay C EXT = 0 pf; R EXT = 5 kω; see Figure 9 nrd, na, nb to nq V CC = 4.5 V ns nrd to nq (reset) V CC = 4.5 V ns t THL, t TLH output transition time V CC = 4.5 V ns t W pulse width V CC = 4.5 V na LOW see Figure ns nb HIGH see Figure ns nrd LOW see Figure ns [1] For other R EXT and C EXT combinations see Figure 7. If C EXT > 10 nf, the next formula is valid. t W =K R EXT C EXT, where: t W = typical output pulse width in ns; R EXT = external resistor in kω; C EXT = external capacitor in pf; K = constant = 0.45 for V CC = 5.0 V, see Figure 8. The inherent test jig and pin capacitance at pins 15 and 7 (nrext/cext) is approximately 7 pf. [2] The time to retrigger the monostable multivibrator depends on the values of R EXT and C EXT. The output pulse width will only be extended when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If C EXT >10 pf, the next formula (at V CC = 5.0 V) for the setup time of a retrigger pulse is valid: t rt = R EXT C EXT R EXT 1.05, where: t rt = typical retrigger time in ns; C EXT = external capacitor in pf; R EXT = external resistor in kω. The inherent test jig and pin capacitance at pins 15 and 7 (nrext/cext) is 7 pf. [3] When the device is powered-up, initiate the device via a reset pulse, when C EXT <50pF. Product data sheet 15 of 28

12 [4] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i + (C L V 2 CC f o ) C EXT V 2 CC f o +D 16 V CC where: f i = input frequency in MHz; f o = output frequency in MHz; D = duty factor in %; C L = output load capacitance in pf; V CC = supply voltage in V; C EXT = timing capacitance in pf; (C L V 2 CC f o ) sum of outputs. [5] The condition is V I = GND to V CC 1.5 V aaa aaa612 t W (ns) 10 5 (1) (2) 'K' factor (3) (4) C EXT (pf) V CC (V) V CC = 5.0 V; T amb = 25 C. (1) R EXT = 100 kω (2) R EXT = 50 kω (3) R EXT = 10 kω (4) R EXT = 2 kω Fig 7. Typical output pulse width as a function of the external capacitor value Fig 8. C X = 10 nf; R X = 10 kω to 100 kω 74HCT123 typical K factor as function of V CC Product data sheet 16 of 28

13 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 D M E seating plane A 2 A L A 1 Z 16 e b b 1 9 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. A 1 A 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included w (1) Z max OUTLINE VERSION SOT38-1 REFERENCES IEC JEDEC JEITA 050G09 MO-001 SC EUROPEAN PROJECTION Fig 16. Package outline SOT38-1 (DIP16) Product data sheet 21 of 28

14 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y H E v M A Z 16 9 Q A 2 A 1 (A ) 3 A pin 1 index θ L p 1 8 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max A 1 A 2 A 3 b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION SOT E07 MS-012 Fig 17. Package outline SOT109-1 (SO16) Product data sheet 22 of 28

74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:

74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to: Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate

More information

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74HC393; 74HCT393. Dual 4-bit binary ripple counter Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified

More information

74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:

74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to: Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate

More information

74HC257; 74HCT257. Quad 2-input multiplexer; 3-state

74HC257; 74HCT257. Quad 2-input multiplexer; 3-state Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has four identical 2-input multiplexers with

More information

74HC238; 74HCT to-8 line decoder/demultiplexer

74HC238; 74HCT to-8 line decoder/demultiplexer Product data sheet 1. General description 2. Features 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders

More information

QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns. TYPICAL SYMBOL PARAMETER CONDITIONS 74HC00 74HCT00 UNIT

QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns. TYPICAL SYMBOL PARAMETER CONDITIONS 74HC00 74HCT00 UNIT FETURES Complies with JEDEC standard no. 8-1 ESD protection: HBM EI/JESD22-114- exceeds 2000 V MM EI/JESD22-115- exceeds 200 V Specified from 40 to +85 C and 40 to +125 C. DESCRIPTION The 74HC00/74HCT00

More information

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting. Product data sheet

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting. Product data sheet 3-to-8 line decoder, demultiplexer with address latches; inverting Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky

More information

QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns. TYPICAL SYMBOL PARAMETER CONDITIONS 74HC00 74HCT00 UNIT

QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns. TYPICAL SYMBOL PARAMETER CONDITIONS 74HC00 74HCT00 UNIT Quad 2-input NND gate FETURES Complies with JEDEC standard no. -1 ESD protection: HBM EI/JESD22-114- exceeds 2000 V MM EI/JESD22-115- exceeds 200 V Specified from 40 to +5 C and 40 to +125 C. DESCRIPTION

More information

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset Rev. 04 16 June 2006 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance

More information

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset Rev. 05 13 July 2009 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance

More information

74HC4051; 74HCT channel analog multiplexer/demultiplexer

74HC4051; 74HCT channel analog multiplexer/demultiplexer Product data sheet 1. General description 2. Features 3. Applications The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The device is specified in compliance

More information

74HC4067; 74HCT channel analog multiplexer/demultiplexer

74HC4067; 74HCT channel analog multiplexer/demultiplexer Product data sheet 1. General description 2. Features 3. Applications The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4067B. The device is specified in compliance with JEDEC standard

More information

74HC4053; 74HCT4053. Triple 2-channel analog multiplexer/demultiplexer

74HC4053; 74HCT4053. Triple 2-channel analog multiplexer/demultiplexer Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The is triple

More information

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 7 4 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device

More information

74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger

74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger Rev. 03 24 January 2006 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

More information

74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.

74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs. Rev. 03 31 January 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRTED CIRCUITS DT SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

74HC244; 74HCT244. Octal buffer/line driver; 3-state

74HC244; 74HCT244. Octal buffer/line driver; 3-state Rev. 03 22 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

More information

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74HC393; 74HCT393. Dual 4-bit binary ripple counter Rev. 03 6 September 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky

More information

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function. Rev. 03 September 200 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible

More information

INTEGRATED CIRCUITS DATA SHEET. 74HC04; 74HCT04 Hex inverter. Product specification Supersedes data of 1993 Sep Jul 23

INTEGRATED CIRCUITS DATA SHEET. 74HC04; 74HCT04 Hex inverter. Product specification Supersedes data of 1993 Sep Jul 23 INTEGRTED CIRCUITS DT SHEET Supersedes data of 993 Sep 0 2003 Jul 23 FETURES Complies with JEDEC standard no. 8- ESD protection: HBM EI/JESD22-4- exceeds 2000 V MM EI/JESD22-5- exceeds 200 V. Specified

More information

INTEGRATED CIRCUITS DATA SHEET. 74HC00; 74HCT00 Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 26.

INTEGRATED CIRCUITS DATA SHEET. 74HC00; 74HCT00 Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 26. INTEGRTED CIRCUITS DT SHEET Quad 2-input NND gate Supersedes data of 1997 ug 26 2003 Jun 30 Quad 2-input NND gate FETURES Complies with JEDEC standard no. 8-1 ESD protection: HBM EI/JESD22-114- exceeds

More information

74HC154; 74HCT to-16 line decoder/demultiplexer

74HC154; 74HCT to-16 line decoder/demultiplexer Rev. 06 2 February 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The

More information

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at   ore.hu. EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. INTEGRTED CIRCUITS DT SHEET Supersedes data of 1990 Dec 01 2003 Jul 25 FETURES

More information

74HC238; 74HCT to-8 line decoder/demultiplexer

74HC238; 74HCT to-8 line decoder/demultiplexer Rev. 03 16 July 2007 Product data sheet 1. General description 2. Features 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238

More information

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting 3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible

More information

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at   ore.hu. EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. INTEGRTED CIRCUITS DT SHEET Supersedes data of 1997 ug 26 2003 Oct 30 FETURES

More information

74AHC123A; 74AHCT123A

74AHC123A; 74AHCT123A Rev. 4 8 November 2011 Product data sheet 1. General description The are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with

More information

The 74HC21 provide the 4-input AND function.

The 74HC21 provide the 4-input AND function. Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).

More information

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function. Rev. 04 2 May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified

More information

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function. Rev. 02 5 November 2007 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

8-bit binary counter with output register; 3-state

8-bit binary counter with output register; 3-state Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It

More information

74HC594; 74HCT bit shift register with output register

74HC594; 74HCT bit shift register with output register Rev. 03 20 December 2006 Product data sheet 1. General description 2. Features 3. Applications The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The is

More information

74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function.

74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function. Quad 2-input NND gate Rev. 5 25 November 200 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard

More information

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses. Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance

More information

74HC4017; 74HCT4017. Johnson decade counter with 10 decoded outputs

74HC4017; 74HCT4017. Johnson decade counter with 10 decoded outputs Rev. 03 8 January 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4017. The is a 5-stage Johnson decade counter with

More information

74AHC14; 74AHCT14. Hex inverting Schmitt trigger

74AHC14; 74AHCT14. Hex inverting Schmitt trigger Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with

More information

74HC08; 74HCT General description. 2. Features and benefits. 3. Ordering information. Quad 2-input AND gate

74HC08; 74HCT General description. 2. Features and benefits. 3. Ordering information. Quad 2-input AND gate Quad 2-input ND gate Rev. 4 6 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input ND gate. Inputs include clamp diodes. This

More information

Hex inverting Schmitt trigger with 5 V tolerant input

Hex inverting Schmitt trigger with 5 V tolerant input Rev. 04 15 February 2005 Product data sheet 1. General description 2. Features 3. pplications The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible

More information

The 74LV32 provides a quad 2-input OR function.

The 74LV32 provides a quad 2-input OR function. Rev. 03 9 November 2007 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32.

More information

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function. Rev. 4 4 September 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS ogic Family Specifications The IC06 74HC/HCT/HCU/HCMOS ogic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting

74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance

More information

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state Rev. 04 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They

More information

8-bit serial-in/parallel-out shift register

8-bit serial-in/parallel-out shift register Rev. 03 4 February 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164.

More information

74HC4040; 74HCT stage binary ripple counter. Each counter stage is a static toggle flip-flop.

74HC4040; 74HCT stage binary ripple counter. Each counter stage is a static toggle flip-flop. Rev. 03 14 September 2005 Product data sheet 1. General description 2. Features 3. pplications 4. uick reference data he are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series.

More information

MM74HC175 Quad D-Type Flip-Flop With Clear

MM74HC175 Quad D-Type Flip-Flop With Clear Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity

More information

MM74HC157 Quad 2-Input Multiplexer

MM74HC157 Quad 2-Input Multiplexer Quad 2-Input Multiplexer General Description The MM74HC157 high speed Quad 2-to-1 Line data selector/multiplexers utilizes advanced silicon-gate CMOS technology. It possesses the high noise immunity and

More information

The 74LV08 provides a quad 2-input AND function.

The 74LV08 provides a quad 2-input AND function. Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0

More information

74HC164; 74HCT bit serial-in, parallel-out shift register

74HC164; 74HCT bit serial-in, parallel-out shift register Rev. 03 4 pril 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They

More information

74HC04; 74HCT General description. 2. Features and benefits. 3. Ordering information. Hex inverter

74HC04; 74HCT General description. 2. Features and benefits. 3. Ordering information. Hex inverter Rev. 4 3 ugust 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The is a hex inverter. The inputs include clamp diodes that enable the use of current limiting

More information

INTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook.

INTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook. INTEGRATED CIRCUITS Supersedes data of 1998 Apr 13 IC24 Data Handbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels

More information

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function. Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They

More information

74HC373; 74HCT General description. 2. Features. Octal D-type transparent latch; 3-state

74HC373; 74HCT General description. 2. Features. Octal D-type transparent latch; 3-state Rev. 03 20 January 2006 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with

More information

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate 8-input NND gate Rev. 6 27 December 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-input NND gate. Inputs include clamp diodes. This enables

More information

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device. Rev. 03 12 November 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The are octal non-inverting buffer/line drivers with 3-state

More information

MM74HC151 8-Channel Digital Multiplexer

MM74HC151 8-Channel Digital Multiplexer 8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation

More information

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device. Rev. 05 20 December 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The has octal non-inverting buffer/line drivers with 3-state

More information

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function. Rev. 3 27 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin

More information

74HC138; 74HCT to-8 line decoder/demultiplexer; inverting

74HC138; 74HCT to-8 line decoder/demultiplexer; inverting Rev. 4 27 June 2012 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The decoder accepts three binary weighted

More information

74HC08; 74HCT08. Temperature range Name Description Version. -40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.

74HC08; 74HCT08. Temperature range Name Description Version. -40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3. Rev. 6 13 June 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number Package The is a quad 2-input ND gate. Inputs include

More information

74HC259; 74HCT259. The 74HC259; 74HCT259 has four modes of operation:

74HC259; 74HCT259. The 74HC259; 74HCT259 has four modes of operation: Rev. 5 7 ugust 202 Product data sheet. General description The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC

More information

74HC32-Q100; 74HCT32-Q100

74HC32-Q100; 74HCT32-Q100 Rev. 1 1 ugust 2012 Product data sheet 1. General description The is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages

More information

74HC74-Q100; 74HCT74-Q100

74HC74-Q100; 74HCT74-Q100 Rev. 3 4 December 2015 Product data sheet 1. General description The are dual positive edge triggered D-type flip-flop with individual data (nd), clock (ncp), set (nsd) and reset (nrd) inputs, and complementary

More information

74HC08-Q100; 74HCT08-Q100

74HC08-Q100; 74HCT08-Q100 Rev. 1 16 July 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC08-Q100; 7 4HCT08-Q100 is a quad 2-input ND gate. Inputs include clamp diodes. This

More information

INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.

INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook. INTEGRATED CIRCUITS Supersedes data of 1997 May 15 IC24 Data Handbook 1998 Jun 23 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for low voltage applications: 1.0V to 3.6V Accepts TTL input levels

More information

74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger

74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger Rev. 4 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

74AHC594-Q100; 74AHCT594-Q100

74AHC594-Q100; 74AHCT594-Q100 74HC594-Q100; 74HCT594-Q100 Rev. 2 4 July 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified

More information

74LV General description. 2. Features. 8-bit addressable latch

74LV General description. 2. Features. 8-bit addressable latch Rev. 03 2 January 2008 Product data sheet. General description 2. Features The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The is a high-speed designed

More information

74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate

74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate Rev. 3 3 September 2012 Product data sheet 1. General description 2. Features and benefits The is a dual 4-input NND gate. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

INTEGRATED CIRCUITS. 74ALS11A Triple 3-Input AND gate. Product specification 1991 Feb 08 IC05 Data Handbook

INTEGRATED CIRCUITS. 74ALS11A Triple 3-Input AND gate. Product specification 1991 Feb 08 IC05 Data Handbook INTEGRATED CIRCUITS Triple 3-Input AND gate 1991 Feb 08 IC05 Data Handbook TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 5.5ns 1.3mA PIN CONFIGURATION 1A 1 1B 2 14 13 V CC 1C ORDERING INFORMATION

More information

74HC373-Q100; 74HCT373-Q100

74HC373-Q100; 74HCT373-Q100 Rev. 1 10 August 2012 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

INTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook

INTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook INTEGRATED CIRCUITS Octal D-type flip-flop with reset; positive-edge trigger 1997 Apr 07 IC24 Data Handbook FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V

More information

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger Rev. 4 8 pril 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and

More information

NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs

NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that

More information

MM74HC164 8-Bit Serial-in/Parallel-out Shift Register

MM74HC164 8-Bit Serial-in/Parallel-out Shift Register 8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

INTEGRATED CIRCUITS. For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications INTEGRTED CIRCUITS DT SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications Dual D-type flip-flop with set and reset; Supersedes data of September

More information

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate Rev. 4 17 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use

More information

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74HC393; 74HCT393. Dual 4-bit binary ripple counter Rev. 5 1 pril 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC393; 7474HCT393 is a dual 4-stage binary ripple counter. Each counter features a clock

More information

74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.

74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver. 16-bit dual supply translating transciever; 3-state Rev. 02 1 June 2004 Product data sheet 1. General description 2. Features The is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior

More information

Dual 2-to-4 line decoder/demultiplexer

Dual 2-to-4 line decoder/demultiplexer 74LV9 Rev. 04 December 007 Product data sheet. General description. Features. Ordering information The 74LV9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC9 and 74HCT9.

More information

74LVU General description. 2. Features. 3. Applications. Hex inverter

74LVU General description. 2. Features. 3. Applications. Hex inverter Rev. 06 20 December 2007 Product data sheet. General description 2. Features 3. pplications The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HCU04. The is a general purpose

More information

MM74HC175 Quad D-Type Flip-Flop With Clear

MM74HC175 Quad D-Type Flip-Flop With Clear Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity

More information

74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer

74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer Rev. 5 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each

More information

74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:

74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation: Rev. 02 15 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance

More information

MM74HC00 Quad 2-Input NAND Gate

MM74HC00 Quad 2-Input NAND Gate MM74HC00 Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption

More information

74AHC14-Q100; 74AHCT14-Q100

74AHC14-Q100; 74AHCT14-Q100 Rev. 9 July 202 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard

More information

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register

NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type package

More information

74HC4060-Q100; 74HCT4060-Q100

74HC4060-Q100; 74HCT4060-Q100 74HC4060-Q100; 74HCT4060-Q100 Rev. 2 10 pril 2013 Product data sheet 1. General description The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible with Low-power

More information

NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset

NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP

More information

74AHC30-Q100; 74AHCT30-Q100

74AHC30-Q100; 74AHCT30-Q100 Rev. 1 20 November 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky

More information

INTEGRATED CIRCUITS DATA SHEET. FAMILY SPECIFICATIONS HCMOS family characteristics. File under Integrated Circuits, IC06

INTEGRATED CIRCUITS DATA SHEET. FAMILY SPECIFICATIONS HCMOS family characteristics. File under Integrated Circuits, IC06 INTEGRTED CIRCUITS DT SHEET FMILY SPECIFICTIONS HCMOS family characteristics File under Integrated Circuits, IC06 March 1988 INTEGRTED CIRCUITS DT SHEET Package outline drawings File under Integrated Circuits,

More information

MM74HCT08 Quad 2-Input AND Gate

MM74HCT08 Quad 2-Input AND Gate MM74HCT08 Quad 2-Input AND Gate General Description The MM74HCT08 is a logic function fabricated by using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS low quiescent

More information

74LV393 Dual 4-bit binary ripple counter

74LV393 Dual 4-bit binary ripple counter INTEGRATED CIRCUITS Supersedes data of 1997 Mar 04 IC24 Data Handbook 1997 Jun 10 FEATURES Optimized for Low Voltage applications: 1.0 to.6v Accepts TTL input levels between V CC = 2.7V and V CC =.6V Typical

More information

INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook

INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook INTEGRATED CIRCUITS 1998 Jun 23 IC24 Data Handbook FEATURES Optimized for Low Voltage applications: 1.0 to 5.5V Accepts TTL input levels between V CC = 2.7V and V CC = 3.6V Typical V OLP (output ground

More information

74HC164; 74HCT bit serial-in, parallel-out shift register

74HC164; 74HCT bit serial-in, parallel-out shift register Rev. 8 19 November 2015 Product data sheet 1. General description The is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs

More information

14-stage binary ripple counter

14-stage binary ripple counter Rev. 01 29 November 2005 Product data sheet 1. General description 2. Features 3. pplications he is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HC4020.

More information