INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic Package Outlines 74C/CT4511 BCD to 7-segment latch/decoder/driver File under Integrated Circuits, IC6 December 199

2 74C/CT4511 FEATURES atch storage of BCD inputs Blanking input amp test input Driving common cathode ED displays Guaranteed 1 ma drive capability per output Output capability: non-standard I CC category: MSI GENERA DESCRIPTION The 74C/CT4511 are high-speed Si-gate CMOS devices and are pin compatible with 4511 of the 4B series. They are specified in compliance with JEDEC standard no. 7A. The 74C/CT4511 are BCD to 7-segment latch/decoder/drivers with four address inputs (D 1 to D 4 ), an active OW latch enable input (E), an active OW ripple blanking input (BI), an active OW lamp test input (T), and seven active IG segment outputs (Q a to Q g ). When E is OW, the state of the segment outputs (Q a to Q g ) is determined by the data on D 1 to D 4. When E goes IG, the last data present on D 1 to D 4 are stored in the latches and the segment outputs remain stable. When T is OW, all the segment outputs are IG independent of all other input conditions. With T IG, a OW on BI forces all segment outputs OW. The inputs T and BI do not affect the latch circuit. APPICATIONS Driving ED displays Driving incandescent displays Driving fluorescent displays Driving CD displays Driving gas discharge displays QUICK REFERENCE DATA GND = V; T amb =25 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P propagation delay C = 15 pf; V CC =5 V D n to Q n ns E to Q n ns BI to Q n 19 2 ns T to Q n ns C I input capacitance pf C PD power dissipation capacitance per latch notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V December 199 2

3 74C/CT4511 ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 3 T lamp test input (active OW) 4 BI ripple blanking input (active OW) 5 E latch enable input (active OW) 7, 1, 2, 6 D 1 to D 4 BCD address inputs 8 GND ground ( V) 13, 12, 11, 1, 9, 15, 14 Q a to Q g segments outputs 16 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December 199 3

4 December Philips Semiconductors 74C/CT4511 FUNCTION TABE Note 1. Depends upon the BCD-code applied during the OW-to-IG transition of E. = IG voltage level = OW voltage level X = don t care INPUTS OUTPUTS DISPAY E BI T D 4 D 3 D 2 D 1 Q a Q b Q c Q d Q e Q f Q g X X X X X X 8 X X X X X blank blank blank blank blank blank blank X X X X (1) (1) Fig.4 Functional diagram.

5 74C/CT4511 Fig.5 ogic diagram. Fig.6 Segment designation. Fig.7 Display. December 199 5

6 74C/CT4511 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard, excepting V O which is given below I CC category: MSI Non-standard DC characteristics for 74C Voltages are referenced to GND (ground = V) SYMBO PARAMETER V O IG level output voltage V O IG level output voltage T amb ( C) 74C to to +125 min. typ. max. min. max. min. max UNIT V CC (V) TEST CONDITIONS V I I O (ma) V V I or 7.5 V I 1. V 6. V I or 7.5 V I December 199 6

7 74C/CT4511 AC CARACTERISTICS FOR 74C GND = V; t r =t f = 6 ns; C = 5 pf SYMBO t P / t P t P / t P t P / t P t P / t P PARAMETER propagation delay 77 D n to Q n propagation delay 74 E to Q n propagation delay 61 BI to Q n propagation delay 41 T to Q n t T / t T output transition time t W t su t h latch enable pulse width OW set-up time D n to E hold time D n to E T amb ( C) 74C to to +125 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) ns ns ns ns ns ns ns ns WAVEFORMS Fig.8 Fig.9 Fig.1 Fig.8 Figs 8, 9 and 1 Fig.9 Fig.11 Fig.11 December 199 7

8 74C/CT4511 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard, excepting V O which is given below I CC category: MSI Non-standard DC characteristics for 74CT Voltages are referenced to GND (ground = V) SYMBO PARAMETER V O IG level output voltage T amb ( C) 74CT to to +125 min. typ. max. min. max. min. max UNIT V CC (V) TEST CONDITIONS V I I O (ma) V V I or V I Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT OAD COEFFICIENT T, E 1.5 BI, D n.3 December 199 8

9 74C/CT4511 AC CARACTERISTICS FOR 74CT GND = V; t r =t f = 6 ns; C = 5 pf T amb ( C) TEST CONDITIONS ns Fig ns Fig ns Fig ns Fig.8 74CT SYMBO PARAMETER UNIT V WAVEFORMS to to +125 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay D n to Q n t P / t P propagation delay E to Q n t P / t P propagation delay BI to Q n t P / t P propagation delay T to Q n t T / t T output transition time ns Figs 8, 9 and 1 t W latch enable pulse ns Fig.9 width OW t su t h set-up time D n to E hold time D n to E ns Fig.11 4 ns Fig.11 December 199 9

10 74C/CT4511 AC WAVEFORMS (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.8 Waveforms showing the input (D n, T) to output (Q n ) propagation delays and the output transition times. Fig.9 Waveforms showing the input (E) to output (Q n ) propagation delays and the latch enable pulse width. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.1 Waveforms showing the input (BI) to output (Q n ) propagation delays. Fig.11 Waveforms showing the data set-up and hold times for D n input to E input. December 199 1

11 74C/CT4511 APPICATION DIAGRAMS Fig.12 Connection to common cathode ED display readout. Fig.13 Connection to common anode ED display readout. (1) A filament pre-warm resistor to reduce thermal shock and to increase effective cold resistance of the filament is recommended. Fig.14 Connection to incandescent display readout. Fig.15 Connection to fluorescent display readout. Fig.16 Connection to gas discharge display readout. Fig.17 Connection to CD display readout. (Direct DC drive is not recommended as it can shorten the life of CD displays). December

12 74C/CT4511 PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December

13 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & ifecycle Information: NXP: 74C4511D,652 74C4511D,653 74C4511N,652 74CT4511N,652

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Important notice Dear Customer, On 7 February 217 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, ogic and