INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specificatio The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 14-stage binary ripple counter with oscillator File under Integrated Circuits, IC06 December 1990

2 FEATURES All active components on chip RC or crystal oscillator configuration Output capability: stard (except for R TC C TC ) I CC category: MSI GENERAL DESCRIPTION The are high-speed Si-gate CMOS devices are pin compatible with 4060 of the 4000B series. They are specified in compliance with JEDEC stard no. 7A. The are 14-stage ripple-carry counter/dividers oscillators with three oscillator terminals (RS, R TC C TC ), ten buffered outputs (Q 3 to Q 9 Q 11 to Q 13 ) an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case keep the other oscillator pi (R TC C TC ) floating. The counter advances on the negative-going traition of RS. A HIGH level on MR resets the counter (Q 3 to Q 9 Q 11 to Q 13 = LOW), independent of other input conditio. In the HCT version, the MR input is TTL compatible, but the RS input has CMOS input switching levels can be driven by a TTL output by using a pull-up resistor to V CC. QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 TYPICAL SYMBOL PARAMETER CONDITIONS HC HCT UNIT t PHL/ t PLH propagation delay C L = 15 pf; V CC =5 V RS to Q Q n to Q n t PHL MR to Q n f max maximum clock frequency MHz C I input capacitance pf C PD power dissipation capacitance per package notes 1, pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in MHz f o = output frequency in MHz (C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf V CC = supply voltage in V 2. For HC the condition is V I = GND to V CC For HCT the condition is V I = GND to V CC 1.5 V 3. For formula on dynamic power dissipation see next pages. ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December

3 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 2, 3 Q 11 to Q 13 counter outputs 7, 5, 4, 6, 14, 13, 15 Q 3 to Q 9 counter outputs 8 GND ground (0 V) 9 C TC external capacitor connection 10 R TC external resistor connection 11 RS clock input/oscillator pin 12 MR master reset 16 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December

4 DYNAMIC POWER DISSIPATION FOR 74HC PARAMETER V CC (V) TYPICAL FORMULA FOR P D (µw) (note 1) total dynamic power dissipation when using the on-chip oscillator (P D ) Note 1. GND = 0 V; T amb =25 C C PD f osc V 2 CC + (C L V 2 CC f o ) + 2C t V 2 CC f osc + 60 V CC C PD f osc V 2 CC + (C L V 2 CC f o ) + 2C t V 2 CC f osc V CC C PD f osc V 2 CC + (C L V 2 CC f o ) + 2C t V 2 CC f osc V CC DYNAMIC POWER DISSIPATION FOR 74HCT PARAMETER V CC (V) TYPICAL FORMULA FOR P D (µw) (note 1) total dynamic power dissipation when using the on-chip oscillator (P D ) C PD f osc V 2 CC + (C L V 2 CC f o ) + 2C t V 2 CC f osc V CC Notes 1. GND = 0 V; T amb =25 C 2. Where: f o = output frequency in MHz f osc = oscillator frequency in MHz (C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf C t = timing capacitance in pf V CC = supply voltage in V Fig.4 Functional diagram. APPLICATIONS Control counters Timers Frequency dividers Time-delay circuits December

5 Fig.5 Logic diagram. Fig.6 Timing diagram. December

6 DC CHARACTERISTICS FOR 74HC Output capability: stard (except for R TC C TC ) I CC category: MSI Voltages are referenced to GND (ground = 0 V) T amb ( C) TEST CONDITIONS SYM- BOL PARAMETER 74HC to to +125 UNIT V CC (V) V I OTHER min. typ. max. min. max. min. max. V IH HIGH level input voltage MR input V V IL LOW level input voltage MR input V V IH HIGH level input voltage RS input V V IL LOW level input voltage RS input V R TC output V RS=GND MR=GND I O = 2.6 ma I O = 3.3 ma V RS=V CC MR=V CC I O = 0.65 ma I O = 0.85 ma V RS=GND MR=GND V RS=V CC MR=V CC C TC output V RS=V IH MR=V IL I O = 3.2 ma I O = 4.2 ma except R TC output V V IH or V IL except R TC C TC outputs V V IH or V IL I O = 4.0 ma I O = 5.2 ma R TC output RS=V CC MR=GND I O = 2.6 ma I O = 3.3 ma V RS=V CC MR=GND I O =µa I O =µa I O =µa December

7 T amb ( C) TEST CONDITIONS SYM- BOL PARAMETER 74HC to to +125 UNIT V CC (V) V I OTHER min. typ. max. min. max. min. max. C TC output V RS=V IL MR=V IH I O = 3.2 ma I O = 4.2 ma except R TC output V V IH or V IL I O =µa I O =µa I O =µa except R TC C TC outputs V V IH or V IL I O = 4.0 ma I O = 5.2 ma ±I I input leakage current µa V CC or GND I CC quiescent supply current µa V CC or GND I O =0 December

8 AC CHARACTERISTICS FOR 74HC GND = 0 V; t r =t f = 6 ; C L = 50 pf T amb ( C) TEST CONDITIONS SYMBOL PARAMETER 74HC to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t PHL / t PLH t PHL / t PLH t PHL t THL / t TLH t W t W t rem f max 99 propagation delay 36 RS to Q propagation delay 8 Q n to Q n propagation delay MR to Q n 16 output traition time clock pulse width RS; HIGH or LOW master reset pulse width MR; HIGH removal time MR to RS maximum clock pulse frequency MHz Fig.12 Fig.14 Fig.13 Fig.12 Fig.12 Fig.13 Fig.13 Fig.12 December

9 December DC CHARACTERISTICS FOR 74HCT Output capability: stard (except for R TC C TC ) I CC category: MSI Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER T amb ( C) 74HCT to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) V I TEST CONDITIONS OTHER V IH HIGH level input voltage V to 5.5 note 2 V IL LOW level input voltage V to 5.5 note V RS=GND MR=GND I O = 2.6 ma R TC output V RS = V CC MR = V CC I O = 0.65 ma C TC output except R TC output except R TC C TC outputs R TC output C TC output except R TC output V RS=GND MR=GND V RS=V CC MR=V CC V RS = V IH MR = V IL I O = 3.2 ma V V IH or V IL V V IH or V IL I O = 4.0 ma V RS=V CC MR=GND I O = 2.6 ma 0 V RS=V CC MR=GND I O =µa V RS = V IL MR = V IH I O = 3.2 ma 0 V V IH or V IL I O =µa V V IH or V IL I O = 4.0 ma except R TC C TC outputs ±I input leakage current µa 5.5 V CC or GND I CC quiescent supply current µa 5.5 V CC or GND I O =0 I CC additional quiescent supply current per input pin for unit load coefficient is 1 (note 1) µa to 5.5 V CC 2.1 V other inputs at V CC or GND; I O =0 14-stage binary ripple counter with oscillator Philips Semiconductors

10 Notes 1. The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given here. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. 2. Only input MR (pin 12) has TTL input switching levels for the HCT versio. INPUT UNIT LOAD COEFFICIENT MR 0.40 AC CHARACTERISTICS FOR 74HCT GND = 0 V; t r =t f = 6 ; C L = 50 pf T amb ( C) TEST CONDITIONS Fig Fig Fig.13 74HCT SYMBOL PARAMETER UNIT V WAVEFORMS to to +125 CC (V) min. typ. max. min. max. min. max. t PHL / t PLH propagation delay RS to Q 3 t PHL / t PLH propagation delay Q n to Q n+1 t PHL propagation delay MR to Q n t THL / t TLH output traition time Fig.12 t W t W t rem f max clock pulse width RS; HIGH or LOW master reset pulse width MR; HIGH removal time MR to RS maximum clock pulse frequency Fig Fig Fig MHz Fig.12 December

14 hbook, g halfpage fs (ma/v) 12 10 max. MBA333 typ. 8 min. 6 4 Fig.7 Test set-up for measuring forward traconductance g fs =di o / dv i at v o is cotant (see also graph Fig.8); MR = LOW. Fig.8 2 0 1 2 3 4 5 6 V CC (V) Typical forward traconductance g fs as a function of the supply voltage V CC at T amb =25 C.

11 14 hbook, g halfpage fs (ma/v) max. MBA333 typ. 8 min. 6 4 Fig.7 Test set-up for measuring forward traconductance g fs =di o / dv i at v o is cotant (see also graph Fig.8); MR = LOW. Fig V CC (V) Typical forward traconductance g fs as a function of the supply voltage V CC at T amb =25 C. RC OSCILLATOR Fig.9 RC oscillator frequency as a function of R t C t at V CC = to V; T amb =25 C. C t curve at R t = 100 kω; R2 = 0 kω. R t curve at C t = 1 nf; R2 = 2 R t. Typical formula for oscillator frequency: 1 f osc = R t C t Fig.10 Example of a RC oscillator. TIMING COMPONENT LIMITATIONS The oscillator frequency is mainly determined by R t C t, provided R2 2R t R2C2 << R t C t. The function of R2 is to minimize the influence of the forward voltage across the input protection diodes on the frequency. The stray capacitance C2 should be kept as small as possible. In coideration of accuracy, C t must be larger than the inherent stray capacitance. R t must be larger than the ON resistance in series with it, which typically is 280 Ω at V CC = V, 130 Ω at V CC = V 100 Ω at V CC = V. The recommended values for these components to maintain agreement with the typical oscillation formula are: C t > 50 pf, up to any practical value, 10 kω <R t <1 MΩ. In order to avoid start-up problems, R t 1 kω. December

12 TYPICAL CRYSTAL OSCILLATOR In Fig.11, R2 is the power limiting resistor. For starting maintaining oscillation a minimum traconductance is necessary, so R2 should not be too large. A practical value for R2 is 2.2 kω. Fig.11 External components connection for a crystal oscillator. AC WAVEFORMS (1) HC : V M = 50%; V I = GND to V CC. HCT: V M = 1.3 V; V I = GND to 3 V. Fig.12 Waveforms showing the clock (RS) to output (Q 3 ) propagation delays, the clock pulse width, the output traition times the maximum clock frequency. (1) HC : V M = 50%; V I = GND to V CC. HCT: V M = 1.3 V; V I = GND to 3 V. Fig.13 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q n ) propagation delays the master reset to clock (RS) removal time. (1) HC : V M = 50%; V I = GND to V CC. HCT: V M = 1.3 V; V I = GND to 3 V. Fig.14 Waveforms showing the output (Q n ) to Q n+1 propagation delays. PACKAGE OUTLINES See 74HC/HCT/HCU/HCMOS Logic Package Outlines. December

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC6 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC6 74HC/HCT/HCU/HCMOS Logic Package Information The IC6 74HC/HCT/HCU/HCMOS