Up/down binary counter with separate up/down clocks

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1 FEATURES Synchronous reversible 4-bit counting Asynchronous parallel load capability Asynchronous reset (clear) Cascadable without external logic DESCRIPTION The is a 4-bit synchronous up/down counter in the binary mode. Separate up/down clocks, U and D respectively, simplify operation. The outputs change state synchronously with the Low-to-High traition of either clock input. If the U clock is pulsed while D is held High, the device will count up. If D clock is pulsed while U is held High, the device will count down. The device can be cleared at any time by the asynchronous reset pin. It may also be loaded in parallel by activating the asynchronous parallel load pin. Iide the device are four master-slave K flip-flops with the necessary steering logic to provide the asynchronous reset, asynchronous preset, load, and synchronous count up and count down functio. Each flip-flop contai K feedback from slave to master, such that a Low-to-High traition on the D input will decrease the count by one, while a similar traition on the U input will advance the count by one. One clock should be held High while counting with the other, because the circuit will either count by twos or not at all, depending on the state of the first K flip-flop, which cannot toggle as long as either clock input is Low. Applicatio requiring reversible operation must make the reversing decision while the activating clock is High to avoid erroneous counts. The Terminal Count Up ( ) and Terminal Count Down ( ) outputs are normally High. When the circuit has reached the maximum count state of 1, the next High-to-Low traition of U will cause to go Low. will stay Low until U goes High again, duplicating the count up clock, although delayed by two gate delays. Likewise, the output will go Low when the circuit is in the zero state and the D goes Low. The TC outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous since there is a two-gate delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel Data inputs (D0 - D) is loaded into the counter and appears on the outputs regardless of the conditio of the clock inputs when the Parallel Load () input is Low. A High level on the Master Reset () input will disable the parallel load gates, override both clock inputs, and set all outputs Low. If one of the clock inputs is Low during and after a reset or load operation, the next Low-to-High traition of the clock will be interpreted as a legitimate signal and will be counted. TYPE TYPICAL f MAX SUPY CURRENT TYPICAL (TOTAL) MHz ma ORDERING INFORMATION DESCRIPTION 1-pin plastic DIP 1-pin plastic SO PIN CONFIGURATION D1 1 0 D U GND COMMERCIAL RANGE V CC = V ±%, T amb = 0 C to +0 C 1 1 NN ND V CC D0 D D SF004 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 4F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 - D Data inputs 1.0/1.0 0µA/0.mA U Count up clock input (active rising edge) 1.0/.0 0µA/1.8mA D Count down clock input (active rising edge) 1.0/.0 0µA/1.8mA Asynchronous parallel load control input (active Low) 1.0/1.0 0µA/0.mA Asynchronous master reset input 1.0/1.0 0µA/0.mA 0 - Flip-flop outputs 0/ 1.0mA/0mA Terminal count up (carry) output (active Low) 0/ 1.0mA/0mA Terminal count down (borrow) output (active Low) 0/ 1.0mA/0mA NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 0µA in the High state and 0.mA in the Low state. 1 ul

2 LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 1 1 D0 D1 D D U 4 D 4 C + G1 1 G R CTIV 1 1CT=1 CT=0 V CC = Pin 1 GND = Pin SF D [1] [] [4] [8] SF004 STATE DIAGRAM COUNT UP COUNT DOWN = U = D Logic Equatio for Terminal Count SF ul 1

3 LOGIC DIAGRAM D0 D1 D D 1 1 U D 4 K K K V CC = Pin 1 GND = Pin SF004 FUNCTION TABLE INPUTS OUTPUTS OPERATING U D D0 D1 D D 0 1 MODE H X X L X X X X L L L L H L Reset (clear) H X X H X X X X L L L L H H L L X L L L L L L L L L H L L L X H L L L L L L L L H H Parallel load L L L X H H H H H H H H L H L L H X H H H H H H H H H H L H H X X X X Count up H 1 H Count up L H H X X X X Count down H H Count down H = High voltage level L = Low voltage level X = Don t care = Low-to-High clock traition NOTES: 1. = U at terminal count up (HHHH). = D at terminal count down (LLLL) 1 ul 1

4 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING V CC Supply voltage 0. to +.0 V V IN Input voltage 0. to +.0 V I IN Input current 0 to + ma V OUT Voltage applied to output in High output state 0. to +V CC V I OUT Current applied to output in Low output state 40 ma T amb Operating free-air temperature range 0 to +0 C T stg Storage temperature to + C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER MIN NOM MAX V CC Supply voltage. V V IH High-level input voltage V V IL Low-level input voltage 0.8 V I IK Input clamp current 18 ma I OH High-level output current 1 ma I OL Low-level output current 0 ma T amb Operating free-air temperature range 0 +0 C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP MAX V OH V OL High-level output voltage Low-level output voltage V CC MIN, V IL MAX, %V CC. V I OH = MAX, V IH = MIN %V CC..4 V V CC MIN, V IL MAX, %V CC V I OL = MAX, V IH = MIN %V CC V V IK Input clamp voltage V CC = MIN, I I = I IK V I I Input current at maximum input voltage V CC = MAX, V I =.0V 0 µa I IH High-level input current V CC = MAX, V I =.V 0 µa I IL Low-level input U, D V current CC = MAX, V I = 0.V Others 1.8 ma 0. ma I OS Short-circuit output current V CC = MAX 0 ma I CC Supply current (total) 4 V CC = MAX 0 ma NOTES: 1. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type.. All typical values are at V CC = V, T amb = C.. Not more than one output should be shorted at a time. For testing I OS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I OS tests should be performed last. 4. Measure I CC with parallel load and Master reset inputs grounded, all other inputs at V and all outputs open. 1 ul 1 4

5 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS T amb = + C V CC = +V C L = 0pF, R L = 00Ω T amb = 0 C to +0 C V CC = +V ± % C L = 0pF, R L = 00Ω MIN TYP MAX MIN MAX f MAX Maximum clock frequency Waveform MHz U or D to or Waveform U or D to n D n to n to n to n Waveform 1 Waveform 4 Waveform Waveform..0 1 to Waveform 1..0 to Waveform..0 1 to or Waveform Dn to or Waveform 4 AC SETUP REUIREMENTS SYMBOL PARAMETER TEST CONDITIONS t s (H) t s (L) t h (H) t h (L) t w (L) t w (H) t w (L) t w (L) t w (H) Setup time, High or Low Dn to Hold time, High or Low Dn to Pulse width Low U or D Pulse width High or Low U or D Pulse width Low (Change of direction) Pulse width High Waveform Waveform T amb = + C V CC = +V C L = 0pF, R L = 00Ω T amb = 0 C to +0 C V CC = +V ± % C L = 0pF, R L = 00Ω MIN TYP MAX MIN MAX Waveform Waveform 1.. Waveform Waveform Recovery time, to U or D Waveform Recovery time to U or D Waveform ul 1

6 AC WAVEFORMS For all waveforms Vm = 1.V 1/f MAX t W (L) U, D U, D t W (H), n VM SF00 SF000 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width and Maximum Clock Frequency Waveform. Propagation Delay, Clock to Terminal Count t W (L) Dn n,, U, D n,,,, n Waveform. Parallel Pulse Width, Parallel Load to Output Delays, and Parallel Load to Clock Recovery Time SF001 SF004 Waveform 4. Propagation Delay, Data to Flip-Flop Outputs, Terminal Count Up and Down Outputs Dn t S (H) t h (H) t S (L) t h (L) t W (H) U, D The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform. Data Setup and Hold Times SF00 n, SF00 Waveform. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time 1 ul 1

7 Timing Diagram (Typical clear, load, and count sequence) CLEAR 1 LOAD D0 D1 DATA D D COUNT UP U COUNT DOWN D 0 OUTPUTS 1 SEUENCE COUNT UP COUNT DOWN CLEAR PRESET NOTES: 1. Clear overrides load, data, and count inputs.. When counting up, count-down input must be High; when counting down, count-up input must be High. SF00 Binary Counter TEST CIRCUIT AND WAVEFORMS PULSE GENERATOR V IN V CC D.U.T. V OUT NEGATIVE PULSE 0% % t THL ( t f ) t w t TLH ( t r ) % 0% AMP (V) 0V R T C L R L Test Circuit for Totem-Pole Outputs POSITIVE PULSE % 0% t TLH ( t r ) t w t THL ( t f ) 0% % AMP (V) 0V DEFINITIONS: R L = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. R T = Termination resistance should be equal to Z OUT of pulse generators. family 4F Input Pulse Definition INPUT PULSE REUIREMENTS amplitude rep. rate t w t TLH t THL.0V 1.V 1MHz 00.. SF ul 1

INTEGRATED CIRCUITS. 74ALS11A Triple 3-Input AND gate. Product specification 1991 Feb 08 IC05 Data Handbook

INTEGRATED CIRCUITS. 74ALS11A Triple 3-Input AND gate. Product specification 1991 Feb 08 IC05 Data Handbook INTEGRATED CIRCUITS Triple 3-Input AND gate 1991 Feb 08 IC05 Data Handbook TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 5.5ns 1.3mA PIN CONFIGURATION 1A 1 1B 2 14 13 V CC 1C ORDERING INFORMATION