CONDITIONS T amb = 25 C; GND = 0V. C L = 50pF; V CC = 5V 4.4 ns. Outputs disabled; V O = 0V or V CC

Transcription

1 9-bit -type flip-flop with reset and enable FEATUES High speed parallel registers with positive edge-triggered -type flip-flops Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors Output capability: +6mA/ 2mA Latch-up protection exceeds 00mA per Jedec Std 7 ES protection exceeds 2000 V per MIL ST 88 Method 0 and 200 V per Machine Model Power-up -State Power-up eset ESCIPTION The Bus interface egister is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The is a 9-bit wide buffered register with Clock Enable (CE) and Master eset (M) which are ideal for parity bus interfacing in high microprogrammed systems. The register is fully edge-triggered. The state of each input, one set-up time before the Low-to-High clock traition is traferred to the corresponding flip-flop s output. UICK EFEENCE ATA SYMBOL PAAMETE CONITIONS T amb = 2 C; GN = TYPICAL t PLH Propagation delay to n C L = 0pF; V CC = V. C IN Input capacitance V I = or V CC pf C OUT Output capacitance Outputs disabled; V O = or V CC 7 pf I CCZ Total supply current Outputs disabled; V CC =.V 00 na ING INFOMATION PACKAGES TEMPEATUE ANGE OUTSIE NOTH AMEICA NOTH AMEICA WG NUMBE 2-Pin Plastic IP 0 C to +8 C N N SOT222-2-Pin plastic SO 0 C to +8 C SOT7-2-Pin Plastic SSOP Type II 0 C to +8 C B B SOT0-2-Pin Plastic TSSOP Type I 0 C to +8 C PW PW H SOT- PIN CONFIGUATION M GN 2 TOP VIEW V CC CE PIN ESCIPTION PIN NUMBE SYMBOL FUNCTION Output enable input (active-low) 2,,,, 6, 7, 8, 9, 0 2, 22, 2, 20, 9,8, 7, 6, CE M ata inputs ata outputs Clock pulse input (active rising edge) Clock enable input (active-low) Master reset input (active-low) 2 GN Ground () 2 V CC Positive supply voltage SA Sep

2 9-bit -type flip-flop with reset and enable LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) EN G C2 CE M SA00228 SA00229 FUNCTION TABLE INPUTS OUTPUTS OPEATING M M CE n 0 8 L L X X X L Clear L H L h H Load and read data L H L l L L H H X NC Hold H X X X X Z High impedance H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock traition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock traition LOGIC IAGAM NC = No change X = on t care Z = High impedance off state = Low to High clock traition = Not a Low-to-High clock traition CE M SA Sep 06 2

3 9-bit -type flip-flop with reset and enable ABSOLUTE MAXIMUM ATINGS, 2 SYMBOL PAAMETE CONITIONS ATING V CC C supply voltage 0. to +7.0 V I IK C input diode current V I < 0 8 ma V I C input voltage.2 to +7.0 V I OK C output diode current V O < 0 0 ma V OUT C output voltage output in Off or High state 0. to +. V I OUT C output current output in Low state 28 ma T stg Storage temperature range 6 to 0 C NOTES:. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 0 C.. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. ECOMMENE OPEATING CONITIONS SYMBOL PAAMETE LIMITS Min Max V CC C supply voltage.. V V I Input voltage 0 V CC V V IH High-level input voltage V V IL Low-level input voltage 0.8 V I OH High-level output current 2 ma I OL Low-level output current 6 ma t/ v Input traition rise or fall rate 0 /V T amb Operating free-air temperature range 0 +8 C 99 Sep 06

4 9-bit -type flip-flop with reset and enable C ELECTICAL CHAACTEISTICS SYMBOL PAAMETE TEST CONITIONS T amb = +2 C LIMITS T amb = 0 C to +8 C Min Typ Max Min Max V IK Input clamp voltage V CC =.V; I IK = 8mA V V CC =.V; I OH = ma; V I = V IL or V IH V V OH High-level output voltage V CC =.; I OH = ma; V I = V IL or V IH.0..0 V V CC =.V; I OH = 2mA; V I = V IL or V IH 2. V V OL Low-level output voltage V CC =.V; I OL = 6mA; V I = V IL or V IH V V ST Power-up output low voltage V CC =.V; I O = ma; V I = GN or V CC V I I Input leakage current V CC =.V; V I = GN or.v ±0.0 ±.0 ±.0 µa I OFF Power-off leakage current V CC = 0.; V O or V I.V ±.0 ±00 ±00 µa I PU /I P Power-up/down -State V CC = 2.; V O = 0.V; V = V CC ; output current ±.0 ±0 ±0 µa V I = GN or V CC I OZH -State output High current V CC =.V; V O = 2.7V; V I = V IL or V IH µa I OZL -State output Low current V CC =.V; V O = 0.V; V I = V IL or V IH µa I CEX Output High leakage current V CC =.V; V O =.V; V I = GN or V CC µa I O Output current V CC =.V; V O = 2.V ma I CCH V CC =.V; Outputs High, V I = GN or V CC µa I CCL uiescent supply current V CC =.V; Outputs Low, V I = GN or V CC 27 ma I CCZ V CC =.V; Outputs -State; V I = GN or V CC µa I CC Additional supply current per input pin 2 V CC =.V; one input at.v, other inputs at V CC or GN 0... ma NOTES:. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at.v.. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.. This parameter is valid for any V CC between and V with a traition time of up to 0msec. For V CC = V to V CC = V 0%, a traition time of up to 00µsec is permitted. AC CHAACTEISTICS GN =, t = t F = 2., C L = 0pF, L = 00Ω SYMBOL PAAMETE WAVEFOM T amb = +2 o C V CC = +. LIMITS T amb = -0 to +8 o C V CC = +. ±0.V Min Typ Max Min Max f MAX Maximum clock frequency MHz t PLH t PZH t PZL t PHZ t PLZ Propagation delay to n Propagation delay M to n Output enable time to High and Low level Output disable time from High and Low level Sep 06

5 9-bit -type flip-flop with reset and enable AC SETUP EUIEMENTS GN =, t = t F = 2., C L = 0pF, L = 00Ω LIMITS SYMBOL PAAMETE WAVEFOM T amb = +2 o C V CC = +. T amb = -0 to +8 o C V CC = +. ±0.V Min Typ Min t s (H) t s (L) Setup time, High or Low n to t h (H) t h (L) Hold time, High or Low n to t w (H) t w (L) pulse width High or Low t s (H) t s (L) Setup time, High or Low CE to t h (H) t h (L) Hold time, High or Low CE to t w (L) M pulse width, Low t rec ecovery time M to Sep 06

6 9-bit -type flip-flop with reset and enable AC WAVEFOMS =.V, V IN = GN to. /f MAX M t w (L) t EC t W (H) t W (L) t PLH n SA009 Waveform. Propagation elay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency n SA0022 Waveform 2. Master eset Pulse WIdth, Master eset to Output elay and Master eset to Clock ecovery Time n, CE ÉÉ ÉÉ ÉÉÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉ t s (H) t h (H) t s (L) t h (L) t PZH t PHZ n V OH 0.V NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA002 Waveform. ata Setup and Hold Times SA00066 Waveform. -State Output Enable Time to High Level and Output isable Time from High Level t PZL t PLZ n V OL +0.V SA00067 Waveform. -State Output Enable Time to Low Level and Output isable Time from Low Level 99 Sep 06 6

7 9-bit -type flip-flop with reset and enable TEST CICUIT AN WAVEFOM V CC t W 90% 90% AMP (V) PULSE GENEATO V IN.U.T. V OUT L 7. NEGATIVE PULSE 0% 0% t THL (t F ) t TLH (t ) T C L Test Circuit for -State Outputs SWITCH POSITION TEST SWITCH t PLZ closed t PZL closed All other open L POSITIVE PULSE 90% 90% t TLH (t ) t THL (t F ) 0% t 0% W =.V Input Pulse efinition AMP (V) EFINITIONS L = Load resistor; see AC CHAACTEISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC CHAACTEISTICS for value. T = Termination resistance should be equal to Z OUT of pulse generators. INPUT PULSE EUIEMENTS FAMILY Amplitude ep. ate t W t t F 7ABT. MHz SA Sep 06 7