CONDITIONS T amb = 25 C; GND = 0V

Transcription

1 Octal -type traparent latch (-State) FATURS is flow-through pinout version of 7ABT7 Inputs and outputs on opposite side of package allow easy interface to microprocessors -State output buffers Common output enable atch-up protection exceeds 00mA per JC Std 7 S protection exceeds 000 V per MI ST 88 Method 0 and 00 V per Machine Model Power-up -State Power-up reset SCRIPTION The high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The device is an octal traparent latch coupled to eight -State output buffers. The two sectio of the device are controlled independently by nable () and Output nable (O) control gates. The is functionally identical to the 7ABT7 but has a flow-through pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the inputs are traferred to the latch outputs when the atch nable () input is igh. The latch remai traparent to the data inputs while is igh, and stores the data that is present one setup time before the igh-to-ow enable traition. The -State output buffers are designed to drive heavily loaded -State buses, MOS memories, or MOS microprocessors. The active-ow Output nable (O) controls all eight -State buffers independent of the latch operation. When O is ow, the latched or traparent data appears at the outputs. When O is igh, the outputs are in the igh-impedance OFF state, which mea they will neither drive nor load the bus. UICK RFRNC ATA SYMBO t P t P PARAMTR Propagation delay n to n C = 0pF; V CC = V CONITIONS T amb = C; GN = 0V TYPICA C IN Input capacitance V I = 0V or V CC pf C OUT Output capacitance Outputs disabled; V O = 0V or V CC 6 pf I CCZ Total supply current Outputs disabled; V CC =.V 00 µa.8. ORRING INFORMATION PACKAGS TMPRATUR RANG OUTSI NORT AMRICA NORT AMRICA WG NUMBR 0-Pin Plastic IP 0 C to +8 C N N SOT6-0-Pin plastic SO 0 C to +8 C SOT6-0-Pin Plastic SSOP Type II 0 C to +8 C B B SOT9-0-Pin Plastic TSSOP Type I 0 C to +8 C PW PW SOT60- PIN CONFIGURATION PIN SCRIPTION PIN NUMBR SYMBO FUNCTION O Output enable input (active-ow) O V CC 0,,,, 6, 7, 8, 9 9, 8, 7, 6,,,, ata inputs ata outputs 6 nable input (active-igh) 6 0 GN Ground (0V) 7 0 V CC Positive supply voltage GN 0 SA Sep

2 Octal -type traparent latch (-State) OGIC SYMBO (I/IC) OGIC SYMBO N C O SA0087 SA0086 FUNCTION TAB INPUTS INTRNA OUTPUTS OPRATING MO O n RGISTR 0 7 l h X NC NC old X n NC n Z Z nable and read register atch and read register isable outputs = igh voltage level h = igh voltage level one set-up time prior to the igh-to-ow traition = ow voltage level l = ow voltage level one set-up time prior to the igh-to-ow traition NC= No change X = on t care Z = igh impedance off state = igh-to-ow traition OGIC IAGRAM O SA Sep 06

3 Octal -type traparent latch (-State) ABSOUT MAXIMUM RATINGS, SYMBO PARAMTR CONITIONS RATING V CC C supply voltage 0. to +7.0 V I IK C input diode current V I < 0 8 ma V I C input voltage to +7.0 V I OK C output diode current V O < 0 0 ma V OUT C output voltage output in Off or igh state 0. to +. V I OUT C output current output in ow state 8 ma T stg Storage temperature range 6 to 0 C NOTS:. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. xposure to absolute-maximum-rated conditio for extended periods may affect device reliability.. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 0 C.. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RCOMMN OPRATING CONITIONS SYMBO PARAMTR IMITS Min Max V CC C supply voltage.. V V I Input voltage 0 V CC V V I igh-level input voltage.0 V V I ow-level input voltage 0.8 V I O igh-level output current ma I O ow-level output current 6 ma t/ v Input traition rise or fall rate 0 /V T amb Operating free-air temperature range 0 +8 C 99 Sep 06

4 Octal -type traparent latch (-State) C CTRICA CARACTRISTICS SYMBO PARAMTR TST CONITIONS T amb = + C IMITS T amb = 0 C to +8 C Min Typ Max Min Max V IK Input clamp voltage V CC =.V; I IK = 8mA 0.9 V V CC =.V; I O = ma; V I = V I or V I..9. V V O igh-level output voltage V CC =.0V; I O = ma; V I = V I or V I.0..0 V V CC =.V; I O = ma; V I = V I or V I.0..0 V V O ow-level output voltage V CC =.V; I O = 6mA; V I = V I or V I V V RST Power-up output low voltage V CC =.V; I O = ma; V I = GN or V CC V I I Input leakage current V CC =.V; V I = GN or.v ±0.0 ± ± µa I OFF Power-off leakage current V CC = 0.0V; V O or V I.V ±.0 ±00 ±00 µa I PU /I P Power-up/down -State output current V CC =.0V; V O = 0.V; V O = on t Care; V I = GN or V CC ±.0 ±0 ±0 µa I OZ -State output igh current V CC =.V; V O =.7V; V I = V I or V I µa I OZ -State output ow current V CC =.V; V O = 0.V; V I = V I or V I µa I CX Output igh leakage current V CC =.V; V O =.V; V I = GN or V CC µa I O Output current V CC =.V; V O =.V ma I CC V CC =.V; Outputs igh, V I = GN or V CC µa I CC uiescent supply current V CC =.V; Outputs ow, V I = GN or V CC 0 0 ma I CCZ V CC =.V; Outputs -State; V I = GN or V CC µa I CC Additional supply current per input pin V CC =.V; one input at.v, other inputs at V CC or GN 0... ma NOTS:. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.. This is the increase in supply current for each input at.v.. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.. This parameter is valid for any V CC between 0V and.v with a traition time of up to 0msec. For V CC =.V to V CC = V 0%, a traition time of up to 00µsec is permitted. AC CARACTRISTICS GN = 0V, t R = t F =., C = 0pF, R = 00Ω SYMBO PARAMTR WAVFORM t P t P t P t P t PZ t PZ t PZ t PZ Propagation delay n to n Propagation delay to n Output enable time to igh and ow level Output disable time from igh and ow level T amb = + o C V CC = +.0V IMITS T amb = -0 to +8 o C V CC = +.0V ±0.V Min Typ Max Min Max Sep 06

5 Octal -type traparent latch (-State) AC STUP RUIRMNTS GN = 0V, t R = t F =., C = 0pF, R = 00Ω SYMBO PARAMTR WAVFORM t s () t s () t h () t h () t w () Setup time, igh or ow n to old time, igh or ow n to pulse width igh T amb = + o C V CC = +.0V IMITS T amb = -0 to +8 o C V CC = +.0V ±0.V Min Typ Min AC WAVFORMS =.V, V IN = GN to.0v O t w () t PZ t PZ t P t P n n V O 0.V 0V SA0006 Waveform. Propagation elay, nable to Output, and nable Pulse Width SA00066 Waveform. -State Output nable Time to igh evel and Output isable Time from igh evel n O t P t P t PZ t PZ n n V O +0.V V O n SA0006 Waveform. Propagation elay for ata to Outputs ÉÉÉ ÉÉ ÉÉÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ SA00 Waveform. -State Output nable Time to ow evel and Output isable Time from ow evel t s () t h () t s () t h () NOT: The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform. ata Setup and old Times SA Sep 06

6 Octal -type traparent latch (-State) TST CIRCUIT AN WAVFORM V CC t W 90% 90% AMP (V) PUS GNRATOR V IN.U.T. V OUT R 7.0V NGATIV PUS 0% 0% t T (t F ) 0V t T (t R ) R T C Test Circuit for -State Outputs SWITC POSITION TST SWITC t PZ closed t PZ closed All other open R POSITIV PUS 90% 90% t T (t R ) t T (t F ) 0% t 0% W =.V Input Pulse efinition AMP (V) 0V FINITIONS R = oad resistor; see AC CARACTRISTICS for value. C = oad capacitance includes jig and probe capacitance; see AC CARACTRISTICS for value. R T = Termination resistance should be equal to Z OUT of pulse generators. INPUT PUS RUIRMNTS FAMIY Amplitude Rep. Rate t W t R t F 7ABT.0V Mz 00.. SA Sep 06 6