Octal 3-State Inverting Transparent Latch High-Performance Silicon-Gate CMOS

Transcription

1 TECNICAL DATA IN74C33A Octal 3-State Inverting Traparent Latch igh-performance Silicon-ate CMOS The IN74C33A is identical in pinout to the LS/ALS33. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. These latches appear traparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. The data appears as the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the highimpedance state. Thus, data may be latched even when the outputs are not enabled. Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: to Low Input Current: 1.0 µa igh Noise Immunity Characteristic of CMOS Devices ORDERIN INFORMATION IN74C33AN Plastic IN74C33ADW SOIC T A = - to 12 C for all packages PIN ASSINMENT LOIC DIARAM FUNCTION TABLE PIN = CC PIN 10 = ND Output Enable Inputs Latch Enable D Output Q L L L L L L X no change X X Z X = don t care Z = high impedance

2 IN74C33A MAXIMUM RATINS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to ND) -0. to +7.0 IN DC Input oltage (Referenced to ND) -1. to CC +1. OUT DC Output oltage (Referenced to ND) -0. to CC +0. I IN DC Input Current, per Pin ± ma I OUT DC Output Current, per Pin ±3 ma I CC DC Supply Current, CC and ND Pi ±7 ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -6 to +10 C T L Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - 10 mw/ C from 6 to 12 C SOIC Package: : - 7 mw/ C from 6 to 12 C mw 260 C RECOMMENDED OPERATIN CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to ND) IN, OUT DC Input oltage, Output oltage (Referenced to ND) 0 CC T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time (Figure 1) CC = CC = CC = This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be cotrained to the range ND ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either ND or CC ). Unused outputs must be left open.

3 IN74C33A DC ELECTRICAL CARACTERISTICS (oltages Referenced to ND) Symbol Parameter Test Conditio 2 C to - C I Minimum igh- Level Input oltage IL Maximum Low - Level Input oltage O Minimum igh- Level Output oltage OUT = or CC - I OUT µa OUT = or CC - I OUT µa IN = I or IL I OUT µa CC uaranteed Limit C C Unit IN = I or IL I OUT ma I OUT 7.8 ma OL Maximum Low- Level Output oltage IN = IL or I I OUT µa I IN I OZ I CC Maximum Input Leakage Current Maximum Three- State Leakage Current Maximum Quiescent Supply Current (per Package) IN = I or IL I OUT ma I OUT 7.8 ma) IN = CC or ND ± ±1.0 ±1.0 µa Output in igh-impedance State IN = IL or I OUT = CC or ND IN = CC or ND I OUT =0µA ±0. ±.0 ±10 µa µa

4 IN74C33A AC ELECTRICAL CARACTERISTICS (C L =0pF,Input t r =t f = ) CC Symbol Parameter 2 C to - C t PL, t PL t PL, t PL t PLZ, t PZ t PZL, t PZ t TL, t TL Maximum Propagation Delay, Input D to Q (Figures 1 and ) Maximum Propagation Delay, Latch Enable to Q (Figures 2 and ) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Output Traition Time, Any Output (Figures 1 and ) uaranteed Limit 8 C 12 C Unit C IN Maximum Input Capacitance pf C OUT Maximum Three-State Output Capacitance (Output in igh-impedance State) pf C PD Power Dissipation Capacitance (Per Latch) Used to determine the no-load dynamic power coumption: P D =C PD CC 2 f+i CC CC C, CC =.0 37 pf TIMIN REQUIREMENTS(C L =0pF,Input t r =t f = ) CC uaranteed Limit Symbol Parameter 2 C to - C 8 C 12 C Unit t su t h t w t r, t f Minimum Setup Time, Input D to Latch Enable (Figure 4) Minimum old Time, Latch Enable to Input D(Figure 4) Minimum Pulse Width, Latch Enable (Figure 2) Maximum Input Rise and Fall Times (Figure 1)

5 IN74C33A Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure. Test Circuit Figure 6. Test Circuit

6 IN74C33A EXPANDED LOIC DIARAM

7 IN74C33A N SUFFIX PLASTIC DIP (MS - 001AD) 1 A B Dimeion, mm Symbol MIN MAX A B C.33 F L D F D N C -T- K SEATIN PLANE M J J 0 10 K NOTES: 0.2 (0.010) M T 1. Dimeio A, B do not include mold flash or protrusio. Maximum mold flash or protrusio 0.2 mm (0.010) per side. L M N 0. D SUFFIX SOIC (MS - 013AC) -T- 1 D A (0.010) M T C M B K P C SEATIN PLANE Symbol MIN MAX A B C D F NOTES: J Dimeio A and B do not include mold flash or protrusion. K Maximum mold flash or protrusion mm (0.006) per side M for A; for B 0.2 mm (0.010) per side. P J R x 4 F M Dimeion, mm R