Programmable Timer High-Performance Silicon-Gate CMOS
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- Roxanne Manning
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1 TECNICAL DATA Programmable Timer igh-performance Silicon-ate CMOS The IW1B programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitons and can also be reset via the MASTER RESET input. The output from this timer is the Q or not Q output from the 8th, th, 1th, or 16th counter stage. The desired stage is chosen using time-select inputs A and B. The output is available in either of two modes selectable via the MODE input, pin. When this MODE input is a logic 1,the output will be a continuous square wave having a frequency equal to the oscillator frequency divided by 2 N. With the MODE input set to logic 0 and after a MASTER RESET is initiated, the output (assuming Q output has been selected) changes from a low to a high state after 2 N-1 counts and remains in that state until another MASTER RESET pulse is applied or the MODE input is set to a logic 1. Timing is initialized by setting the AUTO RESET input (pin ) to IW1B ORDERIN INFORMATION IW1BN Plastic IW1BD SOIC T A = - to 12 C for all packages logic 0 and turning power on. If pin is set to logic 1, the AUTO RESET circuit is disabled and counting will not start untill after a positive MASTER RESET pulse is applied and returns to a low level. The AUTO RESET consumes an appreciable amount of power and should not be used if low-power operation is desired. For reliable automatic power-on reset, CC should be greater than. Operating oltage Range:.0 to 18 Maximum input current of 1 A at 18 over full package-temperature range; 0 na at 18 and 2 C Noise margin (over full package temperature range): 1.0 supply 2.0 supply 2. supply LOIC DIARAM PIN ASSINMENT NC = NO CONNECTION PIN 1 = CC PIN = ND PINS,11 = NO CONNECTION
2 IW1B MAXIMUM RATINS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to ND) -0. to + IN DC Input oltage (Referenced to ND) -0. to CC +0. OUT DC Output oltage (Referenced to ND) -0. to CC +0. I IN DC Input Current, per Pin ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ P D Power Dissipation per Output Transistor 0 mw Tstg Storage Temperature -6 to +0 C T L Lead Temperature, 1 mm from Case for Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - mw/ C from 6 to 12 C SOIC Package: : - mw/ C from 6 to 12 C 0 00 mw 260 C RECOMMENDED OPERATIN CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to ND).0 18 IN, OUT DC Input oltage, Output oltage (Referenced to ND) 0 CC T A Operating Temperature, All Package Types C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be constrained to the range ND ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either ND or CC ). Unused outputs must be left open.
3 IW1B DC ELECTRICAL CARACTERISTICS Digital Section Symbol Parameter Test Conditions - C I IL O OL I IN I CC I OL I O Minimum igh-level Input oltage Maximum Low -Level Input oltage Minimum igh-level Output oltage Maximum Low-Level Output oltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) *Note 1 Minimum Output Low (Sink) Current Minimum Output igh (Source) Current OUT =0. or CC -0. OUT =1.0 or CC -1.0 OUT =1. or CC -1. OUT =0. or CC -0. OUT =1.0 or CC -1.0 OUT =1. or CC -1. CC IN =ND or CC.0 IN =ND or CC uaranteed Limit 2 C C Unit IN = ND or CC A IN = ND or CC.0 IN = ND or CC U OL =0. U OL =0. U OL =1. IN = ND or CC U O =2. U O =.6 U O =9. U O =1. NOTE 1: With AUTO RESET enable additional current drain at 2 C is: 0 A (Max) at ; 0 A (Max) at ; 00 A (Max) at A ma ma
4 IW1B AC ELECTRICAL CARACTERISTICS (C L =0pF, R L =0k, Input t r =t f = ns) CC uaranteed Limit Symbol Parameter - C 2 C 12 C Unit f max Maximum Clock Frequency.0 t PL, t PL t TL t TL Maximum Propagation Delay, Clock to Q (2 8 ) (2 16 ) Maximum Output Transition Time, Any Output Maximum Output Transition Time, Any Output C IN Maximum Input Capacitance -. pf Mz ns ns TIMIN REQUIREMENTS (C L =0pF, R L =0k, Input t r =t f = ns) CC uaranteed Limit Symbol Parameter +2 C -0 C to +8 C t w t r,t f Minimum Pulse Width, Master Reset or Clock Maximum Rise and Fall Time, Clock Unlimited Unit ns s
5 IW1B Figure 1. Switching Weveforms FREQUENCY SELECTION TABLE INPUTS No. of Stages Count A B N 2 N L L L 2 L FUNCTION TABLE PIN STATE 0 1 Auto Reset On Auto Reset Disable 6 Master Reset Off Master Reset On 9 Output Initially Low After Reset Output Initially igh After Reset (not Q) (Q) Single Transition Mode Recycle Mode EXPANDED LOIC DIARAM
6 IW1B N SUFFIX PLASTIC DIP (MS - 001AA) NOTES: 1 1 A F 0.2 (0.0) M T 1. Dimensions A, B do not include mold flash or protrusions. Maximum mold flash or protrusions 0.2 mm (0.0) per side. 8 D N B -T- SEATIN.2 PLANE K D M J F J (0.0) M T C M NOTES: K Dimensions A and B do not include mold flash or protrusion. M Maximum mold flash or protrusion 0. mm (0.006) per side P for A; for B 0.2 mm (0.0) per side. R C -T- K SEATIN PLANE M L J Dimension, mm Symbol MIN MAX A B C. D F J 0 K L M N 0.8 D SUFFIX SOIC (MS - 012AB) 1 1 A 8 B P C Symbol MIN MAX A B.8 C D F R x Dimension, mm 1.2
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TEHNIAL ATA IN74H74A Octal 3-State Noninverting Flip-Flop High-Performance Silicon-Gate MOS N SUFFIX PLASTI IP The IN74H74A is identical in pinout to the LS/ALS74. The device inputs are compatible with
MM74C93 4-Bit Binary Counter
MM74C93 4-Bit Binary Counter General Description The MM74C93 binary counter and complementary MOS (CMOS) integrated circuits cotructed with N- and P- channel enhancement mode traistors. The 4-bit binary
MM74HC08 Quad 2-Input AND Gate
Quad 2-Input AND Gate General Description The MM74HC08 AND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
MM54HCT193 MM74HCT193 Synchronous Binary Up Down Counters
MM54HCT193 MM74HCT193 Synchronous Binary Up Down Counters General Description These high speed synchronous counters utilize advanced silicon-gate CMOS technology to achieve the high noise immunity and
74LS195 SN74LS195AD LOW POWER SCHOTTKY
The SN74LS95A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. CD4020BC CD4040BC CD4060BC 14-Stage Ripple Carry Binary Counters 12-Stage
CD4028BC BCD-to-Decimal Decoder
BCD-to-Decimal Decoder General Description The is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the 4 inputs, A,
CD4013BC Dual D-Type Flip-Flop
Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. Each
High Speed MOSFET Drivers
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74HC393; 74HCT393. Dual 4-bit binary ripple counter
Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified
NTE40194B Integrated Circuit CMOS, 4 Bit Bidirectional Universal Shift Register
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CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
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INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook
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MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder General Description The MM74HC259 device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch, designed for general
MM74HCT138 3-to-8 Line Decoder
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