MC14555B, MC14556B. Dual Binary to 1 of 4 Decoder/Demultiplexer
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1 MC, MC6 Dual inary to of Decoder/Demultiplexer The MC and MC6 are cotructed with complementary MOS (CMOS) enhancement mode devices. ach Decoder/Demultiplexer has two select inputs ( and ), an active low nable input (), and four mutually exclusive outputs (Q, Q, Q, Q). The MC has the selected output go to the high state, and the MC6 has the selected output go to the low state. xpanded decoding such as binarytohexadecimal (of6), etc., can be achieved by using other MC or MC6 devices. pplicatio include code conversion, address decoding, memory selection control, and demultiplexing (using the nable input as a data input) in digital data tramission systems. Features Diode Protection on ll Inputs ctive High or ctive Low Outputs xpandable Supply Voltage Range = to 8 ll Outputs uffered Capable of Driving Two LowPower TTL Loads or One LowPower Schottky TTL Load Over the Rated Temperature Range PbFree Packages are vailable PDIP6 P SUFFIX CS 68 6 SOIC6 D SUFFIX CS 7 SOIJ6 F SUFFIX CS MRKING DIGRMS MCxCP WLYYWWG xg WLYWW MCx LYWG MXIMUM RTINGS (Voltages Referenced to ) Parameter Symbol Value Unit DC Supply Voltage Range. to +8. V Input or Output Voltage Range (DC or Traient) Input or Output Current (DC or Traient) per Pin V in, V out. to +. V I in, I out ± m Power Dissipation, per Package (Note ) P D mw mbient Temperature Range T to + C Storage Temperature Range T stg 6 to + C Lead Temperature (8Second Soldering) T L 6 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. xtended exposure to stresses above the Recommended Operating Conditio may affect device reliability.. Temperature Derating: Plastic P and D/DW Packages: mw/ C From 6 C To C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be cotrained to the range (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDRRM/D. Q Q Q Q x = or 6 = ssembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = PbFree Package MC PIN SSIGNMNTS 6 Q Q Q Q ORDRING INFORMTION See detailed ordering and shipping information in the package dimeio section on page of this data sheet. Q Q Q Q MC Q Q Q Q Semiconductor Components Industries, LLC, 6 Publication Order Number: MC/D
2 MC, MC6 Inputs TRUTH TL Outputs nable Select MC MC6 Q Q Q Q Q Q Q Q X X X = Don t Care MC Q Q Q 6 Q 7 Q Q Q Q LOCK DIGRM = PIN 6 = PIN 8 MC6 Q Q Q 6 Q 7 Q Q Q Q ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ LCTRICL CHRCTRISTICS (Voltages Referenced to ) Characteristic Output Voltage Level V in = or Symbol V Level V in = or OH C C C Min Max Min Typ (Note ) Max Min Max... Unit Input Voltage Level (V O =. or. ) (V O =. or. ) (V O = or. ) V IL Level (V O =. or. ) (V O =. or. ) (V O =. or ) V IH Output Drive Current ( =. ) Source ( =.6 ) ( =. ) ( = ) I OH mdc ( =. ) Sink ( =. ) ( =. ) I OL mdc Input Current I in ±. ±. ±. ±. dc Input Capacitance, (V in = ) C in 7. pf Quiescent Current (Per Package) I DD... 6 dc Total Supply Current (Notes, ) (Dynamic plus Quiescent, Per Package) (C L = pf on all outputs, all buffers switching) I T I T = (.8 /khz) f + I DD I T = (.7 /khz) f + I DD I T = (.6 /khz) f + I DD. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance.. The formulas given are for the typical characteristics only at C.. To calculate total supply current at loads other than pf: I T (C L ) = I T ( pf) + (C L ) Vfk where: I T is in (per package), C L in pf, V = ( ) in volts, f in khz is input frequency, and k =.. dc
3 MC, MC6 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHRCTRISTICS (Note ) (C L = pf, T = C) Characteristic Symbol Min Output Rise and Fall Time t TLH, t THL = (. /pf) C L + t TLH, t THL = (.7 /pf) C L +. t TLH, t THL = (. /pf) C L +. Propagation Delay Time, to Output t PLH, t PHL = (.7 /pf) C L + t PLH, t PHL = (.66 /pf) C L + 6 t PLH, t PHL = (. /pf) C L + Propagation Delay Time to Output t PLH, t PHL = (.7 /pf) C L + t PLH, t PHL = (.66 /pf) C L + t PLH, t PHL = (. /pf) C L + t TLH, t THL t PLH, t PHL t PLH, t PHL Typ (Note 6) Max Unit. The formulas given are for the typical characteristics only at C. 6. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance INPUTS ( DUTY CYCL) INPUTS ( DUTY CYCL) OUTPUT Q INPUT LOW % % ll 8 outputs connect to respective C L loads. f in respect to a system clock. f INPUT HIGH, INPUT LOW INPUT t PHL OUTPUT Q MC6 t THL t PLH OUTPUT Q MC t TLH % % % % % % t PLH t TLH t PHL tthl Figure. Dynamic Power Dissipation Signal Waveforms Figure. Dynamic Signal Waveforms LOGIC DIGRM (/ of Dual) Q Q Q Q liminated for MC
4 MC, MC6 ORDRING INFORMTION MCCP MCCPG Device Package Shipping PDIP6 PDIP6 (PbFree) Units / Rail MCD MCDG MCDR MCDRG MCFL MCFLG MC6CP MC6CPG SOIC6 SOIC6 (PbFree) SOIC6 SOIC6 (PbFree) SOIJ6 SOIJ6 (PbFree) PDIP6 PDIP6 (PbFree) 8 Units / Rail / Tape & Reel / Tape & Reel Units / Rail MC6D SOIC6 8 Units / Rail MC6DR MC6DRG SOIC6 SOIC6 (PbFree) / Tape & Reel MC6F SOIJ6 Units / Tube MC6FL MC6FLG SOIJ6 SOIJ6 (PbFree) / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio rochure, RD8/D.
5 MC, MC6 PCKG DIMNSIONS PDIP6 CS 688 ISSU T 6 8 NOTS:. DIMNSIONING ND TOLRNCING PR NSI Y.M, 8.. CONTROLLING DIMNSION: INCH.. DIMNSION L TO CNTR OF LDS WHN FORMD PRLLL.. DIMNSION DOS NOT INCLUD MOLD FLSH.. ROUNDD CORNRS OPTIONL. H G F S C K STING T PLN D 6 PL. (.) M T M J L M INCHS MILLIMTRS DIM MIN MX MIN MX C D.... F G. SC. SC H SC.7 SC J K...8. L M S.... SOIC6 CS 7 ISSU J 6 8 P 8 PL. (.) M S NOTS:. DIMNSIONING ND TOLRNCING PR NSI Y.M, 8.. CONTROLLING DIMNSION: MILLIMTR.. DIMNSIONS ND DO NOT INCLUD MOLD PROTRUSION.. MXIMUM MOLD PROTRUSION. (.6) PR SID.. DIMNSION D DOS NOT INCLUD DMR PROTRUSION. LLOWL DMR PROTRUSION SHLL.7 (.) TOTL IN XCSS OF TH D DIMNSION T MXIMUM MTRIL CONDITION. T STING PLN G K C D 6 PL. (.) M T S S M R X J F MILLIMTRS INCHS DIM MIN MX MIN MX C D.... F...6. G.7 SC SC J...8. K.... M 7 7 P R....
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8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicon-gate CMOS
MC14504B. Hex Level Shifter for TTL to CMOS or CMOS to CMOS
CB Hex Level Shifter for TTL to COS or COS to COS The CB is a hex noninverting level shifter using COS technology. The level shifter will shift a TTL signal to COS logic levels for any COS supply voltage
SN74LS151D LOW POWER SCHOTTKY
The TTL/MSI SN74LS5 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS5 can be used as a universal function
CD4021BC 8-Stage Static Shift Register
8-Stage Static Shift Register General Description The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages.
MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder General Description The MM74HC259 device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch, designed for general
74HC of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The 74HC38 is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are
CD4024BC 7-Stage Ripple Carry Binary Counter
CD4024BC 7-Stage Ripple Carry Binary Counter General Description The CD4024BC is a 7-stage ripple-carry binary counter. Buffered outputs are externally available from stages 1 through 7. The counter is
MM74HC373 3-STATE Octal D-Type Latch
3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
MM74HC373 3-STATE Octal D-Type Latch
MM74HC373 3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power
MM74HC251 8-Channel 3-STATE Multiplexer
8-Channel 3-STATE Multiplexer General Description The MM74HC251 8-channel digital multiplexer with 3- STATE outputs utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and
Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
TECHNICAL DATA IN74ACT74 Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT74 is identical in pinout to the LS/ALS74, HC/HCT74. The IN74ACT74 may be used as a level converter
MC14511B. BCD-To-Seven Segment Latch/Decoder/Driver
MC45B BCD-To-Seven Segment Latch/Decoder/Driver The MC45B BCDtoseven segment latch/decoder/driver is cotructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a
MC14543B. MARKING DIAGRAMS ORDERING INFORMATION. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) PDIP 16 P SUFFIX CASE 648
The MC14543B BCD to seven segment latch/decoder/driver is designed for use with liquid crystal readouts, and is cotructed with complementary MOS (CMOS) enhancement mode devices. The circuit provides the
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 2005 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
CD4528BC Dual Monostable Multivibrator
Dual Monostable Multivibrator General Description The CD4528BC is a dual monostable multivibrator. Each device is retriggerable and resettable. Triggering can occur from either the rising or falling edge
MC14020B. 14-Bit Binary Counter
M4020B 4-Bit Binary ounter The M4020B 4stage binary counter is cotructed with MOS Phannel and Nhannel enhancement mode devices in a single monolithic structure. This part is designed with an input wave
MM74HC374 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Flip-Flop General Description The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B
MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary