MC14555B, MC14556B. Dual Binary to 1-of-4 Decoder/Demultiplexer
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1 MC4555, MC4556 Dual inary to -of-4 Decoder/Demultiplexer The MC4555 and MC4556 are constructed with complementary MOS (CMOS) enhancement mode devices. ach Decoder/Demultiplexer has two select inputs ( and ), an active low nable input (), and four mutually exclusive outputs (Q0, Q, Q2, Q3). The MC4555 has the selected output go to the high state, and the MC4556 has the selected output go to the low state. xpanded decoding such as binarytohexadecimal (of6), etc., can be achieved by using other MC4555 or MC4556 devices. pplications include code conversion, address decoding, memory selection control, and demultiplexing (using the nable input as a data input) in digital data transmission systems. Features Diode Protection on ll Inputs ctive High or ctive Low Outputs xpandable Supply Voltage Range = 3.0 to 8 ll Outputs uffered Capable of Driving Two LowPower TTL Loads or One LowPower Schottky TTL Load Over the Rated Temperature Range These Devices are PbFree and are RoHS Compliant NLV Prefix for utomotive and Other pplications Requiring Unique Site and Control Change Requirements; CQ0 Qualified and PPP Capable MXIMUM RTINGS (Voltages Referenced to ) Parameter Symbol Value Unit DC Supply Voltage Range 0.5 to +8.0 V Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin V in, V out 0.5 to V I in, I out ± m Power Dissipation, per Package (Note ) P D 500 mw mbient Temperature Range T 55 to +25 C Storage Temperature Range T stg 65 to +0 C Lead Temperature (8Second Soldering) T L 260 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. xtended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ C From 65 C To 25 C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be constrained to the range (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. Q0 Q Q2 Q3 PDIP6 P SUFFIX CS SOIC6 D SUFFIX CS 75 SOIJ6 F SUFFIX CS 66 x = 5 or 6 = ssembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = PbFree Package MC Q0 Q Q2 Q3 ORDRING INFORMTION MRKING DIGRMS 455xG WLYWW See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. 6 6 PIN SSIGNMNTS Q0 Q Q2 Q3 MC455xCP WLYYWWG MC455x LYWG MC Q0 Q Q2 Q3 Semiconductor Components Industries, LLC, 203 May, 203 Rev. Publication Order Number: MC4555/D
2 MC4555, MC4556 TRUTH TL Inputs Outputs nable Select MC4555 MC4556 Q3 Q2 Q Q0 Q3 Q2 Q Q X X X = Don t Care MC Q0 4 Q 5 3 Q2 6 Q Q0 Q Q2 Q3 LOCK DIGRM = PIN 6 = PIN 8 MC Q0 4 Q 5 3 Q2 6 Q3 7 Q0 Q Q2 Q3 2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ LCTRICL CHRCTRISTICS (Voltages Referenced to ) Characteristic Output Voltage 0 Level V in = or 0 Symbol V OL V Level V in = 0 or OH 55 C 25 C 25 C Min Max Min Typ (Note 2) Max Min Max Unit Input Voltage 0 Level (V O = 4.5 or 0.5 ) (V O =.0 or.0 ) (V O = 3.5 or.5 ) V IL Level (V O = 0.5 or 4.5 ) (V O =.0 or.0 ) (V O =.5 or 3.5 ) V IH Output Drive Current (V OH = 2.5 ) Source (V OH = 4.6 ) (V OH =.5 ) (V OH = 3.5 ) I OH mdc (V OL = 0.4 ) Sink (V OL = 0.5 ) (V OL =.5 ) I OL mdc Input Current I in ±0. ± ±0. ±.0 dc Input Capacitance, (V in = 0) C in 7.5 pf Quiescent Current (Per Package) I DD dc Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Package) (C L = 50 pf on all outputs, all buffers switching) I T I T = (0.85 /khz) f + I DD I T = (.70 /khz) f + I DD I T = (2.60 /khz) f + I DD 2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 3. The formulas given are for the typical characteristics only at 25 C. 4. To calculate total supply current at loads other than 50 pf: I T (C L ) = I T (50 pf) + (C L 50) Vfk where: I T is in (per package), C L in pf, V = ( ) in volts, f in khz is input frequency, and k = dc 2
3 MC4555, MC4556 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHRCTRISTICS (Note 5) (C L = 50 pf, T = 25 C) Characteristic Symbol Min Output Rise and Fall Time t TLH, t THL = (.5 ns/pf) C L + 25 ns t TLH, t THL = (0.75 ns/pf) C L ns t TLH, t THL = (0.55 ns/pf) C L +.5 ns Propagation Delay Time, to Output t PLH, t PHL = (.7 ns/pf) C L + 35 ns t PLH, t PHL = (0.66 ns/pf) C L + 62 ns t PLH, t PHL = (0.5 ns/pf) C L + 45 ns Propagation Delay Time to Output t PLH, t PHL = (.7 ns/pf) C L + ns t PLH, t PHL = (0.66 ns/pf) C L + 52 ns t PLH, t PHL = (0.5 ns/pf) C L + 40 ns t TLH, t THL t PLH, t PHL t PLH, t PHL Typ (Note 6) Max Unit 5. The formulas given are for the typical characteristics only at 25 C. 6. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance ns ns ns INPUTS ( DUTY CYCL) INPUTS ( DUTY CYCL) OUTPUT Q INPUT LOW 20 ns 20 ns 0% % ll 8 outputs connect to respective C L loads. f in respect to a system clock. 2f V OH V OL INPUT HIGH, INPUT LOW 20 ns 20 ns INPUT t PHL OUTPUT Q3 MC4556 t THL t PLH OUTPUT Q3 MC4555 t TLH 0% % 0% % 0% % t PLH t TLH t PHL V OH V OL V OH V OL tthl Figure. Dynamic Power Dissipation Signal Waveforms Figure 2. Dynamic Signal Waveforms LOGIC DIGRM (/2 of Dual) Q0 Q Q2 Q3 liminated for MC4555 3
4 MC4555, MC4556 ORDRING INFORMTION MC4555CPG Device Package Shipping PDIP6 (PbFree) 500 Units / Rail MC4555DG MC4555DR2G NLV4555DR2G MC4555FLG MC4556CPG SOIC6 (PbFree) SOIC6 (PbFree) SOIJ6 (PbFree) PDIP6 (PbFree) 48 Units / Rail 2500 / Tape & Reel 2000 / Tape & Reel 500 Units / Rail MC4556DR2G NLV4556DR2G SOIC6 (PbFree) 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications rochure, RD80/D. NLV Prefix for utomotive and Other pplications Requiring Unique Site and Control Change Requirements; CQ0 Qualified and PPP Capable. 4
5 MC4555, MC4556 PCKG DIMNSIONS PDIP6 CS ISSU T 6 8 NOTS:. DIMNSIONING ND TOLRNCING PR NSI Y4.5M, CONTROLLING DIMNSION: INCH. 3. DIMNSION L TO CNTR OF LDS WHN FORMD PRLLL. 4. DIMNSION DOS NOT INCLUD MOLD FLSH. 5. ROUNDD CORNRS OPTIONL. H G F D 6 PL S C K 0.25 (0.0) M T STING T PLN M J L M INCHS MILLIMTRS DIM MIN MX MIN MX C D F G 0.0 SC 2.54 SC H 0 SC.27 SC J K L M 0 0 S SOIJ6 CS 660 ISSU e 6 Z b D H 0.3 (0.005) M 0. (0.004) 8 VIW P M L Q L DTIL P c NOTS:. DIMNSIONING ND TOLRNCING PR NSI Y4.5M, CONTROLLING DIMNSION: MILLIMTR. 3. DIMNSIONS D ND DO NOT INCLUD MOLD FLSH OR PROTRUSIONS ND R MSURD T TH PRTING LIN. MOLD FLSH OR PROTRUSIONS SHLL NOT XCD 0. (0.006) PR SID. 4. TRMINL NUMRS R SHOWN FOR RFRNC ONLY. 5. TH LD WIDTH DIMNSION (b) DOS NOT INCLUD DMR PROTRUSION. LLOWL DMR PROTRUSION SHLL 0.08 (0.003) TOTL IN XCSS OF TH LD WIDTH DIMNSION T MXIMUM MTRIL CONDITION. DMR CNNOT LOCTD ON TH LOWR RDIUS OR TH FOOT. MINIMUM SPC TWN PROTRUSIONS ND DJCNT LD TO 0.46 ( 0.08). MILLIMTRS INCHS DIM MIN MX MIN MX b c D e.27 SC 0 SC H L L M 0 0 Q Z
6 MC4555, MC4556 PCKG DIMNSIONS SOIC6 CS 7505 ISSU K 6 8 P 8 PL 0.25 (0.0) M S NOTS:. DIMNSIONING ND TOLRNCING PR NSI Y4.5M, CONTROLLING DIMNSION: MILLIMTR. 3. DIMNSIONS ND DO NOT INCLUD MOLD PROTRUSION. 4. MXIMUM MOLD PROTRUSION 0. (0.006) PR SID. 5. DIMNSION D DOS NOT INCLUD DMR PROTRUSION. LLOWL DMR PROTRUSION SHLL 0.27 (0.005) TOTL IN XCSS OF TH D DIMNSION T MXIMUM MTRIL CONDITION. MILLIMTRS INCHS DIM MIN MX MIN MX C D F G.27 SC 0 SC J K M P R T STING PLN G D 6 PL 0.25 (0.0) M T S S K C M R X 45 J F SOLDRING FOOTPRINT 8X X.2 6 6X PITCH 8 DIMNSIONS: MILLIMTRS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should uyer purchase or use SCILLC products for any such unintended or unauthorized application, uyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an qual Opportunity/ffirmative ction mployer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PULICTION ORDRING INFORMTION LITRTUR FULFILLMNT: Literature Distribution Center for ON Semiconductor P.O. ox 563, Denver, Colorado 8027 US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada mail: orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada urope, Middle ast and frica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC4555/D
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MUR3020PTG SUR83020PTG MUR3040PTG MUR3060PTG SUR83060PTG. SWITCHMODE Power Rectifiers ULTRAFAST RECTIFIERS 30 AMPERES, VOLTS
MUR00PTG, SUR00PTG, MUR00PTG, MUR00PTG, SUR00PTG SWITCHMODE Power Rectifiers These state of the art devices are designed for use in switching power supplies, inverters and as free wheeling diodes. Features
The MC10107 is a triple 2 input exclusive OR/NOR gate. P D = 40 mw typ/gate (No Load) t pd = 2.8 ns typ t r, t f = 2.
The MC10107 is a triple input exclusive OR/NOR gate. P D = 0 mw typ/gate (No Load) t pd =. ns typ t r, t f =. ns typ (0% 0%) LOGIC DIAGRAM MARKING DIAGRAMS CDIP 16 L SUFFIX CASE 60 16 1 MC10107L AWLYYWW
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10173L AWLYYWW
The MC03 is a quad two channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data
NTJD4105C. Small Signal MOSFET. 20 V / 8.0 V, Complementary, A / A, SC 88
NTJD5C Small Signal MOSFET V / 8. V, Complementary, +.63 A /.775 A, SC 88 Features Complementary N and P Channel Device Leading 8. V Trench for Low R DS(on) Performance ESD Protected Gate ESD Rating: Class
74HC244 Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with
MC74ACT Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
8 Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins The MC74ACT323 is an 8-bit universal shift/storage register with3-state outputs. Its function is similar to the MC74ACT299
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC10176 contains six high-speed, master slave type D flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes
MC74VHC132. Quad 2 Input NAND Schmitt Trigger
MC74HC32 Quad 2 Input NAND Schmitt Trigger The MC74HC32 is an advanced high speed CMOS Schmitt NAND trigger fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
MBRS140T3G SBRS8140T3G. Surface Mount Schottky Power Rectifier SCHOTTKY BARRIER RECTIFIER 1.0 AMPERE, 40 VOLTS
MBRSTG, SBRS8TG Surface Mount Schottky Power Rectifier Schottky Power Rectifiers employ the use of the Schottky Barrier principle in a large area metal to silicon power diode. State of the art geometry
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC06 contains six high speed, master slave type D flip flops. Clocking is common to all six flip flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place
LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES ORDERING INFORMATION. SN74LS37xN AWLYYWW PDIP 20 N SUFFIX CASE 738
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is
MC74LCX74. Low-Voltage CMOS Dual D-Type Flip-Flop. With 5 V Tolerant Inputs
Low-oltage CMOS Dual D-Type Flip-Flop With 5 Tolerant Inputs The MC74LCX74 is a high performance, dual D type flip flop with asynchronous clear and set inputs and complementary (O, O) outputs. It operates
MMBFJ309L, MMBFJ310L, SMMBFJ309L, SMMBFJ310L. JFET - VHF/UHF Amplifier Transistor. N Channel
MMBFJ9L, MMBFJL, SMMBFJ9L, SMMBFJL JFET - VHF/UHF Amplifier Transistor NChannel Features Drain and Source are Interchangeable S Prefix for Automotive and Other Applications Requiring Unique Site and Control
NDF08N50Z, NDP08N50Z. N-Channel Power MOSFET. Low ON Resistance Low Gate Charge 100% Avalanche Tested These Devices are Pb Free and are RoHS Compliant
N-Channel Power MOSFET 500 V, 0.69 Features Low ON Resistance Low Gate Charge 0% Avalanche Tested These Devices are Pb Free and are RoHS Compliant ABSOLUTE MAXIMUM RATINGS (T C = 25 C unless otherwise
74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
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MMBZ5xxBLT Series, SZMMBZ5xxBLTG Series Zener Voltage Regulators 5 mw SOT Surface Mount This series of Zener diodes is offered in the convenient, surface mount plastic SOT package. These devices are designed
2N5655G, 2N5657G. Plastic NPN Silicon High-Voltage Power Transistors 0.5 AMPERE POWER TRANSISTORS NPN SILICON VOLTS, 20 WATTS
, Plastic NPN Silicon High-Voltage Power Transistors These devices are designed for use in lineoperated equipment such as audio output amplifiers; lowcurrent, highvoltage converters; and AC line relays.
NL17SZ02. 2-Input NOR Gate
N7SZ0 -Input NOR Gate The N7SZ0 is a single input NOR Gate in three tiny footprint packages. The device performs much as CX multi gate products in speed and drive. Features Tiny SOT, SOT and SOT 9 Packages.
MC14511B. MARKING DIAGRAMS 16. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2) ORDERING INFORMATION
The MC14511B BCD to seven segment latch/decoder/driver is cotructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides
MC74AC109, MC74ACT109. Dual JK Positive Edge Triggered Flip Flop
MC9, MC9 Dual JK Positive EdgeTriggered FlipFlop The MC9/9 coists of two highspeed completely independent traition clocked JK flipflops. The clocking operation is independent of rise and fall times of
MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10161L AWLYYWW
The MC10161 is designed to decode a three bit input word to a one of eight line output. The selected output will be low while all other outputs will be high. The enable inputs, when either or both are
NTSB40200CTG, NTSJ40200CTG. Very Low Forward Voltage Trench-based Schottky Rectifier. Exceptionally Low V F = 0.53 V at I F = 5 A
NTSBCTG, NTSJCTG Very Low Forward Voltage Trench-based Schottky Rectifier Exceptionally Low V F =.3 V at I F = Features Fine Lithography Trenchbased Schottky Technology for Very Low Forward Voltage and
BAT54XV2 Schottky Barrier Diode
June 2015 BAT54XV2 Schottky Barrier Diode Features Low Forward Voltage Drop Flat Lead, Surface Mount Device at 0.60mm Height Extremely Small Outline Plastic Package SOD523F Moisture Level Sensitivity 1
MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10138L AWLYYWW
The MC101 is a four bit counter capable of divide by two, five, or ten functions. It is composed of four set reset master slave flip flops. Clock inputs trigger on the positive going edge of the clock
MC14518B. MARKING DIAGRAMS 16. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) ORDERING INFORMATION
The MC14518B dual BCD counter and the MC14520B dual binary counter are cotructed with MOS P channel and N channel enhancement mode devices in a single monolithic structure. Each coists of two identical,
NTF3055L175. Power MOSFET 2.0 A, 60 V, Logic Level. N Channel SOT AMPERES, 60 VOLTS R DS(on) = 175 m
NTF355L75 Power MOSFET. A, 6 V, Logic Level NChannel SOT3 Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. Features
SN74LS373, SN74LS374. Octal Transparent Latch with 3 State Outputs; Octal D Type Flip Flop with 3 State Output LOW POWER SCHOTTKY
Octal Transparent Latch with 3 State Outputs; Octal Type Flip Flop with 3 State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops
MJW18020G. NPN Silicon Power Transistors High Voltage Planar 30 AMPERES 1000 VOLTS BV CES 450 VOLTS BV CEO, 250 WATTS
NPN Silicon Power Transistors High Voltage Planar The MJW18020 planar High Voltage Power Transistor is specifically Designed for motor control applications, high power supplies and UPS s for which the
2N4123, 2N4124. General Purpose Transistors. NPN Silicon. Pb Free Packages are Available* Features MAXIMUM RATINGS
N413, General Purpose Transistors NPN Silicon Features PbFree Packages are Available* MAXIMUM RATINGS CollectorEmitter Voltage CollectorBase Voltage Rating Symbol Value Unit N413 N413 V CEO 5 V CBO 4 EmitterBase
MMBT5550L, MMBT5551L, SMMBT5551L. High Voltage Transistors. NPN Silicon
MMBT55L, MMBT555L, SMMBT555L High Voltage Transistors NPN Silicon Features AECQ Qualified and PPAP Capable S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements
MC74VHC1GT50 Noninverting Buffer / CMOS Logic Level Shifter
MC74CGT0 Noninverting Buffer / CMOS Logic Level Shifter TTL Compatible Inputs The MC74CGT0 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation
MC74LV594A. 8-Bit Shift Register with Output Register
8-Bit Shift Register with Output Register The MC74LV594A is an 8 bit shift register designed for 2 V to 6.0 V V CC operation. The device contain an 8 bit serial in, parallel out shift register that feeds
74HCT245. Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs. High-Performance Silicon-Gate CMOS
Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS The 74HCT245 is identical in pinout to LS245. The device has TTL-Compatible Inputs. The HCT245
MC74HC139A. Dual 1 of 4 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
MC74HC39A Dual of 4 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The MC74HC39A is identical in pinout to the LS39. The device inputs are compatible with standard CMOS outputs; with pull up
SN74LS175MEL. Quad D Flip Flop LOW POWER SCHOTTKY
uad Flip Flop The LSTTL/MSI SN74LS75 is a high speed uad Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the inputs is stored
MC3346. General Purpose Transistor Array One Differentially Connected Pair and Three Isolated Transistor Arrays
General Purpose Transistor Array One Differentially Connected Pair and Three Isolated Transistor Arrays The MC336 is designed for general purpose, low power applications for consumer and industrial designs.
74FST Bit Bus Switch
4FST32 4 Bit Bus Switch The ON Semiconductor 4FST32 is a quad, high performance switch. The device is CMOS TTL compatible when operating between 4 and. Volts. The device exhibits extremely low R ON and