Dual J-K Flip-Flop with Set and Reset

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Shanon Young
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1 TECNICAL DATA IN74C109A Dual J-K Flip-Flop with Set and Reset igh-performance Silicon-ate CMOS The IN74C109A is identical in pinout to the LS/ALS109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LS/ALSTTL outputs. This device coists of two J-K flip-flops with individual set, reset, and clock inputs. Changes at the inputs are reflected at the outputs with the next low-to-high traition of the clock. Both Q to Q outputs are available from each flip-flop. Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: to Low Input Current: 1.0 µa igh Noise Immunity Characteristic of CMOS Devices ORDERIN INFORMATION IN74C109AN Plastic IN74C109AD SOIC T A = - to 12 C for all packages PIN ASSINMENT LOIC DIARAM PIN = CC PIN 8 = ND FUNCTION TABLE Inputs Outputs Set Reset Clock J K Q Q L X X X L L X X X L L L X X X * * L L L L Toggle L No Change L L X X No Change X = Don t care * Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.

2 MAXIMUM RATINS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to ND) -0. to +7.0 IN DC Input oltage (Referenced to ND) -1. to CC +1. OUT DC Output oltage (Referenced to ND) -0. to CC +0. I IN DC Input Current, per Pin ± ma I OUT DC Output Current, per Pin ±2 ma I CC DC Supply Current, CC and ND Pi ±0 ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -6 to +10 C T L Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - 10 mw/ C from 6 to 12 C SOIC Package: : - 7 mw/ C from 6 to 12 C mw 260 C RECOMMENDED OPERATIN CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to ND) IN, OUT DC Input oltage, Output oltage (Referenced to ND) 0 CC T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time (Figure 1) CC = CC =4. CC = This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be cotrained to the range ND ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either ND or CC ). Unused outputs must be left open.

3 DC ELECTRICAL CARACTERISTICS (oltages Referenced to ND) Symbol Parameter Test Conditio 2 C to - C I Minimum igh- Level Input oltage IL Maximum Low - Level Input oltage O Minimum igh- Level Output oltage OUT = or CC - I OUT µa OUT = or CC - I OUT µa IN = I or IL I OUT µa CC uaranteed Limit C C Unit IN = I or IL I OUT 4.0 ma I OUT.2 ma OL Maximum Low- Level Output oltage IN = IL or I I OUT µa 4. I IN I CC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) IN = IL or I I OUT 4.0 ma I OUT.2 ma IN = CC or ND ± ±1.0 ±1.0 µa IN = CC or ND I OUT =0µA µa

4 AC ELECTRICAL CARACTERISTICS (C L =0pF,Input t r =t f = ) CC Symbol Parameter 2 C to - C f max t PL, t PL t PL, t PL t TL, t TL Maximum Clock Frequency (0% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) Maximum Propagation Delay, Set or Reset to Q or Q (Figures 2 and 4) Maximum Output Traition Time, Any Output (Figures 1 and 4) uaranteed Limit 8 C 12 C Unit C IN Maximum Input Capacitance pf Mz C PD Power Dissipation Capacitance (Per Flip-Flop) C, CC =.0 Used to determine the no-load dynamic power 40 pf coumption: P D =C PD 2 CC f+i CC CC TIMIN REQUIREMENTS (C L =0pF,Input t r =t f = ) CC uaranteed Limit Symbol Parameter 2 C to - C 8 C 12 C Unit t SU t h t rec t w t w t r, t f Minimum Setup Time, J or K to Clock (Figure 3) Minimum old Time, Clock to J or K (Figure 3) Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Set or Reset (Figure 2) Minimum Pulse Width,Clock (Figure 1) Maximum Input Rise and Fall Times (Figure 1)

5 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit EXPANDED LOIC DIARAM

6 N SUFFIX PLASTIC DIP (MS - 001BB) NOTES: 1 A F 0.2 (0.010) M T 1. Dimeio A, B do not include mold flash or protrusio. Maximum mold flash or protrusio 0.2 mm (0.010) per side. 9 8 D N B -T- C -T- K SEATIN PLANE M L J Dimeion, mm Symbol MIN MAX A B C.33 D F J 0 10 K L M N 0.38 D SUFFIX SOIC (MS - 012AC) 1 D A 0.2 (0.010) M T C M 9 8 B K P C SEATIN PLANE Symbol MIN MAX A B C D 0.33 F Dimeion, mm J 0 8 NOTES: K Dimeio A and B do not include mold flash or protrusion. M Maximum mold flash or protrusion mm (0.006) per side P for A; for B 0.2 mm (0.010) per side. R J R x 4 F M

Dual D Flip-Flop with Set and Reset

TECNICAL DATA IN74C74A Dual D Flip-Flop with Set and Reset The IN74C74A is identical in pinout to the LS/ALS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they