Dual 4-Input AND Gate
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- Harvey Webster
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1 TENIAL DATA Dual 4-Input AND ate The is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the Dual 4-input AND function. Outputs Directly Interface to MOS, NMOS, and TTL Operating oltage Range: to Low Input urrent:. µa igh Noise Immunity haracteristic of MOS Devices ORDERIN INFORMATION N Plastic D SOI T A = -55 to 25 for all packages LOI DIARAM A PIN ASSINMENT B Y A B D2 2 D 5 B2 A2 Y ND 6 9 A2 Y2 B2 Y2 2 FUNTION TABLE D2 PIN 4 = PIN = ND Inputs Output A B С D Y L X X X L X L X X L X X L X L X X X L L X = don t care
2 MAXIMUM RATINS* Symbol Parameter alue Unit D Supply oltage (Referenced to ND) -.5 to +. IN D Input oltage (Referenced to ND) -.5 to +.5 OUT D Output oltage (Referenced to ND) -.5 to +.5 I IN D Input urrent, per Pin ±2 ma I OUT D Output urrent, per Pin ±25 ma I D Supply urrent, and ND Pins ±5 ma P D Power Dissipation in Still Air, Plastic DIP** SOI Package** Tstg Storage Temperature -65 to +5 T L Lead Temperature, mm from ase for Seconds (Plastic DIP or SOI Package) *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating onditions. **Derating - Plastic DIP: - mw/ from 65 to 25 SOI Package: : - mw/ from 65 to mw 26 REOMMENDED OPERATIN ONDITIONS Symbol Parameter Min Max Unit D Supply oltage (Referenced to ND) IN, OUT D Input oltage, Output oltage (Referenced to ND) T A Operating Temperature, All Package Types t r, t f Input Rise and Fall Time (Figure ) =2. = = ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be constrained to the range ND ( IN or OUT ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either ND or ). Unused outputs must be left open.
3 D ELETRIAL ARATERISTIS (oltages Referenced to ND) Symbol Parameter Test onditions uaranteed Limit Unit 25 to I Minimum igh-level Input oltage IL Maximum Low -Level Input oltage O OL I IL I I I I T Minimum igh-level Output oltage Maximum Low-Level Output oltage Maximum Low-Level Input Leakage urrent Maximum igh-level Input Leakage urrent Maximum Quiescent Supply urrent (per Package) Maximum Additional Quiescent Supply urrent on input pin IN = I or IL I OUT = - 5 µa IN = I or IL I OUT = - 4. ma IN = I or IL I OUT = 5 µa IN = I or IL I OUT = 4. ma IN = µa IN =... µa IN = or I OUT = µa IN =3.4 any one input, IN = or others inputs µa mа
4 A ELETRIAL ARATERISTIS ( L =5pF,Input t r =t f =6. ns) Symbol Parameter 25 to -55 uaranteed Limit 5 25 Unit t PL, t PL Maximum Propagation Delay (Figure ) ns t TL, t TL Maximum Output Transition Time (Figure ) ns IN Maximum Input apacitance 5. pf PD Power Dissipation apacitance (Per ate) Used to determine the no-load dynamic power consumption: P D = PD 2 f+i T A =25, =5. 5 pf t L t L Input I ND t PL t PL Output O t TL t TL =.3 = 3. I Figure. Switching Waveforms PULSE ENERATOR I R T DEIE UNDER TEST O L 5 pf Termination resistance R T should be equal to Z OUT of pulse generators Figure 2. Test ircuit
5 N SUFFIX PLASTI DIP (MS - AA) NOTES: 4 A F.25 (.) M T. Dimensions A, B do not include mold flash or protrusions. Maximum mold flash or protrusions.25 mm (.) per side. D N B -T- SEATIN 5.2 PLANE K D M J F J.25 (.) M T M NOTES: K..25. Dimensions A and B do not include mold flash or protrusion. M Maximum mold flash or protrusion.5 mm (.6) per side P for A; for B.25 mm (.) per side. R T- K SEATIN PLANE M L J Dimension, mm Symbol MIN MAX A B D F J K L M.2.36 N.3 D SUFFIX SOI (MS - 2AB) 4 A B P Symbol MIN MAX A.55.5 B D.33.5 F.4.2 R x 45 Dimension, mm.2
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CD40106BC Hex Schmitt Trigger General Description The CD40106BC Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N and P-channel enhancement transistors.
High Performance Silicon Gate CMOS
igh Performance Silicon Gate MOS The M7400A is identical in pinout to the S00. The device inputs are compatible with Standard MOS outputs; with pullup resistors, they are compatible with STT outputs. Output
M74HC20TTR DUAL 4-INPUT NAND GATE
DUAL 4-INPUT NAND GATE HIGH SPEED: t PD = 9ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power
Obsolete Product(s) - Obsolete Product(s)
3 TO 8 LINE DECODER HIGH SPEED: t PD = 15ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
74LS195 SN74LS195AD LOW POWER SCHOTTKY
The SN74LS95A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped
MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer
September 1983 Revised February 1999 MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer General Description The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate
CD4028BC BCD-to-Decimal Decoder
BCD-to-Decimal Decoder General Description The is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the 4 inputs, A,