12-Stage Binary Ripple Counter High-Voltage Silicon-Gate CMOS

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Abel Job Todd
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1 TECHNICAL DATA IW4040B 2-Stage Binary Ripple Counter High-oltage Silicon-Gate CMOS The IW4040B is ripple-carry binary counter. All counter stages are masterslave flip-flops. The state of a counter advances one count on the negative traition of each input pulse; a high level on the line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. Operating oltage Range: 3.0 to Maximum input current of μa at over full package-temperature range; 0 na at and 2 C Noise margin (over full package temperature range):.0 supply 2.0 supply 2. supply 6 6 N SUFFIX PLASTIC DIP ORDERING INFORMATION IW4040BN Plastic DIP IW4040BD SOIC T A = - to 2 C for all packages LOGIC DIAGRAM Q3 Q4 Q Q6 Q7 Q Q Q 2 PIN ASSIGNMENT 2 Q6 Q Q7 Q4 Q3 FUNCTION TABLE Inputs Output Clock Reset Output state L CC Q Q Q No change L Advance to next state X H All Outputs are low PIN 6 = CC PIN = H= high level L = low level X=don t care

2 MAXIMUM RATINGS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to ) -0. to +20 IN DC Input oltage (Referenced to ) -0. to CC +0. OUT DC Output oltage (Referenced to ) -0. to CC +0. I IN DC Input Current, per Pin ± ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 00* mw P tot Power Dissipation per Output Traistor 0 mw Tstg Storage Temperature -6 to +0 C T L Lead Temperature, mm from Case for Seconds 2 C (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. * For T A =- to 0 C (package plastic DIP), for T A =- to 6 C (package SOIC) +Derating - Plastic DIP: - 2 mw/ C from 0 С to 2 C SOIC Package: : - 7 mw/ C from 6 С to 2 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to ) 3.0 IN, OUT DC Input oltage, Output oltage (Referenced to ) 0 CC T A Operating Temperature, All Package Types - +2 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be cotrained to the range ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or CC ). Unused outputs must be left open.

3 DC ELECTRICAL CHARACTERISTICS (oltages Referenced to ) Symbol CC Guaranteed Limit Parameter Test Conditio 2 - C 2 C C IH IL OH OL I IN I CC I OL I OH Minimum High-Level Input oltage Maximum Low -Level Input oltage Minimum High-Level Output oltage Maximum Low-Level Output oltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Minimum Output High (Source) Current OUT =0. or CC - 0. OUT =.0 or CC -.0 OUT =. or CC -. OUT =0. or CC - 0. OUT =.0 or CC -.0 OUT =. or CC -. IN = or CC IN = or CC Unit IN = or CC ±0. ±0. ±.0 μa IN = or CC 20 IN = or CC U OL =0.4 U OL =0. U OL =. IN = or CC U OH =2. U OH =4.6 U OH =. U OH = μa ma ma

4 AC ELECTRICAL CHARACTERISTICS (C L =0 pf, R L = kω, t r =t f =20 ) Symbol Parameter CC f max Maximum Clock Frequency (Figure ) t PLH, t PHL Maximum Propagation Delay, Clock to (Figure ) t PLH, t PHL Maximum Propagation Delay, Q n to Q n+ (Figure 2) t PHL t TLH, t THL Maximum Propagation Delay, Reset to Any Q (Figure 3) Maximum Output Traition Time, Any Output (Figure ) Guaranteed Limit - C 2 C 2 C C IN Maximum Input Capacitance - 7. pf Unit MHz TIMING REQUIREMENTS (C L =0 pf, R L = kω, t r =t f =20 ) Symbol Parameter CC t w Minimum Pulse Width, Clock (Figure ) t w Minimum Pulse Width, Reset (Figure 3) t rem Minimum Removal Time, Reset(Figure 3) t r, t f Maximum Input Rise and Fall Times, Clock (Figure ) Guaranteed Limit - C 2 C 2 C Unlimited Unit Figure. Switching Waveforms Figure 2. Switching Waveforms

5 0% tw trem 0% CC CC t PHL ANY Q 0% Figure 3. Switching Waveforms CC TIMING DIAGRAM Clock Reset Q3 Q4 Q Q6 Q7 Q Q Q 2 EXPANDED LOGIC DIAGRAM CL CL2 CL3 CL7 2 FF CL FF2 CL2 CL3 FFI2 CL7 2 R R FF3-FF R Q3 2

6 N SUFFIX PLASTIC (MS - 00BB) A 6 G F 0.2 (0.0) M T D N B C -T- K SEATING PLANE NOTES:. imeio A, B do not include mold flash or protrusio. Maximum mold flash or protrusio 0.2 mm (0.0) per side. M L H J Dimeio, mm Symbol MIN MAX A.67.6 B C.33 D F.4.7 G 2.4 H 7.62 J 0 K L M N 0.3 D SUFFIX SOIC (MS - 02AC) 6 A Dimeio, mm Symbol. MIN MAX H B P A..0 B 3. 0 C.3.7 G D C R x 4 F T- SEATING G.27 D K PLANE J F M H (0.0) M T C M J 0 K NOTES: M Dimeio A and B do not include mold flash or protrusion. 2.Maximum mold flash or protrusion 0. mm (0.006) per side for A, for P B mm (0.0) per side. R

Dual JK Flip-Flop IW4027B TECHNICAL DATA PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE. Rev. 00

Dual JK Flip-Flop IW4027B TECHNICAL DATA PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE. Rev. 00 TECHNICAL DATA IW027B Dual JK Flip-Flop The IW027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and traferred