8-Input NAND Gate IN74HCT30A TECHNICAL DATA LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE. Rev. 00
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1 TENIL T IN74T3 8-Input NN ate The IN74T3 is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the 8-input NN function. Outputs irectly Interface to MOS, NMOS, and TTL Operating oltage Range: to Low Input urrent:. µ igh Noise Immunity haracteristic of MOS evices ORERIN INORMTION IN74T3N Plastic IN74T3 SOI T = for all packages LOI IRM E Y UNTION TLE PIN SSINMENT E N 7 8 Y PIN 4 = PIN 7 = N Inputs Output С E Y L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L L X = don t care
2 IN74T3 MXIMUM RTINS* Symbol Parameter alue Unit Supply oltage (Referenced to N) -.5 to +7. IN Input oltage (Referenced to N) -.5 to +.5 OUT Output oltage (Referenced to N) -.5 to +.5 I IN Input urrent, per Pin ±2 m I OUT Output urrent, per Pin ±25 m I Supply urrent, and N Pins ±5 m P Power issipation in Still ir, Plastic IP** SOI Package** Tstg Storage Temperature -65 to +5 T L Lead Temperature, mm from ase for Seconds (Plastic IP or SOI Package) *Maximum Ratings are those values beyond which damage to the device may occur. unctional operation should be restricted to the Recommended Operating onditions. **erating - Plastic IP: - mw/ from 65 to 25 SOI Package: : - 7 mw/ from 65 to mw 26 REOMMENE OPERTIN ONITIONS Symbol Parameter Min Max Unit Supply oltage (Referenced to N) IN, OUT Input oltage, Output oltage (Referenced to N) T Operating Temperature, ll Package Types t r, t f Input Rise and all Time (igure ) = = = ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. or proper operation, IN and OUT should be constrained to the range N ( IN or OUT ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either N or ). Unused outputs must be left open.
3 IN74T3 ELETRIL RTERISTIS (oltages Referenced to N) Symbol Parameter Test onditions uaranteed Limit Unit 25 to I IL O OL I IL I I I I T Minimum igh-level Input oltage Maximum Low -Level Input oltage Minimum igh-level Output oltage Maximum Low-Level Output oltage Maximum Low-Level Input Leakage urrent Maximum igh-level Input Leakage urrent Maximum Quiescent Supply urrent (per Package) Maximum dditional Quiescent Supply urrent OUT or OUT - I OUT 2 µ OUT or OUT - I OUT 2 µ IN = I or IL I OUT - 2 µ IN = I or IL I OUT - 4. m IN = I or IL I OUT 2 µ IN = I or IL I OUT 4. m IN = µ IN =.. µ IN = or I OUT = µ IN =2.4 any one input, IN = or, others inputs I OUT = µ 2 4 µ mа
4 IN74T3 ELETRIL RTERISTIS ( L =5p,Input t r =t f =6. ns) Symbol Parameter 25 to -55 uaranteed Limit Unit t PL, t PL Maximum Propagation elay (igure ) ns t TL, t TL Maximum Output Transition Time (igure ) ns IN Maximum Input apacitance 5. p P Power issipation apacitance (Per ate) Used to determine the no-load dynamic power consumption: P = P 2 f+i T =25, =5. 27 p t f t r Input N t PL t PL Output t TL t TL = 3 =.3 2 igure. Switching Waveforms PULSE ENERTOR I R T EIE UNER TEST O L 5 p Termination resistance R T should be equal to Z OUT of pulse generators igure 2. Test ircuit
5 IN74T3 N SUIX PLSTI IP (MS - ) NOTES: 4.25 (.) M T. imensions, do not include mold flash or protrusions. Maximum mold flash or protrusions.25 mm (.) per side. 8 7 N -T- SETIN 5.27 PLNE K M J J 8.25 (.) M T M NOTES: K.25. imensions and do not include mold flash or protrusion. M Maximum mold flash or protrusion 5 mm (.6) per side P for ; for.25 mm (.) per side. R T- K SETIN PLNE M L J imension, mm Symbol MIN MX J K L M.2.36 N.38 SUIX SOI (MS - 2) P Symbol MIN MX R x 45 imension, mm.27
8-Input NAND Gate IN74HC30A TECHNICAL DATA LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE. Rev. 00
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The SN74LS95A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped
SN74LS153D 74LS153 LOW POWER SCHOTTKY
74LS153 The LSTTL/MSI SN74LS153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. It can select two bits of data from four sources.
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
UNISONIC TECHNOLOGIES CO., LTD
UNISONIC TECHNOLOGIES CO., LTD BUS BUFFER/LINE DRIVER 3-STATE DESCRIPTION The U74LVC1G125 is a single bus buffer/line driver with 3-state output. When the output enable ( ΟΕ ) is high the output will be
MM74HC00 Quad 2-Input NAND Gate
MM74HC00 Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption
MC74VHC08. Quad 2-Input AND Gate
M7408 Quad 2-Input ND Gate The M7408 is an advanced high speed MOS 2 input ND gate fabricated with silicon gate MOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate Description: The NTE4501 is a triple gate device in a 16 Lead DIP type package constructed with MOS P
74VHC00 Quad 2-Input NAND Gate
Quad 2-Input NAND Gate General Description The HC00 is an advanced high-speed CMOS 2-Input NAND Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent
MC74HC374A. Octal 3-State Non-Inverting D Flip-Flop. High Performance Silicon Gate CMOS
M7H37A Octal 3-State Non-Inverting Flip-Flop High Performance Silicon Gate MOS The M7H37A is identical in pinout to the LS37. The device inputs are compatible with standard MOS outputs; with pullup resistors,
74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset
Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard