CD54/74HC30, CD54/74HCT30

Transcription

1 /70, /7T0 ata sheet acquired from arris Semiconductor SS ugust Revised September 00 igh Speed MOS Logic -Input NN ate [ /Title ( 0, 7 0, 7 T0) /Subject (igh Speed MOS Logic - eatures uffered Inputs Typical Propagation elay: 0ns at = V, L = p, T = o anout (Over Temperature Range) - Standard Outputs LS - us river Outputs LS Wide Operating Temperature Range... - o to o alanced Propagation elay and Transition Times Significant Power Reduction ompared to LSTTL Logic Is Types - V to V Operation - igh Noise Immunity: N IL = 0%, N I = 0% of at = V T Types -.V to.v Operation - irect LSTTL Input Logic ompatibility, = 0.V (Max), V I = V (Min) - MOS Input ompatibility, I l µ at V OL, V O escription The 0 and T0 each contain an -input NN gate in one package. They provide the system designer with the direct implementation of the positive logic -input NN function. Logic gates utilize silicon gate MOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard MOS integrated circuits. ll devices have the ability to drive 0 LSTTL loads. The T logic family is functionally pin compatible with the standard LS logic family. Ordering Information PRT NUMR TMP. RN ( o ) PK 0 - to Ld RIP T0 - to Ld RIP 70 - to Ld PIP 70M - to Ld SOI 70MT - to Ld SOI 70M9 - to Ld SOI 70NSR - to Ld SOP Pinout 0, T0 (RIP) 70 (PIP, SOI, SOP, TSSOP) 7T0 (PIP, SOI) TOP VIW 70PW - to Ld TSSOP 70PWR - to Ld TSSOP 70PWT - to Ld TSSOP 7T0 - to Ld PIP 7T0M - to Ld SOI 7T0MT - to Ld SOI 7T0M9 - to Ld SOI NOT: When ordering, use the entire part number. The suffixes 9 and R denote tape and reel. The suffix T denotes a small-quantity reel of 0. UTION: These devices are sensitive to electrostatic discharge. Users should follow proper I andling Procedures. opyright 00, Texas Instruments Incorporated.

2 unctional iagram = TRUT TL S L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L L NOT: = I Level, L = LOW Level, X = Irrelevant Logic Symbol

3 bsolute Maximum Ratings Supply, V to 7V Input iode, I IK or V I < -0.V or V I > + 0.V ±0m Output iode, I OK or V O < -0.V or V O > + 0.V ±0m Output Source or Sink per Output Pin, I O or V O > -0.V or V O < + 0.V ±m or round, I or I ±0m Operating onditions Temperature Range (T ) o to o Supply Range, Types V to V T Types V to.v Input or Output, V I, V O V to Input Rise and all Time V ns (Max).V ns (Max) V ns (Max) Thermal Information Package Thermal Impedance, θ J (see Note ) (PIP) Package o /W M (SOI) Package o /W NS (SOP) Package o /W PW (TSSOP) Package o /W Maximum Junction Temperature (ermetic Package or ie)... 7 o Maximum Junction Temperature (Plastic Package) o Maximum Storage Temperature Range o to 0 o Maximum Lead Temperature (Soldering 0s) o (SOI - Lead Tips Only) UTION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOT:. The package thermal impedance is calculated in accordance with JS -7. lectrical Specifications TPS igh Level Input Low Level Input Input Leakage o -0 o TO + o - o TO o V I (V) I O (m) (V) MIN TP MX MIN MX MIN MX V I V V V V V V V O V OL I I V I or V V V V V V V I or V V V or V V V ±0. - ± - ± µ

4 lectrical Specifications (ontinued) Quiescent evice T TPS igh Level Input Low Level Input Input Leakage Quiescent evice dditional Quiescent evice Per Input Pin: Unit Load (Note ) I or V I - -. to to. V O V OL I I I I o -0 o TO + o - o TO o V I (V) I O (m) (V) MIN TP MX MIN MX MIN MX µ V V V I or V V V I or V and or V -. - ±0. - ± - ± µ µ -. to. NOT:. or dual-supply systems theoretical worst case (V I =.V, =.V) specification is.m. T Input Loading Table µ UNIT LOS ll 0. NOT: Unit Load is I limit specified in lectrical Specifications table, e.g. 0µ max at o. Switching Specifications Input t r, t f = ns TPS Propagation elay, Input to Output (igure ) Propagation elay, ata Input to Output (V) o -0 o TO o - o TO o MIN TP MX MIN MX MIN MX t PL, t PL L = 0p ns ns ns t PL, t PL L = p ns

5 Switching Specifications Input t r, t f = ns (ontinued) Transition Times (igure ) t TL, t TL L = 0p ns ns ns Input apacitance I p Power issipation apacitance (Notes, ) P p T TPS Propagation elay, Input to Output (igure ) Propagation elay, ata Input to Output t RL, t PL L = 0p ns t PL, t PL L = p ns Transition Times (igure ) t TL, t TL L = 0p ns Input apacitance I p Power issipation apacitance (Notes, ) P p NOTS:. P is used to determine the dynamic power consumption, per gate.. P = V f i ( P + L ) where f i = Input requency, L = Output Load apacitance, = Supply. (V) o -0 o TO o - o TO o MIN TP MX MIN MX MIN MX Test ircuits and Waveforms t r = ns t f = ns t r = ns t f = ns 0% 0%.7V.V 0.V V t TL t TL t TL t TL INVRTIN t PL t PL 0% 0% INVRTIN t PL t PL.V 0% IUR. N U TRNSITION TIMS N PROP- TION L TIMS, OMINTION LOI IUR. T TRNSITION TIMS N PROPTION L TIMS, OMINTION LOI