CD54/74HC147, CD74HCT147. High Speed CMOS Logic 10-to-4 Line Priority Encoder. Features. [ /Title (CD74 HC147, CD74 HCT14 7) /Subject

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1 CD/7HC7, CD7HCT7 Data sheet acquired from Harris Semiconductor SCHS9B September Revised March 00 High 0-to- Encoder [ /Title (CD7 HC7, CD7 HCT 7) /Subject (High 0-to- Encode r) /Autho r () /Keywords (High 0-to- Encode r, High 0-to- Features Buffered Inputs and Outputs Typical Propagation Delay: ns at = V, C L = pf, T A = o C Fanout (Over Temperature Range) - Standard Outputs LS - Bus Driver Outputs LS Wide Operating Temperature Range... - o C to o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL ICs HC Types - V to 6V Operation - High Noise Immunity: N IL = 0%, N IH = 0% of at = V HCT Types -.V to.v Operation - Direct LSTTL Input Compatibility, V IL = 0.8V (Max), V IH = V (Min) - Input Compatibility, I l µa at V OL, V OH Description The HC7 and CD7HCT7 are high speed silicon-gate devices and are pin-compatible with low power Schottky TTL (LSTTL). Pinout I I I6 I7 I8 Y Y CDHC7 (CERDIP) CD7HC7 (PDIP, SOIC, SOP) CD7HCT7 (PDIP, SOIC) TOP VIEW The HC7 and CD7HCT7 9-input priority encoders accept data from nine active LOW inputs (l to l 9 ) and provide binary representation on the four active LOW inputs (Y0 to Y). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line l 9 having the highest priority. These devices provide the 0-line to -line priority encoding function by use of the implied decimal zero. The zero is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CDHC7FA - to 6 Ld CERDIP CD7HC7E - to 6 Ld PDIP CD7HC7M - to 6 Ld SOIC CD7HC7NSR - to 6 Ld SOP CD7HCT7E - to 6 Ld PDIP CD7HCT7M - to 6 Ld SOIC NOTES:. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. 6 NC Y I I I 0 I9 9 Y0 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 00, Texas Instruments Incorporated

2 Functional Diagram I I I I I I6 I7 I8 I Y0 Y Y Y = 8 = 6 TRUTH TABLE S OUTPUTS I I I I I I6 I7 I8 I9 Y Y Y Y0 H H H H H H H H H H H H H X X X X X X X X L L H H L X X X X X X X L H L H H H X X X X X X L H H H L L L X X X X X L H H H H L L H X X X X L H H H H H L H L X X X L H H H H H H L H H X X L H H H H H H H H L L X L H H H H H H H H H L H L H H H H H H H H H H H L NOTE: H = High Level, L = Low Level, X = Don t Care

3 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode, I IK For V I < -0.V or V I > + 0.V ±0mA DC Output Diode, I OK For V O < -0.V or V O > + 0.V ±0mA DC Output Source or Sink per Output Pin, I O For V O > -0.V or V O < + 0.V ±mA DC or Ground, I CC or I ±0mA Thermal Information Package Thermal Impedance, θ JA (see Note ): PDIP Package o C/W SOIC Package o C/W SOP Package o C/W Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 0 o C Maximum Lead Temperature (Soldering 0s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range (T A ) o C to o C Supply Range, HC Types V to 6V HCT Types V to.v DC Input or Output, V I, V O V to Input Rise and Fall Time V ns (Max).V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. The package thermal impedance is calculated in accordance with JESD -7. DC Electrical Specifications HC TYPES High Level Input Low Level Input Input Leakage Quiescent Device V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V IH or V IL V V V V V V V OL V IH or V IL V V V I I I CC or or V V V ±0. - ± - ± µa µa

4 DC Electrical Specifications (Continued) HCT TYPES High Level Input Low Level Input Input Leakage Quiescent Device Additional Quiescent Device Per Input Pin: Unit Load V IH - -. to. V IL - -. to V V V OH V IH or V IL V V V OL V IH or V IL V I I I CC I CC V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX and or V 0. - ±0. - ± - ± µa µa -. to. NOTE: For dual-supply systems theoretical worst case (V I =.V, =.V) specification is.8ma. HCT Input Loading Table µa UNIT LOADS I, I, I, I 6, I 7. I, I, I 8, I 9. NOTE: Unit Load is I CC limit specified in DC Electrical Table, e.g., 60µA max at o C. Switching Specifications Input t r, t f = 6ns (V) MIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation Delay, Input to Output (Figure ) t PLH, t PHL C L = 0pF ns ns ns ns Transition Times (Figure ) t TLH, t THL C L = 0pF ns ns ns Input Capacitance C IN pf

5 Switching Specifications Input t r, t f = 6ns (Continued) (V) MIN TYP MAX MIN MAX MIN MAX Power Dissipation Capacitance (Notes, ) HCT TYPES Propagation Delay, Input to Output (Figure ) C PD pf t PLH, t PHL C L = 0pF ns ns Transition Times (Figure ) t TLH, t THL C L = 0pF ns Input Capacitance C IN pf Power Dissipation Capacitance (Notes, ) C PD pf NOTES:. C PD is used to determine the dynamic power consumption, per gate.. P D = V CC f i (C PD + C L ) where f i = Input Frequency, C L = Output Load Capacitance, = Supply. Test Circuits and Waveforms t r = 6ns t f = 6ns t r = 6ns t f = 6ns 0% 0%.7V.V 0.V V t THL t TLH t THL t TLH INVERTING OUTPUT t PHL t PLH 0% 0% INVERTING OUTPUT t PHL t PLH.V 0% FIGURE 6. HC AND HCU TRANSITION TIMES AND PROPAGA- TION DELAY TIMES, COMBINATION LOGIC FIGURE 7. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC