CD54HC257, CD74HC257, CD54HCT257, CD74HCT257

Transcription

1 CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Data sheet acquired from Harris Semiconductor SCHS171D November Revised October 2003 High-Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs [ /Title (CD74 HC257, CD74 HCT25 7) /Subject (High Speed CMOS Logic Quad 2-Input Multiplexer Features Buffered Inputs Typical ( In to Output ) = 12ns at = 5V, C L = 15pF, T A = 25 o C Fanout (Over Temperature Range) - Standard Outputs LS - Bus Driver Outputs LS Wide Operating Temperature Range o C to 125 o C Balanced and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Description The HC257 and HCT257 are quad 2-input multiplexers which select four bits of data from two sources under the control of a common Select Input (S). The Output Enable input (OE) is active LOW. When OE is HIGH, all of the outputs (1Y-4Y) are in the high impedance state regardless of all other input conditions. Moving data from two groups of registers to four common output buses is a common use of the 257. The state of the Select input determines the particular register from which the data comes. It can also be used as a function generator. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC257F3A -55 to Ld CERDIP CD54HCT257F3A -55 to Ld CERDIP CD74HC257E -55 to Ld PDIP CD74HC257M -55 to Ld SOIC CD74HC257MT -55 to Ld SOIC CD74HC257M96-55 to Ld SOIC CD74HCT257E -55 to Ld PDIP CD74HCT257M -55 to Ld SOIC CD74HCT257MT -55 to Ld SOIC CD74HCT257M96-55 to Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC257, CD54HCT257 (CERDIP) CD74HC257, CD74HCT257 (PDIP, SOIC) TOP VIEW S I OE 1I I 0 1Y I 1 2I Y 2I I 0 2Y I Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2003, Texas Instruments Incorporated 1

2 Functional Diagram CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 OE S I 1 4I P N 12 4Y 3I 1 3I 0 2I 1 2I 0 1I 1 1I CIRCUITS IDENTICAL TO CIRCUIT IN ABOVE DASHED ENCLOSURE Y 2Y 1Y TRUTH TABLE ENABLE SELECT INPUT DATA INPUTS OE S I 0 I 1 Y H X X X Z L L L X L L L H X H L H X L L L H X H H H= High Level L= Low Level X= Don t Care Z= High Impedance, OFF State 2

3 CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Output Diode, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Drain, per Output, I O For -0.5V < V O < + 0.5V ±35mA DC Output Source or Sink per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground, I CC ±70mA Thermal Information Thermal Resistance (Typical, Note 1) θ JA ( o C/W) E (PDIP) Package M (SOIC) Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 125 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD DC Electrical Specifications TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER SYMBOL V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input V IH V V V Low Level Input V V V OH V OL V V IH or V V V V V V IH or V V V V V Input Leakage I I or ±0.1 - ±1 - ±1 µa 3

4 CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 DC Electrical Specifications (Continued) TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER SYMBOL V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX UNITS Quiescent Device I CC or µa Three-State Leakage HCT TYPES I OZ or ±0.5 - ±5 - ±10 µa V IH High Level Input Low Level Input V IH to to V V V OH V OL V IH or V V V IH or V V Input Leakage I I to ±0.1 - ±1 - ±1 µa Quiescent Device I CC or µa Additional Quiescent Device Per Input Pin: 1 Unit Load I CC (Note 2) to µa Three-State Leakage I OZ or ±0.5 - ±5 - ±10 µa V IH NOTE: 2. For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS Data 0.95 S 3 OE 0.6 NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25 o C. 4

5 CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Switching Specifications Input t r, t f = PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX UNITS HC TYPES In to Y t PLH, t PHL C L = 50pF ns ns C L = 15pF ns CL = 50pF ns S to Y t PLH, t PHL C L = 50pF ns ns C L = 15pF ns CL = 50pF ns OE to Y t PLZ, t PHZ, CL = 50pF ns t PZL, t PZH C L = 50pF ns C L = 15pF ns CL = 50pF ns Output Transition Times t TLH, t THL C L = 50pF ns ns ns Input C I pf Three-State Output Power Dissipation (Notes 3, 4) HCT TYPES In to Y S to Y OE to Y C O pf C PD pf t PLH, t PHL C L = 50pF ns C L = 15pF ns t PZL, t PZH C L = 50pF ns C L = 15pF ns t PLZ, t PHZ C L = 50pF ns C L = 15pF ns Output Transition Times t TLH, t THL C L = 50pF ns Input C I pf Three-State Output Power Dissipation (Notes 3, 4) C O pf C PD pf NOTES: 3. C PD is used to determine the dynamic power consumption, per multiplexer. 4. P D = V 2 CC f i (C PD + C L ) where f i = Input Frequency, C L = Output Load, = Supply. 5

6 Test Circuits and Waveforms CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 t r = t f = t r = t f = INPUT INPUT 2.7V 0.3V 3V t THL t TLH t THL t TLH INVERTING t PHL t PLH INVERTING t PHL t PLH FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC DISABLE t r DISABLE t f V tplz t PZL t PLZ t PZL LOW LOW HIGH t PHZ t PZH HIGH t PHZ t PZH S S DISABLED S S S DISABLED S FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW DISABLE IC WITH THREE- STATE R L = 1kΩ C L 50pF FOR t PLZ AND t PZL FOR t PHZ AND t PZH NOTE: Open drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left. The test circuit is Output R L =1kΩ to, C L = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 6