CD74HC109, CD74HCT109

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Data sheet acquired from Harris Semiconductor SCHS140 March 1998 CD74HC109, CD74HCT109 Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title (CD74H C109, CD74H CT109) /Subject Dual J-

1 Data sheet acquired from Harris Semiconductor SCHS140 March 1998 CD74HC109, CD74HCT109 Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title (CD74H C109, CD74H CT109) /Subject Dual J- Fliplop ith Set nd eset Features Asynchronous Set and Reset Schmitt Trigger Clock Inputs Typical Propagation Delay = 18ns at = 5V, C L = 15pF, T A = 25 o C Typical f MAX = 60MHz at = 5V, C L = 15pF, T A = 25 o C Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Description The Harris CD74HC109 and CD74HCT109 are dual J-K flipflops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S and R, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. Pinout CD74HC109, CD74HCT109 (PDIP, SOIC) TOP VIEW 1R J R 1K J 1CP K 1S CP 1Q S 1Q Q 8 9 2Q CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation File Number

2 Functional Diagram 1S 5 1J 1K 1CP 1R F/F Q 1Q 2S 11 2J 14 2K CP 2R 15 F/F Q 2Q = 8 = 16 TRUTH TABLE S OUTPUTS S R CP J K Q Q L H X X X H L H L X X X L H L L X X X H (Note 3) H (Note 3) H H L L L H H H H L Toggle H H L H No Change H H H H H L H H L X X No Change NOTES: H= High Level (Steady State) L= Low Level (Steady State) X= Don t Care = Low-to-High Transition 3. Unpredictable and unstable condition if both S and R go high simultaneously. Logic Diagram 5(11) S 2(14) J J S Q 6(10) Q 3(13) K FF K CL CL R Q 7(9) Q 4(12) CP 1(15) R

3 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Drain Current, per Output, I O For -0.5V < V O < + 0.5V ±25mA DC Output Diode Current, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground Current, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 4) θ JA ( o C/W) PDIP Package SOIC Package Maximum Junction Temperature (Hermetic Package or Die) o C Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 125 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to C P Input Rise and Fall Time, t r, t f 2V ms (Max) 4.5V ms (Max) 6V ms (Max) Input Rise and Fall Time (All Inputs Except C P ), t r, t f 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS HC TYPES SYMBOL V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input V IH V V V Low Level Input V IL V V High Level Output CMOS Loads High Level Output TTL Loads V OH V V IH or V V IL V V V V V 3

4 DC Electrical Specifications (Continued) Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current Quiescent Device Current HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load SYMBOL V OL I I I CC V IH or V V IL V V or or V IH to 5.5 V IL to 5.5 V OH V OL I I I CC I CC (Note 5) TEST CONDITIONS V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V V V ±0.1 - ±1 - ±1 µa µa V V V IH or V V IL V V IH or V V IL and or V ±0.1 - ±1 - ±1 µa µa to 5.5 NOTE: 5. For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. UNITS µa HCT Input Loading Table UNIT LOADS All 0.3 NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25 o C. 4

5 Prerequisite For Switching Specifications TEST SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Setup Time J, K, to CP t SU ns ns ns Hold Time J, K, to CP t H ns ns ns Removal Time R, S, to CP t REM ns ns ns Pulse Width CP, R, S t W ns ns ns CP Frequency f MAX MHz MHz MHz HCT TYPES Setup Time J, K to CP t SU ns Hold Time J, K to CP t H ns Removal Time R, S, to CP t REM ns Pulse Width CP, R, S t W ns CP Frequency f MAX MHz Switching Specifications Input t r, t f = 6ns HC TYPES CP Q, Q S Q S Q SYMBOL TEST CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS t PLH, t PHL C L = 50pF ns C L = 50pF ns C L = 15pF ns C L = 50pF ns t PLH, t PHL C L = 50pF ns C L = 50pF ns C L = 15pF ns C L = 50pF ns t PLH, t PHL C L = 50pF ns C L = 50pF ns C L = 15pF ns C L = 50pF ns 5

6 Switching Specifications Input t r, t f = 6ns (Continued) R Q t PLH, t PHL C L = 50pF ns C L = 50pF ns C L = 15pF ns C L = 50pF ns t PLH, t PHL C L = 50pF ns R Q C L = 50pF ns C L = 15pF ns C L = 50pF ns Transition Time t TLH, t THL C L = 50pF ns C L = 50pF ns C L = 50pF ns Input Capacitance C I pf CP Frequency f MAX C L = 15pF MHz Power Dissipation Capacitance (Notes 6, 7) C PD pf HCT TYPES CP Q, Q S Q S Q R Q SYMBOL TEST CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX t PLH, t PHL C L = 50pF ns C L = 15pF ns t PLH, t PHL C L = 50pF ns C L = 15pF ns t PLH, t PHL C L = 50pF ns C L = 15pF ns t PLH, t PHL C L = 50pF ns C L = 15pF ns t PLH, t PHL C L = 50pF ns R Q C L = 15pF ns Transition Time (Figure 5 t TLH, t THL C L = 50pF ns Input Capacitance C I pf CP Frequency f MAX CL = 15pF MHz Power Dissipation Capacitance (Notes 6, 7) C PD pf NOTES: 6. C PD is used to determine the dynamic power consumption, per flip-flop. 7. P D = C PD V 2 CC f i + Σ C L f o where f i = input frequency, f o = output frequency, C L = output load capacitance, = supply voltage. UNITS 6

7 Test Circuits and Waveforms t r C L CLOCK t f C L I t WL + t WH = fcl t r C L = 6ns CLOCK t f C L = 6ns I t WL + t WH = fcl 2.7V t WL t WH t WL t WH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 7. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 8. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH t r = 6ns t f = 6ns t r = 6ns t f = 6ns 2.7V 0. t THL t TLH t THL t TLH INVERTING OUTPUT t PHL t PLH INVERTING OUTPUT t PHL t PLH FIGURE 9. HC AND HCU TRANSITION TIMES AND PROPAGA- TION DELAY TIMES, COMBINATION LOGIC FIGURE 10. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC CLOCK t r C L t f C L CLOCK t r C L 2.7V 0. t f C L t H(H) t H(L) t H(H) t H(L) DATA t SU(H) t SU(L) DATA t SU(H) t SU(L) OUTPUT t TLH t THL OUTPUT t TLH t THL t PLH t PHL t PLH t PHL t REM SET, RESET OR PRESET t REM SET, RESET OR PRESET IC C L 50pF IC C L 50pF FIGURE 11. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 12. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7

8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated

CD74HC151, CD74HCT151

Data sheet acquired from Harris Semiconductor SCHS150 September 1997 CD74HC151, CD74HCT151 High Speed CMOS Logic 8-Input Multiplexer [ /Title (CD74H C151, CD74H CT151) /Subject High peed MOS ogic 8- nput