High Performance Silicon Gate CMOS
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- Chester Watkins
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1 SEIONDUTOR TEHNIAL DATA HighPerformance Siliconate OS The H is identical in pinout to the LS. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with LSTTL outputs. The H decodes a D Address to oneoften active low outputs. or Address inputs with a hexadecimal equivalent greater than, all outputs, Y0 Y, remain high (inactive). Output Drive apability: 0 LSTTL Loads Outputs Directly Interface to OS, NOS, and TTL Operating Range: to Low Input urrent: µa High Noise Immunity haracteristic of OS Devices In ompliance with the Requirements Defined by EDE Standard No. A hip omplexity: 0 ETs or Equivalent ates N SUIX PLASTI PAAE ASE 808 D SUIX SOI PAAE ASE 0 ORDERIN INORATION HXXN HXXD Plastic SOI LOI DIARA PIN ASSINENT Y0 Y D ADDRESS INPUTS (LS) A A Y0 Y Y Y Y Y Y ATIE LOW OUTPUTS Y Y Y Y Y ND 8 0 A A A Y Y Y A (S) 0 Y PIN = PIN 8 = ND 0/ otorola, Inc. RE
2 H ÎÎ AXIU RATINS* Symbol Parameter alue Unit ÎÎ D Supply (Referenced to ND) 0. to +.0 inîî D Input (Referenced to ND). to +. outîî D Output (Referenced to ND) 0. to + 0. Iin ÎÎ D Input urrent, per Pin ± 0 ma Iout ÎÎ D Output urrent, per Pin ± ma IÎÎ D Supply urrent, and ND Pi ± 0 ma PD ÎÎ Power Dissipation in Still Air Plastic DIP 0 SOI Package ÎÎ mw 00 TstgÎÎ Storage Temperature to + 0 LÎÎ ÎÎ T Lead Temperature, mm from ase for 0 Seconds (Plastic DIP or SOI Package) 0 * aximum Ratings are those values beyond which damage to the device may occur. unctional operation should be restricted to the Recommended Operating onditio. Derating Plastic DIP: 0 mw/ from to SOI Package: mw/ from to or high frequency or heavy load coideratio, see hapter of the otorola HighSpeed OS Data ook (DL/D). REOENDED OPERATIN ONDITIONS Î Symbol ÎÎ Parameter in ax Unit Î ÎÎ D Supply (Referenced to ND).0.0 Î in, out ÎÎ D Input, Output (Referenced to ND) 0 TA Operating Temperature, All Package Types Î + Î tr, tf ÎÎ Input Rise and all Time =.0 ÎÎ (igure ) =. ÎÎ = D ELETRIAL HARATERISTIS (s Referenced to ND) uaranteed Limit to Î Symbol Parameter Test onditio Î 8 Î Unit Î IH inimum HighLevel Input out = 0. or 0. Î ÎÎ Iout.0.. Î. Î 0 µa Î Î. Î. IL aximum LowLevel Input out = 0. or 0. Iout.0 0 µa Î Î 0. Î 0. Î 0. Î.0... OH inimum HighLevel Output in = IH or IL Iout.0 0 µa Î.... Î. Î. Î. Î.0... Î in = IH or IL Iout.0. Iout. ma.0.8î Î OL aximum LowLevel Output in = IH or IL Iout.0 0 µa Î Î 0. Î 0. Î 0. Î Î in = IH or IL Iout.0. Iout. ma.0 0.Î Î Iin aximum Input Leakage urrent in = or ND.0 ± 0.Î ±.0 Î µa I aximum Quiescent Supply in = or ND µa urrent (per Package) Iout = 0 µa This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this highimpedance circuit. or proper operation, in and out should be cotrained to the range ND (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either ND or ). Unused outputs must be left open. NOTE: Information on typical parametric values can be found in hapter of the otorola HighSpeed OS Data ook (DL/D). OTOROLA HighSpeed OS Logic Data DL Rev
3 H A ELETRIAL HARATERISTIS (L = 0 p, Input tr = tf = ) uaranteed Limit to Î SymbolÎÎ Parameter 8 Î Unit Î tplh, ÎÎ aximum Propagation Delay, Input A to Output Y Î.0 Î 0 0 Î Î tphl (igures and ) Î Î 8 ttlh, aximum Output Traition Time, Any Output.0 Î Î 0 tthl (igures and )..0 aximum Input apacitance p in. or propagation delays with loads other than 0 p, see hapter of the otorola HighSpeed OS Data ook (DL/D).. Information on typical parametric values can be found in hapter of the otorola HighSpeed OS Data ook (DL/D). =.0 PD Power Dissipation apacitance (Per Package)* p * Used to determine the noload dynamic power coumption: PD = PD f + I. or load coideratio, see hapter of the otorola HighSpeed OS Data ook (DL/D). INPUT A OUTPUT Y 0% 0% 0% tr 0% 0% 0% tphl tf ND tplh DEIE UNDER TEST OUTPUT TEST POINT L* tthl ttlh * Includes all probe and jig capacitance igure. Switching Waveforms igure. Test ircuit Inputs UNTION TALE Outputs A A A Y0 Y Y Y Y Y Y Y Y L L L L L H H H H H H H H H L L L H H L H H H H H H H H L L H L H H L H H H H H H H L L H H H H H L H H H H H H L H L L H H H H L H H H H H L H L H H H H H H L H H H H L H H L H H H H H H L H H H L H H H H H H H H H H L H H H L L L H H H H H H H H L H H L L H H H H H H H H H H L H L H L H H H H H H H H H H H L H H H H H H H H H H H H H H L L H H H H H H H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H H H H H H HighSpeed OS Logic Data DL Rev OTOROLA
4 H PIN DESRIPTIONS INPUTS, A, A, A, (Pi,,, ) D Address Inputs. The D address present at these inputs determines which output is activelow. These inputs are arranged such that A is the mostsignificant bit and is the least significant bit. Addresses with a hexadecimal equivalent number greater than nine are not decoded OUTPUTS Y0 Y (Pi, ) ActiveLow Decoded Outputs. These outputs assume a low level when addressed and remain high when not addressed. EXPANDED LOI DIARA Y0 Y Y Y A Y Y A Y Y A 0 Y OTOROLA HighSpeed OS Logic Data DL Rev
5 H OUTLINE DIENSIONS A 8 H S T SEATIN PLANE D PL 0. (0.00) T A N SUIX PLASTI PAAE ASE 808 ISSUE R L. DIENSIONIN AND TOLERANIN PER ANSI Y., 8.. ONTROLLIN DIENSION: INH.. DIENSION L TO ENTER O LEADS WHEN ORED PARALLEL.. DIENSION DOES NOT INLUDE OLD LASH.. ROUNDED ORNERS OPTIONAL. DI A D H L S INHES IN AX S 0.00 S ILLIETERS IN AX S. S T SEATIN PLANE 8 A D PL 0. (0.00) T S A S D SUIX PLASTI SOI PAAE ASE 0 ISSUE P 8 PL 0. (0.00) R X. DIENSIONIN AND TOLERANIN PER ANSI Y., 8.. ONTROLLIN DIENSION: ILLIETER.. DIENSIONS A AND DO NOT INLUDE OLD PROTRUSION.. AXIU OLD PROTRUSION 0. (0.00) PER SIDE.. DIENSION D DOES NOT INLUDE DAAR PROTRUSION. ALLOWALE DAAR PROTRUSION SHALL E 0. (0.00) TOTAL IN EXESS O THE D DIENSION AT AXIU ATERIAL ONDITION. DI A D P R ILLIETERS IN AX INHES IN AX S 0.00 S otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation coequential or incidental damages. Typical parameters can and do vary in different applicatio. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any licee under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: otorola Literature Distribution; APAN: Nippon otorola Ltd.; TatsumiSPDLD, Toshikatsu Otsuki, P.O. ox 0; Phoenix, Arizona Seibuutsuryuenter, Tatsumi otou, Tokyo, apan. 08 AX: RAX0@ .sps.mot.com TOUHTONE (0) 0 HON ON: otorola Semiconductors H.. Ltd.; 8 Tai Ping Industrial Park, INTERNET: Ting ok Road, Tai Po, N.T., Hong ong. 88 HighSpeed OS Logic Data DL Rev ODELINE H/D OTOROLA
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MC74AC32, MC74ACT32 Quad 2 Input NAND Schmitt Trigger The MC74AC/74ACT32 contains four 2 input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter free
74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 4HC4 is identical in pinout to the LS4. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they
The MC10107 is a triple 2 input exclusive OR/NOR gate. P D = 40 mw typ/gate (No Load) t pd = 2.8 ns typ t r, t f = 2.
The MC10107 is a triple input exclusive OR/NOR gate. P D = 0 mw typ/gate (No Load) t pd =. ns typ t r, t f =. ns typ (0% 0%) LOGIC DIAGRAM MARKING DIAGRAMS CDIP 16 L SUFFIX CASE 60 16 1 MC10107L AWLYYWW
LOW POWER SCHOTTKY. ESD > 3500 Volts. GUARANTEED OPERATING RANGES ORDERING INFORMATION V CC 8 7 GND
ESD > 3500 Volts V CC 8 4 3 2 0 9 LOW POWER SCHOTTKY 2 3 4 5 6 7 GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage 4.75 5.0 5.25 V T A Operating Ambient Temperature
MC14511B. MARKING DIAGRAMS 16. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2) ORDERING INFORMATION
The MC14511B BCD to seven segment latch/decoder/driver is cotructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides
MC74AC259, MC74ACT Bit Addressable Latch
8-Bit Addressable Latch The MC259/T259 is a high speed 8 bit addressable latch designed for general purpose storage applicatio in digital systems. It is a multifunctional device capable of storing single
74HCT245. Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs. High-Performance Silicon-Gate CMOS
Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS The 74HCT245 is identical in pinout to LS245. The device has TTL-Compatible Inputs. The HCT245
MC Bit Magnitude Comparator
Bit Magnitude Comparator The MC0 is a high speed expandable bit comparator for comparing the magnitude of two binary words. Two outputs are provided: and. A = B can be obtained by NORing the two outputs
8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SHIFT RESISTER High-Performance Silicon-Gate CMOS
TECNICAL DATA 8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SIFT RESISTER igh-performance Silicon-ate CMOS The may be used as a level converter for interfacing TTL or NMOS outputs to high-speed CMOS inputs. The is
MC74HCT366A. Hex 3-State Inverting Buffer with Common Enables and LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
ex 3-State Inverting Buffer with Common Enables and STT Compatible Inputs igh Performance Silicon Gate CMOS The MC74CT366A is identical in pinout to the S366. The device inputs are compatible with standard
Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS
TECHNICAL DATA IN74HC193A Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS The IN74HC193A is identical in pinout to the LS/ALS193. The device inputs are compatible with standard
Octal 3-State Noninverting Transparent Latch
TECNICAL DATA IN74CT373A Octal 3-State Noninverting Transparent Latch The IN74CT373A may be used as a level converter for interfacing TTL or NMOS outputs to igh-speed CMOS inputs. The IN74CT373A is identical
NL17SHT08. 2-Input AND Gate / CMOS Logic Level Shifter
N7ST08 -Input AND Gate / CMOS ogic evel Shifter The N7ST08 is an advanced high speed CMOS input AND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
MC14020B. 14-Bit Binary Counter
M4020B 4-Bit Binary ounter The M4020B 4stage binary counter is cotructed with MOS Phannel and Nhannel enhancement mode devices in a single monolithic structure. This part is designed with an input wave
LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES ORDERING INFORMATION. SN74LS37xN AWLYYWW PDIP 20 N SUFFIX CASE 738
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is
Presettable Counters High-Performance Silicon-Gate CMOS
TECHNICAL DATA IN74HC1A Presettable Counters High-Performance Silicon-Gate CMOS The IN74HC1A is identical in pinout to the LS/ALS1. The device inputs are compatible with standard CMOS outputs; with pullup
MC74HC4040A. 12 Stage Binary Ripple Counter. High Performance Silicon Gate CMOS
M74HA 2 Stage Binary Ripple ounter High Performance Silicon Gate MOS The M74A is identical in pinout to the standard MOS M. The device inputs are compatible with standard MOS outputs; with pullup resistors,
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163. Synchronous Presettable Binary Counter
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 Synchronous Presettable Binary Counter The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high speed synchronous modulo 16 binary counters. They are synchronously
CONNECTION DIAGRAM (TOP VIEW) 20. Note: Pin 1 is marked for orientation. Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74
FOUR-BIT UP/DOWN COUNTER WITH THREE-STATE OUTPUTS The SN54/ LS569A is designed as programmable up/down BCD and Binary counters respectively. These devices have 3-state outputs for use in bus organized
74AC00, 74ACT00 Quad 2-Input NAND Gate
74AC00, 74ACT00 Quad 2-Input NAND Gate Features I CC reduced by 50% Outputs source/sink 24mA ACT00 has TTL-compatible inputs Ordering Information Order Number Package Number General Description The AC00/ACT00
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10173L AWLYYWW
The MC03 is a quad two channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data
High Performance Silicon Gate CMOS
High Performance Silicon Gate CMOS The MC74HCT14A may be used as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs. The HCT14A is identical in pinout to the LS14. The HCT14A
MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10161L AWLYYWW
The MC10161 is designed to decode a three bit input word to a one of eight line output. The selected output will be low while all other outputs will be high. The enable inputs, when either or both are