High Performance Silicon Gate CMOS
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- Lydia Flowers
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1 SEONDUTOR TEHNAL HighPerformance Siliconate OS The H is identical in pinout to the LS. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with LSTTL outputs. The Address nputs select one of four Data nputs from each multiplexer. Each multiplexer has an activelow Strobe control and a noninverting output. The H is similar in function to the H, which has state outputs. Output Drive apability: 0 LSTTL Loads Outputs Directly nterface to OS, NOS, and TTL Operating oltage Range: to Low nput urrent: µa High Noise mmunity haracteristic of OS Devices n ompliance with the Requirements Defined by EDE Standard No. A hip omplexity: 08 ETs or Equivalent ates ADDRESS A LO DARA WORD a WORD b 0 PN ASSNENT A 8 UNTON TALE nputs N SUX PLAST PAAE ASE 808 D SUX SO PAAE ASE 0 ORDERN NORATON HXXXN HXXXD 0 Output A Strobe Y X X H L L L L D0 L H L D H L L D H H L D D0, D, D, and D = the level of the respective data input. Plastic SO PN = PN 8 = 0/ otorola, nc. RE
2 H AXU RATNS* Symbol Parameter alue Unit ÎÎ D Supply oltage (Referenced to ) 0. to +.0 in D nput oltage (Referenced to ). to +. out D Output oltage (Referenced to ) 0. to + 0. ÎÎ in D nput urrent, per Pin ± 0 ma ÎÎ out D Output urrent, per Pin ± ma ÎÎ D Supply urrent, and Pi ± 0 ma ÎÎ ÎÎ P D Power Dissipation in Still Air Plastic DP 0 mw TstgÎÎ SO Package 00 Storage Temperature to + 0 LÎÎ T Lead Temperature, mm from ase for 0 Seconds 0 (Plastic DP or SO Package) This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this highimpedance circuit. or proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. * aximum Ratings are those values beyond which damage to the device may occur. unctional operation should be restricted to the Recommended Operating onditio. Derating Plastic DP: 0 mw/ from to SO Package: mw/ from to or high frequency or heavy load coideratio, see hapter of the otorola HighSpeed OS Data ook (DL/D). REOENDED OPERATN ONDTONS Î Symbol Parameter in ax Unit Î D Supply oltage (Referenced to ).0.0 ÎÎ in, out D nput oltage, Output oltage (Referenced to ) 0 Î TA Operating Temperature, All Package Types + tr, tf nput Rise and all Time =.0 ÎÎ (igure ) =. Î = D ELETRAL HARATERSTS (oltages Referenced to ) ÎÎ uaranteed Limit ÎÎ to Î Î Symbol Parameter Test onditio 8 Î Î Unit H inimum HighLevel nput out = 0. or 0. Î ÎÎ oltage out.0 Î 0 µa..0.. Î...Î. Î.. L aximum LowLevel nput out = 0. or 0. Î ÎÎ oltage out Î 0. Î 0 µa Î Î.. OH inimum HighLevel Output in = H or L.0 oltage out 0 µa Î. ÎÎ....Î Î. Î ÎÎ.0... in = H or L out Î.0 ma. out Î ma Î OL aximum LowLevel Output in = H or L.0 oltage out 0 µa Î. ÎÎ 0. 0.Î Î 0. Î ÎÎ in = H or L out Î.0 ma. out Î ma Î in aximum nput Leakage urrent in = or.0 ± 0. ±.0 ±.0 µa ÎÎ aximum Quiescent Supply in = or.0 urrent (per Package) out = 0 µa Î Î Î Î µa NOTE: nformation on typical parametric values can be found in hapter of the otorola HighSpeed OS Data ook (DL/D). OTOROLA DL Rev
3 H A ELETRAL HARATERSTS (L = 0 p, nput tr = tf = ) Î uaranteed Limit Î to Î SymbolÎÎ Parameter 8 Î Unit Î, ÎÎ aximum Propagation Delay, nput D to Output Y Î.0 ÎÎ 0 Î 0 Î (igures, and ). 8.0 ÎÎ 0 Î, aximum Propagation Delay, nput A to Output Y.0 ÎÎ 0 Î (igures and )..0 0 Î Î, aximum Propagation Delay, Strobe to Output Y.0 Î Î ÎÎ (igures, and ) Î. 0 Î Î Î Î.0 0 ttlh, ÎÎ aximum Output Traition Time, Any Output Î.0 tthl (igures and )..0 Î 0 Î ÎÎ aximum nput apacitance 0 Î 0 0 p in. or propagation delays with loads other than 0 p, see hapter of the otorola HighSpeed OS Data ook (DL/D).. nformation on typical parametric values can be found in hapter of the otorola HighSpeed OS Data ook (DL/D). =.0 PD Power Dissipation apacitance (Per ultiplexer)* p * Used to determine the noload dynamic power coumption: PD = PD f +. or load coideratio, see hapter of the otorola HighSpeed OS Data ook (DL/D). SWTHN WAEORS tr NPUT D 0% 0% 0% 0% 0% 0% tf NPUT A 0% ALD 0% ALD ttlh tthl igure. igure. STROE 0% 0% 0% tf 0% 0% 0% tr DEE UNDER TEST OUTPUT TEST PONT L* ttlh tthl * ncludes all probe and jig capacitance igure. igure. Test ircuit DL Rev OTOROLA
4 H PN DESRPTONS, (Pi,,,, 0,,, ) Data nputs. With the outputs enabled, the addressed Data nputs appear at the Y outputs. ONTROL, A (Pi, ) Address nputs. These inputs address the pair of Data nputs which appear at the corresponding outputs. Strobe (Pi, ) Activelow Strobe. A low level applied to these pi enables the corresponding outputs. OUTPUTS, (Pi, ) Noninverting data outputs. EXPANDED LO DARA WORD a 0 NONNERTN OUTPUTS WORD b ADDRESS A OTOROLA DL Rev
5 H OUTLNE DENSONS A 8 H S T SEATN PLANE D PL 0. (0.00) T A N SUX PLAST PAAE ASE 808 SSUE R L. DENSONN AND TOLERANN PER ANS Y., 8.. ONTROLLN DENSON: NH.. DENSON L TO ENTER O LEADS WHEN ORED PARALLEL.. DENSON DOES NOT NLUDE OLD LASH.. ROUNDED ORNERS OPTONAL. D A D H L S NHES N AX S 0.00 S LLETERS N AX S. S T SEATN PLANE 8 A D PL 0. (0.00) T S A S D SUX PLAST SO PAAE ASE 0 SSUE P 8 PL 0. (0.00) R X. DENSONN AND TOLERANN PER ANS Y., 8.. ONTROLLN DENSON: LLETER.. DENSONS A AND DO NOT NLUDE OLD PROTRUSON.. AXU OLD PROTRUSON 0. (0.00) PER SDE.. DENSON D DOES NOT NLUDE DAAR PROTRUSON. ALLOWALE DAAR PROTRUSON SHALL E 0. (0.00) TOTAL N EXESS O THE D DENSON AT AXU ATERAL ONDTON. D A D P R LLETERS N AX NHES N AX S 0.00 S otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation coequential or incidental damages. Typical parameters can and do vary in different applicatio. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any licee under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, nc. otorola, nc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: otorola Literature Distribution; APAN: Nippon otorola Ltd.; TatsumiSPDLD, Toshikatsu Otsuki, P.O. ox 0; Phoenix, Arizona Seibuutsuryuenter, Tatsumi otou, Tokyo, apan. 08 AX: RAX0@ .sps.mot.com TOUHTONE (0) 0 HON ON: otorola Semiconductors H.. Ltd.; 8 Tai Ping ndustrial Park, NTERNET: Ting ok Road, Tai Po, N.T., Hong ong. 88 DL Rev ODELNE H/D OTOROLA
High Performance Silicon Gate CMOS
SEIONDUTOR TEHNIAL DATA HighPerformance Siliconate OS The H is identical in pinout to the LS. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with
High Performance Silicon Gate CMOS
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High Performance Silicon Gate CMOS
SEIONDUTO TEHNIAL DATA High Performance Silicon Gate OS The 54/74HA and HI6A are identical in pinout to the LS and LS. The device inputs are compatible with standard OS outputs; with pullup resistors,
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC10176 contains six high-speed, master slave type D flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes
MC74HCT366A. Hex 3-State Inverting Buffer with Common Enables and LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
ex 3-State Inverting Buffer with Common Enables and STT Compatible Inputs igh Performance Silicon Gate CMOS The MC74CT366A is identical in pinout to the S366. The device inputs are compatible with standard
NL17SH02. Single 2-Input NOR Gate
N7S0 Single -Input NOR Gate The N7S0 MiniGate is an advanced high speed CMOS input NOR gate in ultra small footprint. The N7S0 input structures provide protection when voltages up to 7.0 are applied, regardless
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC06 contains six high speed, master slave type D flip flops. Clocking is common to all six flip flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place
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MC74ACT Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
8 Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins The MC74ACT323 is an 8-bit universal shift/storage register with3-state outputs. Its function is similar to the MC74ACT299
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in
LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES ORDERING INFORMATION. SN74LS37xN AWLYYWW PDIP 20 N SUFFIX CASE 738
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is
LOW POWER SCHOTTKY. ESD > 3500 Volts. GUARANTEED OPERATING RANGES ORDERING INFORMATION V CC 8 7 GND
ESD > 3500 Volts V CC 8 4 3 2 0 9 LOW POWER SCHOTTKY 2 3 4 5 6 7 GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage 4.75 5.0 5.25 V T A Operating Ambient Temperature
High Performance Silicon Gate CMOS
igh Performance Silicon Gate MOS The M7400A is identical in pinout to the S00. The device inputs are compatible with Standard MOS outputs; with pullup resistors, they are compatible with STT outputs. Output
SN74LS138MEL LOW POWER SCHOTTKY
The LSTTL/MSI SN74LS18 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel
IN74HC164А 8-Bit Serial-Input/Parallel-Output Shift Register
TECHNICAL DATA IN74HC164А 8-Bit Serial-Input/Parallel-Output Shift Register High-Performance Silicon-Gate CMOS The IN74HC164 is identical in pinout to the LS/ALS164. The device inputs are compatible with
MC74VHC14. Hex Schmitt Inverter
MC74HC4 Hex Schmitt Inverter The MC74HC4 is an advanced high speed CMOS Schmitt inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky
MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10161L AWLYYWW
The MC10161 is designed to decode a three bit input word to a one of eight line output. The selected output will be low while all other outputs will be high. The enable inputs, when either or both are
MC74HCT573A/D. Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC74HCT573A is identical in pinout to the LS573. This device may be used as a level converter
SEMICONDUCTOR TECHNICAL DATA
SEIONDUTOR TEHNIL DT The decoder is constructed so that an 8421 D code on the four inputs provides a decimal (one of ten) decoded output, while a 3 bit binary input provides a decoded octal (one of eight)
MC14518B. MARKING DIAGRAMS 16. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) ORDERING INFORMATION
The MC14518B dual BCD counter and the MC14520B dual binary counter are cotructed with MOS P channel and N channel enhancement mode devices in a single monolithic structure. Each coists of two identical,
MMBZ5221BLT1 Series. Zener Voltage Regulators. 225 mw SOT 23 Surface Mount
MMBZ5BLT Series Zener Voltage Regulators 5 mw SOT Surface Mount This series of Zener diodes is offered in the convenient, surface mount plastic SOT package. These devices are designed to provide voltage
MC Bit Magnitude Comparator
Bit Magnitude Comparator The MC0 is a high speed expandable bit comparator for comparing the magnitude of two binary words. Two outputs are provided: and. A = B can be obtained by NORing the two outputs
MMBZ5221BLT1 Series. Zener Voltage Regulators. 225 mw SOT 23 Surface Mount
MMBZ5BLT Series Preferred Device Zener Voltage Regulators 5 mw SOT Surface Mount This series of Zener diodes is offered in the convenient, surface mount plastic SOT package. These devices are designed
Is Now Part of To learn more about ON Semiconductor, please visit our website at
Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC