MC74HCT573A. Octal 3 State Noninverting Transparent Latch with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS

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1 Octal 3 State Noninverting Traparent Latch with LSTTL Compatible Inputs High Performance Silicon Gate COS The C74HCT573 is identical in pinout to the LS573. This device may be used as a level converter for interfacing TTL or NOS outputs to High Speed COS inputs. These latches appear traparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold times becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high impedance state. Thus, data may be latched even when the outputs are not enabled. The HCT573 is identical in function to the HCT373 but has the Data Inputs on the opposite side of the package from the outputs to facilitate PC board layout. Output Drive Capability: 5 LSTTL Loads TTL/NOS Compatible Input Levels Outputs Directly Interface to COS, NOS and TTL Operating Range: 4.5 to 5.5 Low Input Current: 0 μ In Compliance with the Requirements Defined by JEDEC Standard No. 7 Chip Complexity: 234 FETs or 58.5 Equivalent Gates Improved Propagation Delays 50% Lower uiescent Power These devices are available in Pb free package(s). Specificatio herein apply to both standard and Pb free devices. Please see our website at for specific Pb free orderable part numbers, or contact your local ON Semiconductor sales office or representative. PDIP N SUFFIX CSE 738 SOIC WIDE DW SUFFIX CSE 75D TSSOP DT SUFFIX CSE 948E RKING DIGRS = ssembly Location WL = Wafer Lot YY = Year WW = Work Week C74HCT573N WLYYWW HCT573 WLYYWW ORDERING INFORTION Device Package Shipping C74HCT573N PDIP 440 / ox C74HCT573DW SOIC WIDE 38 / Rail C74HCT573DWR2 SOIC WIDE 000 / Reel C74HCT573DT TSSOP 75 / Rail C74HCT573DTR2 TSSOP 2500 / Reel HCT 573 LYW Semiconductor Components Industries, LLC, 06 arch, 06 Rev. Publication Order Number: C74HCT573/D

2 DT INPUTS D0 D D2 D3 D4 D5 D6 D7 LTCH OUTPUT LOGIC DIGR FUNCTION TLE PIN = CC PIN 0 = NONINERTING OUTPUTS OUTPUT D0 PIN SSIGNENT D D2 D3 5 D4 D5 D6 D CC LTCH Inputs Output Output Latch Enable Enable D L H H H L H L L L L X No Change H X X Z X = Don t Care Z = High Impedance ÎÎ Design Criteria alue Units Internal Gate Count* 58.5 ea ÎÎ Internal Gate Propagation Delay.5 ÎÎ Internal Gate Power Dissipation 5.0 μw ÎÎ Speed Power Product *Equivalent to a two input NND gate pj 2

3 XIU RTINGS* SymbolÎÎ Î alue Unit CC ÎÎ DC Supply (Referenced to ) Î 0.5 to in ÎÎ DC Input (Referenced to ) Î 0.5 to CC out ÎÎ DC Output (Referenced to ) Î 0.5 to CC I in ÎÎ DC Input Current, per Pin Î ± m I out ÎÎ DC Output Current, per Pin Î ± 25 m I CC ÎÎ DC Supply Current, CC and Pi Î ± 50 m P D ÎÎ Power Dissipation in Still ir Plastic DIP Î 750 mw SOIC Package 500 TSSOP Package 450 T stg ÎÎ Storage Temperature 65 to + 50 C T L Lead Temperature, mm from Case for 0 Seconds Î (Plastic DIP, TSSOP or SOIC Package) Î 260 C *aximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. Derating Plastic DIP: 0 mw/ C from 65 to 25 C SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C For high frequency or heavy load coideratio, see Chapter 2 of the ON Semiconductor High Speed COS Data ook (DL29/D). RECOENDED OPERTING CONDITIONS Symbol in ax Unit CC DC Supply (Referenced to ) in, out DC Input, Output (Referenced to ) 0 CC T Operating Temperature, ll Package Types C t r, t f Input Rise and Fall Time (Figure ) DC ELECTRICL CHRCTERISTICS (s Referenced to ) Guaranteed Limit CC 55 to Symbol Test Conditio 25 C 85 C 25 C Unit IH ÎÎ inimum High Level Input out = 0. or CC ÎÎ Î Î I out μ IL ÎÎ aximum Low Level Input Î out = 0. or CC I out μ ÎÎ OH inimum High Level Output ÎÎ Î in = IH or IL 4.5 I out μ Î in = IH or IL ÎÎ I out 6.0 m ÎÎ OL aximum Low Level Output ÎÎ Î in = IH or IL 4.5 I out μ Î in = IH or IL ÎÎ I Î out 6.0 m 4.5 ÎÎ ÎÎ Iin aximum Input Leakage Current in = CC or 5.5 ± 0. ±.0 ±.0 Î μ I OZ aximum Three State Output in High Impedance State 5.5 ± 0.5 ± 5.0 ± 0 μ ÎÎ Leakage Current Î in = IL or IH ÎÎ Î out = CC or ÎÎ I CC ÎÎ aximum uiescent Supply Î in = CC or 5.5 Current (per Package) I out ÎÎ ÎÎ μ 0 μ ΔI CC ÎÎ dditional uiescent Supply in ÎÎ = 2.4, ny One Input Î Current Î in = CC or, Other Inputs Î 55 C 25 C to 25 C l out = 0 μ This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or CC ). Unused outputs must be left open. NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed COS Data ook (DL29/D). m 3

4 C ELECTRICL CHRCTERISTICS ( CC = 5.0 ± 0%, C L = 50 pf, Input t r = t f = 6.0 ) Guaranteed Limit Î 55 to ÎÎ Symbol 25 C 85 C 25 C Î Unit t Î PLH, aximum Propagation Delay, Input D to Output t PHL Î (Figures and 5) Î t PLH Î aximum Propagation Delay, Latch Enable to Î t PHL ÎÎ (Figures 2 and 5) ÎÎ Î T PLZ, ÎÎ aximum Propagation Delay, Output Enable to T Î PHZ (Figures 3 and 6) Î t Î TZL, aximum Propagation Delay, Output Enable to t TZH Î (Figures 3 and 6) Î t Î TLH, aximum Output Traition Time, any Output t THL ÎÎ (Figures and 5) ÎÎ Î C in ÎÎ aximum Input Capacitance pf Î C out ÎÎ aximum Three State Output Capacitance ÎÎ (Output in High Impedance State) ÎÎ pf NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High Speed COS Data ook (DL29/D). C PD Power Dissipation Capacitance (Per Enabled Output)* 25 C, CC = 5.0 * Used to determine the no load dynamic power coumption: P D = C PD CC 2 f + I CC CC. For load coideratio, see Chapter 2 of the ON Semiconductor High Speed COS Data ook (DL29/D). Î TIING REUIREENTS ( CC = 5.0 ± 0%, C L = 50 pf, Input t r = t f = 6.0 ) Guaranteed Limit 55 to 25 C Î 85 C 25 C Symbol Fig. in ax in ax ÎÎ in ax Unit t su inimum Setup Time, Input D to Latch Enable 4 0 Î 3 5 Î t h inimum Hold Time, Latch Enable to Input D Î Î t w inimum Pulse Width, Latch Enable 2 5 Î 9 22 Î t r, t f aximum Input Rise and Fall Times Î 500 Î pf 4

5 SWITCHING WEFORS INPUT D t r t f LTCH.3 t w t PLH 0%.3 90% t PHL t PLH t PHL t TLH t THL.3 Figure. Figure 2. OUTPUT t PZL t PZH t PLZ t PHZ 0% 90% HIGH IPEDNCE OL OH HIGH IPEDNCE INPUT D LTCH.3 Figure 3. Figure 4. t SU LID.3 t h TEST POINT EXPNDED LOGIC DIGR DEICE UNDER TEST OUTPUT C L * D0 2 D 9 0 D 3 D 8 *Includes all probe and jig capacitance Figure 5. Test Circuit D2 4 D 7 2 D3 5 D 6 3 D4 6 D 5 4 DEICE UNDER TEST TEST POINT OUTPUT kω C L * CONNECT TO CC WHEN TESTING t PLZ ND t PZL. CONNECT TO WHEN TESTING t PHZ ND t PZH. D5 7 D 4 5 D6 8 D 3 6 D7 9 D 2 7 *Includes all probe and jig capacitance Figure 6. Test Circuit LTCH OUTPUT 5

6 PCKGE DIENSIONS T SETING PLNE G E F 0 D PL N PDIP N SUFFIX PLSTIC DIP PCKGE CSE ISSUE E K C 0.25 (0.00) T L J PL 0.25 (0.00) T NOTES:. DIENSIONING ND TOLERNCING PER NSI Y4.5, CONTROLLING DIENSION: INCH. 3. DIENSION L TO CENTER OF LED WHEN FORED PRLLEL. 4. DIENSION DOES NOT INCLUDE OLD FLSH. INCHES ILLIETERS DI IN X IN X C D E SC.27 SC F G 0.00 SC 2.54 SC J K L SC 7.62 SC N SO DW SUFFIX CSE 75D 05 ISSUE F D H 0X E h X 45 NOTES:. DIENSIONS RE IN ILLIETERS. 2. INTERPRET DIENSIONS ND TOLERNCES PER SE Y4.5, DIENSIONS D ND E DO NOT INCLUDE OLD PROTRUSION. 4. XIU OLD PROTRUSION 0.5 PER SIDE. 5. DIENSION DOES NOT INCLUDE DR PROTRUSION. LLOWLE PROTRUSION SHLL E 0.3 TOTL IN EXCESS OF DIENSION T XIU TERIL CONDITION. X 0.25 T S 8X e S T SETING PLNE C L ILLIETERS DI IN X C D E e.27 SC H h L

7 PCKGE DIENSIONS 0.5 (0.006) T L 0.5 (0.006) T U 2X L/2 PIN IDENT U S S C 0.00 (0.004) T SETING PLNE X K REF 0.0 (0.004) T U S S 0 D G H TSSOP DT SUFFIX CSE 948E 02 ISSUE U J J N K K ÍÍÍÍ ÍÍÍÍ N SECTION N N F DETIL E 0.25 (0.00) DETIL E W NOTES: М. DIENSIONING ND TOLERNCING PER NSI Y4.5, 982. М 2. CONTROLLING DIENSION: ILLIETER. М 3. DIENSION DOES NOT INCLUDE OLD FLSH, PROTRUSIONS OR GTE URRS. OLD FLSH OR GTE URRS SHLL NOT EXCEED 0.5 (0.006) PER SIDE. М 4. DIENSION DOES NOT INCLUDE INTERLED FLSH OR PROTRUSION. INTERLED FLSH OR PROTRUSION SHLL NOT EXCEED 0.25 (0.00) PER SIDE. М 5. DIENSION K DOES NOT INCLUDE DR PROTRUSION. LLOWLE DR PROTRUSION SHLL E 0.08 (0.003) TOTL IN EXCESS OF THE K DIENSION T XIU TERIL CONDITION. М 6. TERINL NUERS RE SHOWN FOR REFERENCE ONLY. М 7. DIENSION ND RE TO E DETERINED T DTU PLNE W. ILLIETERS INCHES DI IN X IN X C D F G 0.65 SC SC H J J K K L 6.40 SC SC ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should uyer purchase or use SCILLC products for any such unintended or unauthorized application, uyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PULICTION ORDERING INFORTION LITERTURE FULFILLENT: Literature Distribution Center for ON Semiconductor P.O. ox 632, Phoenix, rizona US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@oemi.com N. merican Technical Support: Toll Free US/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2 9 Kamimeguro, eguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. C74HCT573/D