High Performance Silicon Gate CMOS

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1 SEIONUTOR TEHNIL T High Performance Silicon Gate OS The 74H45 is identical in pinout to the 45 metal gate OS decoder/driver. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with LSTTL outputs. The H45 provides the functio of a 4 bit storage latch, a to seven segment decoder, and a display driver. It can be used either directly or indirectly with seven segment light emitting diode (), incandescent, fluorescent, gas discharge, or liquid crystal readouts. Lamp test (LT), blanking (I), and latch enable () inputs are used to test the display, to turn off or pulse modulate the brightness of the display, and to store a code, respectively. Latch Storage of Inputs lanking Input Lamp Test Input Output rive apability: 0 LSTTL Loads Outputs irectly Interface to OS, NOS, and TTL Operating oltage Range: 2 to 6 Low Input urrent: µ High Noise Immunity haracteristic of OS evices In ompliance with the Requirements efined by JEE Standard No. 7 hip omplexity: 264 FETs or 66 Equivalent Gates LOGI IGR 6 6 PIN SSIGNENT LT I N SUFFIX PLSTI PKGE SE SUFFIX SOI PKGE SE ORERING INFORTION 74HXXXXN 74HXXXX Plastic SOI f g a b c d e INPUTS (LS) (S) IT TRNSPRENT LTH EOER N ONTROL a b c d e f g SEEN SEGENT ISPLY RIER S a f g b e c d ISPLY ONTROL INPUTS I LT PIN 6 = PIN 8 = 0/5 otorola, Inc. 5 RE 6

2 74H45 XIU RTINGS* SymbolÎ Parameter alue Unit ÎÎ Supply oltage (Referenced to ) 0.5 to ÎÎ ÎÎ in Input oltage (Referenced to ).5 to +.5 ÎÎ ÎÎ out Output oltage (Referenced to ) 0.5 to ÎÎ I in Input urrent, per Pin ± 20 m ÎÎ I out Output urrent, per Pin ± 25 m ÎÎ I Supply urrent, and Pi ± 70 m ÎÎ P Power issipation in Still ir Plastic IP 750 mw Î TstgÎÎ SOI Package 500 Storage Temperature ÎÎ 65 to + 50 LÎÎ T Lead Temperature, mm from ase for 0 Seconds (Plastic IP or SOI Package) 260 This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. * aximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating onditio. erating Plastic IP: 0 mw/ from 65 to 25 SOI Package: 7 mw/ from 65 to 25 For high frequency or heavy load coideratio, see hapter 2 of the otorola High Speed OS ata ook (L2/). REOENE OPERTING ONITIONS Symbol Parameter in ax Unit Supply oltage (Referenced to ) 6.0 Î in, out Input oltage, Output oltage (Referenced to ) 0 T Operating Temperature, ll Package Types tr, tf Input Rise and Fall Time = Î (Figure 3) = = ETRIL HRTERISTIS (oltages Referenced to ) Guaranteed Limit Î 55 to Symbol Î Parameter Î Test onditio Î Unit IH Î inimum High Level Input Î out = 0. or 0. oltage Iout ÎÎ 20 µ IL aximum Low Level Input Î out = 0. or 0. oltage Iout ÎÎ ÎÎ ÎÎ 20 µ Î.2.2 OH inimum High Level Output in = IH or IL Î Î oltage Iout 20 µ ÎÎ ÎÎ in = IH or IL Iout 6.0 m Iout ÎÎ m Î OL aximum Low Level Output in = IH or IL oltage Iout 20 µ ÎÎ ÎÎ in = IH or IL Iout 4.0 m Iout ÎÎ m Î ÎÎ ÎÎ Iin aximum Input Leakage urrent in = or 6.0 ± 0. ±.0 ±.0 µ Î I aximum Quiescent Supply in = or 6.0 urrent (per Package) Î Iout = 0 µ ÎÎ µ NOTE: Information on typical parametric values can be found in hapter 2 of the otorola High Speed OS ata ook (L2/). OTOROL 2 High Speed OS Logic ata

3 74H45 ETRIL HRTERISTIS (L = 50 pf, Input tr = tf = 6 ) Î Guaranteed Limit Î 55 to SymbolÎ Parameter Î Unit tplh, Î aximum Propagation elay, Input,,, or to Output ÎÎ Î ÎÎ (Figures and 6) tplh, aximum Propagation elay, Latch Enable to Output Î ÎÎ (Figures 2 and 6) Î 2 53 tplh, aximum Propagation elay, lanking Input to Output ÎÎ Î (Figures 3 and 6) ÎÎ tplh, Î aximum Propagation elay, Lamp Test to Output ÎÎ (Figures 4 and 6) Î ttlh, aximum Output Traition Time, ny Output Î ÎÎ tthl (Figures 3 and 6) Î aximum Input apacitance pf in NOTES:. For propagation delays with loads other than 50 pf, see hapter 2 of the otorola High Speed OS ata ook (L2/). 2. Information on typical parametric values can be found in hapter 2 of the otorola High Speed OS ata ook (L2/). 25, = 5.0 P Power issipation apacitance (Per Package)* 70 pf * Used to determine the no load dynamic power coumption: P = P 2 f + I. For load coideratio, see hapter 2 of the otorola High Speed OS ata ook (L2/). TIING REQUIREENTS (Input tr = tf = 6 ) Guaranteed Limit Î 55 to ÎÎ SymbolÎ Parameter Î Unit tsu Î inimum Setup Time, Input,,, or to Latch Enable ÎÎ (Figure 5) th inimum Hold Time, Latch Enable to Input,,, or Î 0 (Figure 5) Î tw inimum Pulse Width, Latch Enable (Figure 2) Î ÎÎ tr, tf Î aximum Input Rise and Fall Times (Figure 3) NOTE: Information on typical parametric values can be found in hapter 2 of the otorola High Speed OS ata ook (L2/). High Speed OS Logic ata 3 OTOROL

4 74H45 SWITHING WEFORS INPUT,,, OR tplh LI LI INPUT tw tplh NY OPUTPUT NY OPUTPUT Figure. Figure 2. INPUT I NY OPUTPUT 0% 0% tf 0% 0% tthl tr tplh ttlh INPUT LT NY OPUTPUT 0% 0% ttlh tplh tf 0% 0% tr tthl Figure 3. Figure 4. TEST POINT INPUT,,, OR INPUT LI tsu th EIE UNER TEST L* * Includes all probe and jig capacitance Figure 5. Figure 6. Test ircuit OTOROL 4 High Speed OS Logic ata

5 74H45 Inputs FUNTION T Outputs I LT a b c d e f g isplay X X L X X X X H H H H H H H 8 X L H X X X X L L L L L L L lank L H H L L L L H H H H H H L 0 L H H L L L H L H H L L L L L H H L L H L H H L H H L H 2 L H H L L H H H H H H L L H 3 L H H L H L L L H H L L H H 4 L H H L H L H H L H H L H H 5 L H H L H H L L L H H H H H 6 L H H L H H H H H H L L L L 7 L H H H L L L H H H H H H H 8 L H H H L L H H H H L L H H L H H H L H L L L L L L L L lank L H H H L H H L L L L L L L lank L H H H H L L L L L L L L L lank L H H H H L H L L L L L L L lank L H H H H H L L L L L L L L lank L H H H H H H L L L L L L L lank H H H X X X X * * * = epends upon the code previously applied while was at a low level. PIN ESRIPTIONS INPUTS,,, (Pi 7,, 2, 6) inputs. (pin 7) is the least significant bit and (pin 6) is the most significant bit. Hexadecimal code F at these inputs causes the outputs to assume a low level, offering an alternate method of blanking the display. S a, b, c, d, e, f, g (Pi 3, 2,, 0,, 5, 4) ecoded, buffered seven segment display driver outputs. These outputs, unlike the 45, have OS drivers, which produce typical OS output voltage levels. These outputs are connected to various displays as shown in Figure 7. ONTROL INPUTS I (Pin 4) ctive low display blanking input. low level on this input will cause all outputs to be held low, thereby blanking the display. LT is the only input that overrides the I input. LT (Pin 3) ctive low lamp test. low level on this input causes all outputs to assume a high level. This input allows the user to test all segments of a display with a single control input. This input is independent of all other inputs. (Pin 5) Latch enable input. This input controls the 4 bit traparent latch. high level on this input latches the code present at the,, and inputs, a low level allows the code to be tramitted through the latch to the decoder. High Speed OS Logic ata 5 OTOROL

6 74H45 HRTERISTI URES ( = 5 ) I O, SOURE URRENT (m) SOURE URRENT TYPIL T = 25 T = 25 T = 85 T = 25 EXPETE INIU* I O, SINK URRENT (m) TYPIL T = 25 SINK URRENT T = 25 T = 85 T = 25 EXPETE INIU* O, OLTGE (OLTS) O, OLTGE (OLTS) * The expected minimum curves are not guarantees, but are design aids. OTOROL 6 High Speed OS Logic ata

7 74H45 EXPNE LOGI IGR 5 I LI a 7 T 2 b c T 0 d e 2 T 5 f 4 g 6 T High Speed OS Logic ata 7 OTOROL

8 74H45 Liquid rystal isplay (L) Readout Incandescent Readout TYPIL LUES H45 RS = Ω RT = 00 kω T = 0.0 µf RS RT T H86 ONE OF SEEN SEGENTS PPROPRITE OLTGE HU04 HU04 Readout OON KPLNE H45 OON THOE H45 Gas ischarge Readout PPROPRITE OLTGE H45 OON NOE H45 H04 Figure 7. onnectio to arious isplay Readouts OTOROL 8 High Speed OS Logic ata

9 74H45 OUTLINE IENSIONS 6 8 H G F S K T SETING PLNE 6 PL 0.25 (0.00) T N SUFFIX PLSTI PKGE SE ISSUE R J L NOTES:. IENSIONING N TORNING PER NSI Y, ONTROLLING IENSION: INH. 3. IENSION L TO ENTER OF S WHEN FORE PRLL. 4. IENSION OES NOT INLUE OL FLSH. 5. ROUNE ORNERS OPTIONL. I F G H J K L S INHES IN X S S ILLIETERS IN X S.27 S T SETING PLNE 6 8 G 6 PL K 0.25 (0.00) T S S SUFFIX PLSTI SOI PKGE SE ISSUE J P 8 PL 0.25 (0.00) R X 45 J F NOTES:. IENSIONING N TORNING PER NSI Y, ONTROLLING IENSION: ILLIETER. 3. IENSIONS N O NOT INLUE OL PROTRUSION. 4. XIU OL PROTRUSION 0.5 (0.006) PER SIE. 5. IENSION OES NOT INLUE R PROTRUSION. LLOW R PROTRUSION SHLL E 0.27 (0.005) TOTL IN EXESS OF THE IENSION T XIU TERIL ONITION. I F G J K P R ILLIETERS IN X INHES IN X S S otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation coequential or incidental damages. Typical parameters can and do vary in different applicatio. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any licee under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/ffirmative ction Employer. How to reach us: US/EUROPE: otorola Literature istribution; JPN: Nippon otorola Ltd.; Tatsumi SP JL, Toshikatsu Otsuki, P.O. ox 202; Phoenix, rizona F Seibu utsuryu enter, Tatsumi Koto Ku, Tokyo 35, Japan FX: RFX0@ .sps.mot.com TOUHTONE (602) HONG KONG: otorola Semiconductors H.K. Ltd.; 8 Tai Ping Industrial Park, INTERNET: NET.com 5 Ting Kok Road, Tai Po, N.T., Hong Kong High Speed OS Logic ata OELINE 74H45/ OTOROL

High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS SONUTOR TNL T igh Performance Silicon ate OS The 7078 is similar to the 078 metal gate OS device. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with