INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Size: px

Start display at page:

Download "INTEGRATED CIRCUITS. For a complete data sheet, please also download:"

Alexandrina Hoover
5 years ago
Views:

1 INTEGRATED CIRCUITS DATA SEET F a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Infmation The IC06 74C/CT/CU/CMOS ogic Package Outlines BCD to 7-segment latch/decoder/driver f File under Integrated Circuits, IC06 December 1990

2 BCD to 7-segment latch/decoder/driver f FEATURES atch stage of BCD inputs Blanking inputs Output capability: non-standard I CC categy: MSI GENERA DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with 4543 of the 4000B series. They are specified in compliance with JEDEC standard no. 7A. The are BCD to 7-segment latch/decoder/drivers f liquid crystal displays. They have four address inputs (D 0 to D 3 ), an active IG latch disable input (D), an active IG ing input (BI), an active IG phase input (P) and seven buffered segment outputs (Q a to Q g ). The 4543 provides the function of a 4-bit stage latch and an BCD to 7-segment decoder driver. The 4543 can invert the logic levels of the output combination. The phase (P), ing (BI) and latch disable (D) inputs are used to reverse the function table phase, the display and ste a BCD code, respectively. F liquid crystal displays a square-wave is applied to P and the electrical common back-plane of the display. The outputs of the 4543 are directly connected to the segments of the liquid crystal. QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f =6ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P propagation delay C = 15 pf; V CC =5V D n to Q n ns D to Q n ns BI to Q n ns C I input capacitance pf C PD power dissipation capacitance per package notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply in V 2. F C the condition is V I = GND to V CC F CT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Infmation. December

3 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1 D latch disable input (active IG) 5, 3, 2, 4 D 0 to D 3 address (data) inputs 6 P phase input (active IG) 7 BI ing input (active IG) 8 GND ground (0 V) 9, 10, 11, 12, 13, 15, 14 Q a to Q g segment outputs 16 V CC positive supply Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December

4 December Fig.4 Functional diagram. Fig.5 Segment designation. APPICATIONS Driving CD displays Driving fluescent displays Driving incandescent displays Driving gas discharge displays FUNCTION TABE Notes 1. F liquid crystal displays, apply a square-wave to P. 2. Depends upon the BCD-code previously applied when D = IG. = IG level = OW level X = don t care INPUTS OUTPUTS DISPAY D BI P (1) D 3 D 2 D 1 D 0 Q a Q b Q c Q d Q e Q f Q g X X X X X X X X X (1) (1) as above as above inverse of above as above

5 Fig.6 ogic diagram. Fig.7 Display. RATINGS imiting values in accdance with the Absolute Maximum System (IEC 134). F RATINGS see 74C/CT/CU/CMOS ogic Family Specifications, standard outputs. December

6 DC CARACTERISTICS FOR 74C Output capability: non-standard I CC categy: MSI Voltages are referenced to GND (ground = 0 V) T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74C to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) V I OTER V I IG level input V 2.0 V I OW level input V 2.0 V O IG level output V 2.0 V I V I I O =20µA I O =20µA I O =20µA V O IG level output V V I V I I O = 1.0 ma I O = 1.3 ma V O OW level output V 2.0 V I V I I O =20µA I O =20µA I O =20µA V O OW level output V V I V I I O = 1.0 ma I O = 1.3 ma ±I I input leakage current µa V CC GND I CC quiescent supply current µa V CC GND I O =0 December

7 AC CARACTERISTICS FOR 74C GND = 0 V; t r = t f = 6 ns; C =50pF SYMBO t P / t P t P / t P t P / t P PARAMETER propagation delay 91 D n to Q n propagation delay 102 D to Q n propagation delay 66 BI to Q n t P / t P propagation delay P to Q n t T / t T output transition time t W t su t h D pulse width IG OW set-up time D n to D hold time D n to D T amb ( C) 74C to to +125 min. typ. max. min. max. min. max UNIT V CC (V) TEST CONDITIONS Fig.12 Fig.13 Fig.14 OTER Figs 12, 13 and 14 Fig.13 Fig.15 Fig.15 December

8 DC CARACTERISTICS FOR 74CT Output capability: non-standard I CC categy: MSI Voltages are referenced to GND (ground = 0 V) T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74CT to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) V I OTER V I V I V O V O V O V O IG level input OW level input IG level output IG level output OW level output OW level output ±I I input leakage current I CC I CC quiescent supply current additional quiescent supply current per input pin f unit load coefficient is 1 (note 1) V to V to V V I V I V V I V I 0 V V I V I V V I V I µa 5.5 V CC GND µa 5.5 V CC GND µa to 5.5 V CC 2.1V I O =20µA I O = 1.0 ma I O =20µA I O = 1.0 ma I O =0 other inputs at V CC GND; I O =0 December

9 Note to CT types The value of additional quiescent supply current ( I CC ) f a unit load of 1 is given here. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D 0, D 1, D 2 D 3 BI D P UNIT OAD COEFFICIENT AC CARACTERISTICS FOR 74CT GND = 0 V; t r = t f = 6 ns; C =50pF T amb ( C) TEST CONDITIONS ns Fig ns Fig ns Fig ns 74CT SYMBO PARAMETER UNIT V OTER to to +125 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay D n to Q n t P / t P propagation delay D to Q n t P / t P propagation delay BI to Q n t P / t P propagation delay P to Q n t T / t T output transition time ns Figs 12, 13 and 14 t W t su t h D pulse width IG OW set-up time D n to D hold time D n to D ns Fig ns Fig ns Fig.15 December

10 APPICATION DIAGRAMS Fig.8 Connection to liquid crystal (CD) display readout. Fig.9 Connection to incandescent display readout. Fig.10 Connection to gas discharge display readout. Fig.11 Connection to fluescent display readout. December

11 AC WAVEFORMS (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.12 Wavefms showing the address input (D n ) to output (Q n ) propagation delays and the output transition times. Fig.13 Wavefms showing the latch disable input (D) to output (Q n ) propagation delays and the output transition times. The shaded areas indicate when the input is permitted to change f predictable output perfmance. (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.15 Wavefms showing the address (D n ) to latch disable (D) input set-up and hold times. Fig.14 Wavefms showing the ing (BI) to output (Q n ) propagation delays and the output transition times. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic