Quad 2-input NAND gate

Transcription

1 uad -input NAN gate ALS00A TYPE PROPAGATION ELAY SUPPLY CURRENT (TOTAL) ALS00A.0ns.0mA PIN CONFIGURATION A B V CC B ORERING INFORMATION Y A A Y ORER COE COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C RAWING NUMBER B Y GN 0 B A Y -pin plastic IP ALS00AN SOT- SC0000 -pin plastic SO ALS00A SOT0- -pin plastic SSOP Type II ALS00AB SOT- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE NOTE: PINS ALS (U.L.) LOA VALUE na, nb ata inputs.0/.0 0µA/0.mA ny ata output 0/0 0.mA/mA One (.0) ALS unit load is defined as: 0µA in the High state and 0.mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL 0 & A B A B A B A B Y Y Y Y 0 V CC = Pin GN = Pin SC0000 SF0000 LOGIC IAGRAM FUNCTION TABLE A B Y INPUTS OUTPUT na nb ny V CC = Pin GN = Pin A B A B A B 0 Y Y Y SC0000 H H L L X H X L H H = High voltage level L = Low voltage level X = on t care Feb

2 uad -input NOR gate ALS0 TYPE PROPAGATION ELAY SUPPLY CURRENT (TOTAL) ALS0.0ns.0mA PIN CONFIGURATION Y A V CC Y ORERING INFORMATION B Y B A ORER COE COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C RAWING NUMBER A B GN 0 Y B A -pin plastic IP ALS0N SOT- SC0000 -pin plastic SO ALS0 SOT0- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE NOTE: PINS ALS (U.L.) LOA VALUE na, nb ata inputs.0/.0 0µA/0.mA ny ata output 0/0 0.mA/mA One (.0) ALS unit load is defined as: 0µA in the High state and 0.mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL A B A B A B A B Y Y Y Y 0 0 V CC = Pin GN = Pin SC0000 SF0000 LOGIC IAGRAM FUNCTION TABLE A B Y INPUTS OUTPUT na nb ny V CC = Pin GN = Pin A B A B A B 0 Y Y Y SC0000 H H L L X H X L H H = High voltage level L = Low voltage level X = on t care Feb

3 ata selector/multiplexer ALS/ALS ALS uad -input data selector/multiplexer, non-inverting ALS uad -input data selector/multiplexer, inverting The ALS is a quad -input multiplexer which selects bits of data from one of two sources under the control of a common select input (S). The enable input (E) is active when Low. When E is High, all of the outputs (Yn) are forced Low regardless of all other input conditions. Moving data from two registers to a common output bus is a typical use of the ALS. The state of the select input determines the particular register from which data comes. The device is the logic implementation of -pole, -position switch where the position of the switch is determined by the logic levels supplied to the select input. The ALS is similar but has inverting outputs (Yn). TYPE PROPAGATION ELAY SUPPLY CURRENT (TOTAL) ALS.0ns ma ALS.0ns ma ORERING INFORMATION ORER COE COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C RAWING NUMBER -pin plastic IP ALSN, ALSN SOT- -pin plastic SO ALS, ALS SOT0- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE NOTE: PINS ALS (U.L.) LOA VALUE Ina, Inb, Inc, Ind ata inputs.0/.0 0µA/0.mA S Select input.0/.0 0µA/0.mA E Enable input.0/.0 0µA/0.mA Ya Yd, Ya Yd ata outputs 0/0 0.mA/mA One (.0) ALS unit load is defined as: 0µA in the High state and 0.mA in the Low state. PIN CONFIGURATION ALS PIN CONFIGURATION ALS S V CC S V CC I0a E I0a E Ia I0d Ia I0d Ya Id Ya Id I0b Yd I0b Yd Ib I0c Ib I0c Yb 0 Ic Yb 0 Ic GN Yc GN Yc SC000 SC000 LOGIC SYMBOL ALS LOGIC SYMBOL ALS 0 0 I0a Ia I0b Ib I0c Ic I0d Id I0a Ia I0b Ib I0c Ic I0d Id S S E E Ya Yb Yc Yd Ya Yb Yc Yd V CC = Pin GN = Pin SC000 V CC = Pin GN = Pin SC000 Feb 0 00

4 ata selector/multiplexer ALS/ALS IEC/IEEE SYMBOL ALS IEC/IEEE SYMBOL ALS G EN G EN MUX MUX 0 0 SC000 SC000 LOGIC IAGRAM ALS E I0a Ia I0b Ib I0c Ic I0d I0d S 0 LOGIC IAGRAM ALS E I0a Ia I0b Ib I0c Ic I0d I0d S 0 Ya Yb Yc Yd Ya Yb Yc Yd V CC = Pin GN = Pin SC000 V CC = Pin GN = Pin SC000 FUNCTION TABLE ALS INPUTS OUTPUTS E S I0n In Yn H X X X L L L L X L L L H X H L H X L L L H X H H H = High voltage level L = Low voltage level X = on t care FUNCTION TABLE ALS INPUTS OUTPUTS E S I0n In Yn H X X X H L L L X H L L H X L L H X L H L H X H L H = High voltage level L = Low voltage level X = on t care Feb 0

5 -input multiplexer ALS FEATURES -to- multiplexing On chip decoding Multi-function capability Complementary outputs See ALS for -State version PIN CONFIGURATION I I I I0 Y V CC I I I I The ALS is a logic implementation of a single -position switch with the switch position controlled by the state of three select (S0, S, S) inputs. True (Y) and complementary (Y) outputs are both provided. The enable (E) is active-low. When E is High, Y output is Low and the Y output is High regardless of all other inputs. TYPE PROPAGATION ELAY SUPPLY CURRENT (TOTAL) ALS.0ns.0mA Y E GN ORERING INFORMATION 0 ORER COE S0 S S COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C SF00 RAWING NUMBER -pin plastic IP ALSN SOT- -pin plastic SO ALS SOT0- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE NOTE: PINS ALS (U.L.) LOA VALUE I0 I ata inputs.0/.0 0µA/0.mA S0 S Select inputs.0/.0 0µA/0.mA E Enable input (active-low).0/.0 0µA/0.mA Y, Y ata outputs 0/0.mA/mA One (.0) ALS unit load is defined as: 0µA in the High state and 0.mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL I0 I I I I I I I 0 EN 0 G 0 MUX 0 S0 S S E Y Y V CC = Pin GN = Pin SF00 SF00 Feb

6 -input multiplexer ALS LOGIC IAGRAM S I0 I I I I I I I S 0 S0 E V CC = Pin GN = Pin Y Y SF00 FUNCTION TABLE INPUTS OUTPUTS S S S0 E Y Y X X X H L H L L L L I0 I0 L L H L I I L H L L I I L H H L I I H L L L I I H L H L I I H H L L I I H H H L I I H = High voltage level L = Low voltage level X = on t care Feb 0

7 ual -input multiplexer ALS FEATURES Non inverting outputs Common select outputs Separate enable for each section See ALS for State version PIN CONFIGURATION Ea S Ia V CC Eb S0 Ia Ib The ALS has two identical input multiplexer with State outputs which selects two bits of data from four sources by using common select inputs (S0, S). The two input multiplexer circuits have individual active Low enables (Ea, Eb) which can be used to strobe the outputs independently. Outputs (Ya, Yb) are forced Low when the corresponding enable is high. Ia I0a Ya GN 0 Ib Ib I0b Yb SF00 The ALS is the logic implementation of a pole, position switch where the position of the switch is determined by the logic levels supplied to the common select inputs. TYPE PROPAGATION ELAY SUPPLY CURRENT (TOTAL) ALS.0ns.mA ORERING INFORMATION ORER COE COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C RAWING NUMBER -pin plastic IP ALSN SOT- -pin plastic SO ALS SOT0- -pin plastic SSOP Type II ALSB SOT- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE PINS ALS (U.L.) LOA VALUE Ioa Ia Port A data inputs.0/.0 0µA/0.mA Iob Ib Port B data inputs.0/.0 0µA/0.mA S0, S Common select inputs.0/.0 0µA/0.mA Ea Port A enable input.0/.0 0µA/0.mA Eb Port B enable input.0/.0 0µA/0.mA Ya, Yb ata outputs 0/0.mA/mA NOTE: One (.0) ALS unit load is defined as: 0µA in the High state and 0.mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL 0 0 G 0 I0a S0 S Ea Eb Ia Ia Ia I0b Ib Ib Ib EN 0 MUX Ya Yb 0 V CC = Pin GN = Pin SF00 SF00 Feb 0 00

8 ual -input multiplexer ALS LOGIC IAGRAM Ea I0a Ia Ia Ia S S I0b I0b Ib Ib Eb 0 V CC = Pin GN = Pin Ya Yb SF00A FUNCTION TABLE INPUTS OUTPUT S0 S I0n In In In En Yn L L L X X X L L L L H X X X L H H L X L X X L L H L X H X X L H L H X X L X L L L H X X H X L H H H X X X L L L H H X X X H L H H = High voltage level L = Low voltage level X = on t care Feb 0

9 -of- decoder/demultiplexer ALS FEATURES emultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding The ALS decoder accepts three binary weighted inputs (A0, A, A) and when enabled, provides eight mutually exclusive, active-low outputs (0 ). The device features three Enable inputs; two active-low (E0, E) and one active-high (E). Every output will be High unless E0 and E are Low and E is High. This multiple enable function allows easy parallel expansion of the device to -of- ( lines to lines) decoder with just four ALSs and one inverter. The device can be used as an eight output demultiplexer by using one of the active-low Enable inputs as the data input and the remaining Enable inputs as strobes. Enable inputs not used must be permanently tied to their appropriate active-high or active-low state. TYPE PROPAGATION ELAY SUPPLY CURRENT (TOTAL) ALS.0ns.0mA PIN CONFIGURATION A0 A A E0 E E GN ORERING INFORMATION 0 V CC 0 ORER COE COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C SF00 RAWING NUMBER -pin plastic IP ALSN SOT- -pin plastic SO ALS SOT0- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE NOTE: PINS ALS (U.L.) LOA VALUE A0 A Address inputs.0/.0 0µA/0.mA E0, E Enable inputs (active-low).0/.0 0µA/0.mA E Enable input (active-high).0/.0 0µA/0.mA 0 ata outputs (active-low) 0/.0mA/0mA One (.0) ALS unit load is defined as: 0µA in the High state and 0.mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL E0 E A0 A A X 0 0 G 0 E 0 & 0 0 V CC = Pin GN = Pin SF00 SC000 Jul 0 0

10 -of- decoder/demultiplexer ALS LOGIC IAGRAM A A A0 E0 E E V CC = Pin GN = Pin 0 0 SF00 FUNCTION TABLE INPUTS OUTPUTS E0 E E A0 A A 0 H X X X X X H H H H H H H H X H X X X X H H H H H H H H X X L X X X H H H H H H H H L L H L L L L H H H H H H H L L H H L L H L H H H H H H L L H L H L H H L H H H H H L L H H H L H H H L H H H H L L H L L H H H H H L H H H L L H H L H H H H H H L H H L L H L H H H H H H H H L H L L H H H H H H H H H H H L H = High voltage level L = Low voltage level X = on t care Jul 0

11 ual -of- decoder/demultiplexer ALS FEATURES emultiplexing capability Two independent -of- decoders Multi-function capability PIN CONFIGURATION Ea A0a Aa V CC Eb A0b The ALS is a dual -of- decoder/demultiplexer. This device has two independent decoders, each accepting two binary weighted inputs (A 0n, A n ) and providing four mutually exclusive active-low outputs (0n n). Each decoder has an active-low enable (E). When E is High, every output is forced High. The enable can be used as the data input for a -of- demultiplexer application. 0a a a a GN 0 Ab 0b b b b SF00 TYPE PROPAGATION ELAY SUPPLY CURRENT (TOTAL) ALS.0ns ma ORERING INFORMATION ORER COE COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C RAWING NUMBER -pin plastic IP ALSN SOT- -pin plastic SO ALS SOT0- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE NOTE: PINS ALS (U.L.) LOA VALUE A0n, An Address inputs.0/.0 0µA/0.mA Ea, Eb Enable inputs (active-low).0/.0 0µA/0.mA 0n, n ata outputs 0/0 0.mA/mA One (.0) ALS unit load is defined as: 0µA in the High state and 0.mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL Ea A0a Aa ECOER a Eb A0b Ab ECOER b 0 EMUX G 0 0 0a a a a 0b b b b 0 0 V CC = Pin GN = Pin SF000 SF00 Feb 0 00

12 ual -of- decoder/demultiplexer ALS LOGIC IAGRAM Ea A0a Aa Eb A0b Ab FUNCTION TABLE INPUTS OUTPUTS E A0 A 0 H X X H H H H L L L L H H H L H L H L H H L L H H H L H L H H H H H L H = High voltage level L = Low voltage level X = on t care 0a a a a 0 0b b b b V CC = Pin GN = Pin SF00 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V CC Supply voltage 0. to +.0 V V IN Input voltage 0. to +.0 V I IN Input current 0 to + ma V OUT Voltage applied to output in High output state 0. to V CC V I OUT Current applied to output in Low output state ma T amb Operating free-air temperature range 0 to +0 C T stg Storage temperature range to +0 C RECOMMENE OPERATING CONITIONS SYMBOL PARAMETER LIMITS MIN NOM MAX V CC Supply voltage..0. V V IH High-level input voltage.0 V V IL Low-level input voltage 0. V I Ik Input clamp current ma I OH High-level output current 0. ma I OL Low-level output current ma T amb Operating free-air temperature range 0 +0 C UNIT Feb 0

13 ecoder/demultiplexer F FEATURES -line demultiplexing capability Mutually exclusive outputs -input enable gate for strobing or expansion The F decoder accepts four active High binary address inputs and provides mutually exclusive active Low outputs. The -input Enable (E0, E) gate can be used to strobe the decoder to eliminate the normal decoding glitches on the outputs, or it can be used for expansion of the decoder. The enable gate has two AN ed inputs which must be Low to enable the outputs. The F can be used as -of- demultiplexer by using one of the Enable inputs as the multiplexed data input. When the other Enable is Low, the addressed output will follow the state of the applied data. ORERING INFORMATION COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C PKG WG # -pin plastic Slim NFN SOT- IP (00mil) -pin plastic SOL NF SOT- PIN CONFIGURATION 0 V CC A0 A A 0 A E0 E TYPE PROPAGATION ELAY SUPPLY CURRENT (TOTAL) 0 F. ns ma 0 GN SF00 INPUT AN OUTPUT LOAING AN FAN-OUT TABLE PINS F (U.L.) LOA VALUE A0 A ata inputs.0/.0 0µA/0.mA E0, E Enable inputs.0/.0 0µA/0.mA 0 ata outputs 0/.0mA/0mA NOTE: One (.0) FAST unit load is defined as: 0µA in the High state and 0.mA in the Low state. LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 0 A0 A A A X G 0 0 V CC =Pin GN=Pin E E0 SF000 SF00 0 Jan 0

14 ecoder/demultiplexer F LOGIC IAGRAM E0 E A0 A A A 0 0 V CC = Pin GN = Pin SF00 FUNCTION TABLE INPUTS OUTPUTS OUTPUTS E0 E A0 A A A 0 0 L H X X X X H H H H H H H H H H H H H H H H H L X X X X H H H H H H H H H H H H H H H H H H X X X X H H H H H H H H H H H H H H H H L L L L L L L H H H H H H H H H H H H H H H L L H L L L H L H H H H H H H H H H H H H H L L L H L L H H L H H H H H H H H H H H H H L L H H L L H H H L H H H H H H H H H H H H L L L L H L H H H H L H H H H H H H H H H H L L H L H L H H H H H L H H H H H H H H H H L L L H H L H H H H H H L H H H H H H H H H L L H H H L H H H H H H H L H H H H H H H H L L L L L H H H H H H H H H L H H H H H H H L L H L L H H H H H H H H H H L H H H H H H L L L H L H H H H H H H H H H H L H H H H H L L H H L H H H H H H H H H H H H L H H H H L L L L H H H H H H H H H H H H H H L H H H L L H L H H H H H H H H H H H H H H H L H H L L L H H H H H H H H H H H H H H H H H L H L L H H H H H H H H H H H H H H H H H H H L H = High voltage level L = Low voltage level X = on t care 0 Jan 0

15 -input priority encoder F FEATURES Code conversions Multi-channel /A converter ecimal-to-bc converter Cascading for priority encoding of N bits Input enable capability Priority encoding-automatic selection of highest priority input line Output enable-active Low when all inputs are High Group signal output-active when any input is Low PIN CONFIGURATION I I I I EI A A GN 0 V CC EO GS I I I I0 A0 The F -input priority encoder accepts data from eight active-low inputs and provides a binary representation on the three active-low outputs. A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line I having the highest priority. A High on the Enable Input (EI) will force all outputs to the inactive (High) state and allow new data to settle without producing erroneous information at the outputs. A Group Signal (GS) output and an Enable Output (EO) are provided with the three data outputs. The GS is active-low when any input is Low: this indicates when any input is active. The EO is active-low when all inputs are High. Using the Enable Output along with the Enable Input allows priority encoding of N input signals. Both EO and GS are active-high when the Enable Input is High. TYPE PROPAGATION ELAY SF00 SUPPLY CURRENT (TOTAL) F.0ns ma ORERING INFORMATION COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C PKG WG # -pin plastic IP NFN SOT- -pin plastic SO NF SOT0- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE PINS F (U.L.) LOA VALUE I I Priority inputs (active Low).0/.0 0µA/.mA I0 Priority input (active Low).0/.0 0µA/0.mA EI Enable input (active Low).0/.0 0µA/.mA EO Enable output (active Low) 0/.0mA/0mA GS Group select output (active Low) 0/.0mA/0mA A0 A Address outputs (active Low) 0/.0mA/0mA NOTE: One (.0) FAST unit load is defined as: 0µA in the High state and 0.mA in the Low state. March, 0 0

16 -input priority encoder F LOGIC SYMBOL IEC/IEEE SYMBOL EI V CC = Pin GN = Pin 0 I0 I I I I I I I A0 A A EO GS SF00 0 0/Z0 /Z /Z /Z /Z /Z /Z /Z EN = α/v HPRI/BIN 0 0 α α α α SF00 LOGIC IAGRAM EI I I I I I I I I0 0 V CC = Pin GN = Pin A A A0 GS EO SF00 March, 0

17 -input priority encoder F FUNCTION TABLE INPUTS OUTPUTS EI I0 I I I I I I I GS A0 A A EO H X X X X X X X X H H H H H L H H H H H H H H H H H H L L X X X X X X X L L L L L H L X X X X X X L H L H L L H L X X X X X L H H L L H L H L X X X X L H H H L H H L H L X X X L H H H H L L L H H L X X L H H H H H L H L H H L X L H H H H H H L L H H H L L H H H H H H H L H H H H H = High voltage level L = Low voltage level X = on t care APPLICATION LSB ENABLE MSB I0 I I I I I I I I0 I I I I I I I EI EO GS A0 A A EI EO GS A0 A A A0 A A A FLAG -Input Priority Encoder SF00 March, 0

18 -bit magnitude comparator F FEATURES High-impedance NPN base inputs for reduced loading (0µA in High and Low states) Magnitude comparison of any binary words Serial or parallel expansion without extra gating The F is a -bit magnitude comparator that can be expanded to almost any length. It compares two -bit binary, BC, or other monotonic codes and presents the three possible magnitude results at the outputs. The -bit inputs are weighted (A0 A) and (B0 B) where A and B are the most significant bits. The operation of the F is described in the Function Table, showing all possible logic conditions. The upper part of the table describes the normal operation under all conditions that will occur in a single device or in a series expansion scheme. In the upper part of the table the three outputs are mutually exclusive. In the lower part of the table, the outputs reflect the feed-forward conditions that exist in the parallel expansion scheme. The expansion inputs I A>B, and I A=B and I A<B are the least significant bit positions. When used for series expansion, the A>B, A=B and A<B outputs of the lease significant word are connected to the corresponding I A>B, I A=B and I A<B inputs of the next higher stage. Stages can be added in this manner to any length, but a propagation delay penalty of about ns is added with each additional stage. For proper operation, the expansion inputs of the least significant word should be tied as follows: I A>B = Low, I A=B = High, and I A<B = Low. PIN CONFIGURATION TYPE B I A<B I A=B I A>B A>B A=B A<B GN PROPAGATION ELAY 0 SF000 V CC A B A A B A0 B0 SUPPLY CURRENT (TOTAL) F.0ns 0mA ORERING INFORMATION COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C PKG WG # -pin plastic IP NFN SOT- -pin plastic SO NF SOT- INPUT AN OUTPUT LOAING AN FAN OUT TABLE PINS F (U.L.) LOA VALUE A0 A Comparing inputs.0/0.0 0µA/0µA B0 B Comparing inputs.0/0.0 0µA/0µA I A<B, I A=B, I A>B Expansion inputs (active High).0/0.0 0µA/0µA A<B, A=B, A>B ata outputs (active High) 0/.0mA/0mA NOTE: One (.0) FAST unit load is defined as: 0µA in the High state and 0.mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL COMP P V CC = Pin GN = Pin A0 A A A B0 B B B I A<B I A=B I A>B A>B A=B A<B SF000 0 < = > P< P= P> SF000 September, 00 0

19 -bit magnitude comparator F LOGIC IAGRAM A B A>B A B I A<B I A=B A=B I A>B A B A<B A0 B0 0 V CC = Pin GN = Pin SF000 FUNCTION TABLE COMPARING INPUTS EXPANSION INPUTS OUTPUTS A,B A,B A,B A0,B0 I A>B I A<B I A=B A>B A<B A=B A>B X X X X X X H L L A<B X X X X X X L H L A=B A>B X X X X X H L L A=B A<B X X X X X L H L A=B A=B A>B X X X X H L L A=B A=B A<B X X X X L H L A=B A=B A=B A0>B0 X X X H L L A=B A=B A=B A0<B0 X X X L H L A=B A=B A=B A0=B0 H L L H L L A=B A=B A=B A0=B0 L H L L H L A=B A=B A=B A0=B0 L L H L L H A=B A=B A=B A0=B0 X X H L L H A=B A=B A=B A0=B0 H H L L L L A=B A=B A=B A0=B0 L L L H H L H = High voltage level L = Low voltage level X = on t care September,

20 -bit magnitude comparator F APPLICATION INPUTS (LSB) B A B A B A B0 A0 B A B A B A B A B A B A L L B A B A B A<B A A=B B0 A>B A0 I A<B I A=B I A>B B A B A B A<B A A=B B0 A>B A0 I A<B I A=B I A>B NC NC The parallel expansion scheme shown in Figure demonstrates the most efficient general use of these comparators. The expansion inputs can be used as a fifth input bit position except on the least significant device, which must be connected as in the serial scheme. The expansion inputs used by labeling I A>B as an A input, I A<B as a B input and setting I A=B = Low. The F can be used as a -bit comparator only when the outputs are used to drive the (A0 A) and (B0 B) inputs of another F device. The parallel technique can be expanded to any number of bits as shown in Table. Table. WOR LENGTH NUMBER OF PACKAGES SPEES F bits ns bits ns 0 bits ns B B B A A A B B B A B A B A<B A B A<B OUTPUTS A A A=B NC A A=B B0 B0 A>B B0 A>B A0 A0 A0 B A L I A<B I A=B I A>B A<B A=B A>B B B A A B B A A B B A<B A A A=B NC B B0 A>B A A0 B A L I A<B I A=B I A>B B B A A B B A A B B A<B A A A=B (LSB) B0 B0 A>B A0 A0 L H L I A<B I A=B I A>B SF000 Figure. Comparison of Two -Bit Words September,

21 Octal transceiver (-State) ALSA/ALSA- FEATURES Octal bidirectional bus interface -State buffer outputs sink ma and source ma Outputs are placed in high impedance state during power-off conditions The - version sinks ma PIN CONFIGURATION T/R A0 A A A 0 V CC OE B0 B B The ALSA is an octal transceiver featuring non-inverting -State bus compatible outputs in both transmit and receive directions. The device features an output enable (OE) input for easy cascading and transmit/receive (R/T) input for direction control. The ALSA- is the same as the ALSA except that both ports sink ma within the ±% V CC range. A A A A GN 0 B B B B B SF00 TYPE PROPAGATION ELAY SUPPLY CURRENT (TOTAL) ALSA.0ns ma ALSA-.0ns ma ORERING INFORMATION 0-pin plastic IP 0-pin plastic SOL 0-pin plastic SSOP Type II ORER COE COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C ALSAN, ALSA-N ALSA, ALSA- ALSAB, ALSA-B RAWING NUMBER SOT- SOT- SOT- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE NOTE: PINS ALS (U.L.) LOA VALUE A0 A, B0 B ata inputs.0/.0 0µA/0.mA OE Output Enable input (active-low).0/.0 0µA/0.mA T/R Transmit/receive input.0/.0 0µA/0.mA A0 A A port outputs 0/0 ma/ma B0 B B port outputs 0/0 ma/ma A0 A A port outputs (- version) 0/0 ma/ma B0 B B port outputs (- version) 0/0 ma/ma One (.0) ALS unit load is defined as: 0µA in the High state and 0.mA in the Low state. Jun

22 Octal transceiver (-State) ALSA/ALSA- LOGIC SYMBOL IEC/IEEE SYMBOL G EN [BA] EN [AB] OE T/R A0 A A A A A B0 B B B B B A B A B V CC = Pin 0 GN = Pin 0 SF00 SC000 LOGIC IAGRAM A0 A A A A A A A OE T/R V CC = Pin 0 GN = Pin 0 B0 B B B B B B B SF000 FUNCTION TABLE OE INPUTS T/R OUTPUTS L L Bus B data to Bus A L H Bus A data to Bus B H X Z H = High voltage level L = Low voltage level X = on t care Z = High impedance off state Jun 0

23 Hex flip-flop ALS FEATURES Four edge-triggered flip-flops Buffered common clock Buffered asynchronous master reset PIN CONFIGURATION MR 0 V CC 0 The ALS has six edge-triggered -type flip-flops with individual inputs and outputs. The common buffered clock () and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop s output. All outputs will be forced Low independent of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where true outputs only are required, and the clock and master reset are common to all storage elements. TYPE f MAX SUPPLY CURRENT (TOTAL) ALS 0MHz ma GN ORERING INFORMATION 0 ORER COE COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C SF00 RAWING NUMBER -pin plastic IP ALSN SOT- -pin plastic SO ALS SOT0- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE NOTE: PINS ALS (U.L.) LOA VALUE 0 ata inputs.0/.0 0µA/0.mA Clock Pulse input (active rising edge).0/.0 0µA/0.mA MR Master Reset input (active-low).0/.0 0µA/0.mA 0 ata outputs 0/0 0.mA/mA One (.0) ALS unit load is defined as: 0µA in the High state and 0.mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL R C MR V CC = Pin GN = Pin 0 SF00 SF000 Feb

24 Hex flip-flop ALS LOGIC IAGRAM 0 R R R R R R MR V CC = Pin GN = Pin 0 0 SF00 FUNCTION TABLE INPUTS OUTPUTS OPERATING MR n MOE L X X L Reset (clear) H h H Load H I L Load 0 NOTES: H = High-voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low-voltage level l = Low state must be present one setup time before the Low-to-High clock transition X = on t care = Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT V CC Supply voltage 0. to +.0 V V IN Input voltage 0. to +.0 V I IN Input current 0 to + ma V OUT Voltage applied to output in High output state 0. to V CC V I OUT Current applied to output in Low output state ma T amb Operating free-air temperature range 0 to +0 C T stg Storage temperature range to +0 C RECOMMENE OPERATING CONITIONS SYMBOL PARAMETER LIMITS MIN NOM MAX V CC Supply voltage..0. V V IH High-level input voltage.0 V V IL Low-level input voltage 0. V I IK Input clamp current ma I OH High-level output current 0. ma I OL Low-level output current ma T amb Operating free-air temperature range 0 +0 C UNIT Feb 0

25 Octal -type flip-flop ALS FEATURES Eight edge-triggered -type flip-flops Buffered common clock Buffered asynchronous master reset See ALS for clock enable version See ALS for transparent latch version See ALS for -State version The ALS has eight edge-triggered -type flip-flops with individual inputs and outputs. The common buffered clock () and master reset (MR) inputs load and reset all flip-flops simultaneously. The register is fully edge-triggered. The state of each input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop s output. All outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the and MR are common to all flip-flops. TYPE f MAX SUPPLY CURRENT (TOTAL) ALS MHz ma PIN CONFIGURATION MR 0 V CC 0 0 GN 0 ORERING INFORMATION ORER COE COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C SF00 RAWING NUMBER 0-pin plastic IP ALSN SOT- 0-pin plastic SO ALS SOT- 0-pin plastic SSOP Type II ALSB SOT- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE NOTE: PINS ALS (U.L.) LOA VALUE 0 ata inputs.0/.0 0µA/0.mA Clock pulse input (active rising edge).0/.0 0µA/0.mA MR Master Reset input (active-low).0/.0 0µA/0.mA 0 -State outputs 0/0.mA/mA One (.0) ALS unit load is defined as: 0µA in the High state and 0.mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL R 0 MR 0 C V CC = Pin 0 GN = Pin 0 SF00 SF00 Feb 0 00

26 Octal -type flip-flop ALS LOGIC IAGRAM 0 R R R R R R R R MR V CC = Pin 0 GN = Pin 0 0 SF00 FUNCTION TABLE INPUTS OUTPUTS MR n n OPERATING MOE L X X L Reset (clear) H h H Load H l L Load 0 H = High-voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low-voltage level l = Low state must be present one setup time before the Low-to-High clock transition X = on t care = Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT V CC Supply voltage 0. to +.0 V V IN Input voltage 0. to +.0 V I IN Input current 0 to + ma V OUT Voltage applied to output in High output state 0. to V CC V I OUT Current applied to output in Low output state ma T amb Operating free-air temperature range 0 to +0 C T stg Storage temperature range to +0 C RECOMMENE OPERATING CONITIONS SYMBOL PARAMETER LIMITS MIN NOM MAX UNIT V CC Supply voltage..0. V V IH High-level input voltage.0 V V IL Low-level input voltage 0. V I IK Input clamp current ma I OH High-level output current. ma I OL Low-level output current ma T amb Operating free-air temperature range 0 +0 C Feb 0

27 -bit bidirectional universal shift register F FEATURES Shift right and shift left capability Synchronous parallel and serial data transfer Easily expanded for both serial and parallel operation Asynchronous Master Reset Hold (do nothing) mode The functional characteristics of the F -Bit Bidirectional Shift Register are indicated in the Logic iagram and Function Table. The register is fully synchronous, with all operations taking place in less than ns (typical) for F, making the device especially useful for implementing very high speed Us, or for memory buffer registers. The F design has special logic features which increase the range of application. The synchronous operation of the device is determined by two Mode Select inputs, S0 and S. As shown in the Mode Select-Function Table, data can be entered and shifted from left to right (shift right, 0, etc.), or right to left (shift left,, etc.), or parallel data can be entered, loading all bits of the register simultaneously. When both S0 and S are Low, existing data is retained in a hold (do nothing) mode. The first and last stages provide -type Serial ata inputs ( SR, SL ) to allow multistage shift right or shift left data transfers without interfering with parallel load operation. Mode Select and data inputs on the F are edge-triggered, responding only to the Low-to-High transition of the Clock (). Therefore, the only timing restriction is that the Mode Select and selected data inputs must be stable one setup time prior to the Low-to-High transition of the clock pulse. Signals on the Mode Select, Parallel ata (0 ) and Serial ata ( SR, SL ) can change when the clock is in either state, provided only the recommended setup and hold times, with respect to the clock rising edge, are observed. The four Parallel ata inputs (0 ) are -type inputs. ata appearing on (0 ) inputs when S0 and S are High is transferred to the 0 outputs respectively, following the next Low-to-High transition of the clock. When Low, the asynchronous Master Reset (MR) overrides all other input conditions and forces the outputs Low. PIN CONFIGURATION MR SR 0 SL GN 0 V CC 0 S S0 SF00 TYPE f MAX SUPPLY CURRENT (TOTAL) F 0MHz ma ORERING INFORMATION COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C PKG WG # -pin plastic IP NFN SOT- -pin plastic SO NF SOT0- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE PINS F (U.L.) LOA VALUE 0 Parallel data inputs.0/.0 0µA/0.mA SR Serial data input (Shift Right).0/.0 0µA/0.mA SL Serial data input (Shift Left).0/.0 0µA/0.mA S0, S Mode Select inputs.0/.0 0µA/0.mA Clock Pulse input (active rising edge).0/.0 0µA/0.mA MR Asynchronous master Reset input (Active Low).0/.0 0µA/0.mA 0 ata outputs 0/.0mA/0mA NOTE: One (.0) FAST unit load is defined as: 0µA in the High state and 0.mA in the Low state. April, 0

28 -bit bidirectional universal shift register F LOGIC SYMBOL IEC/IEEE SYMBOL 0 SR S0 S 0 SL 0 SRG R 0 M 0 C / V CC = Pin GN = Pin MR 0 SF00,,,,,, SF00 LOGIC IAGRAM S S0 0 SL S R R S R R S R R S SR MR R R V CC = Pin GN = Pin SF000 April,

29 -bit bidirectional universal shift register F FUNCTION TABLE INPUTS OUTPUTS MR S S0 SR SL n 0 OPERATING MOES X L X X X X X L L L L Reset (clear) X H l l X X X q0 q q q Hold (do nothing) H h l X l X q q q L H h l X h X q q q H H l h l X X L q0 q q H l h h X X H q0 q q Shift left Shift right H h h X X dn d0 d d d Parallel load H = High voltage level h = High voltage level one setup time prior to Low-to-High clock transition L = Low voltage level l = Low voltage level one setup time prior to Low-to-High clock transition X = on t care = Low-to-High clock transition dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition. ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V CC Supply voltage 0. to +.0 V V IN Input voltage 0. to +.0 V I IN Input current 0 to + ma V OUT Voltage applied to output in High output state 0. to V CC V I OUT Current applied to output in Low output state 0 ma T amb Operating free-air temperature range 0 to +0 C T stg Storage temperature range to +0 C RECOMMENE OPERATING CONITIONS SYMBOL PARAMETER LIMITS MIN NOM MAX V CC Supply voltage..0. V V IH High-level input voltage.0 V V IL Low-level input voltage 0. V I IK Input clamp current ma I OH High-level output current ma I OL Low-level output current 0 ma T amb Operating free-air temperature range 0 +0 C UNIT April,

30 -bit bidirectional universal shift register F AC WAVEFORMS For all waveforms, V M =.V. The shaded areas indicate when the input is permitted to change for predictable output performance. /f MAX MR V M V M V M t w (H) V M V M t w (L) t REC V M t PHL t PLH t PHL n V M V M n V M SF00 Waveform. Propagation elay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency SF00 Waveform. Master Reset Pulse Width, Master Reset to Output elay, and Master Reset to Clock Recovery Time n, SR, SL S0, S V M V M V M V M t s (H) t h (H) t s (L) t h (L) V M V M SF00 Waveform. Setup and Hold Times TIMING IAGRAM Typical Clear, Load, Shift-Right, Shift-Left and Inhibit Sequence S0 S SERIAL ATA INPUTS PARALLEL ATA INPUTS OUTPUTS MR SR SL 0 0 H L H L SHIFT RIGHT SHIFT LEFT INHIBIT CLEAR CLEAR LOA SF00 April,

31 -bit binary counters FA, FA FEATURES Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock Asynchronous Master Reset (FA) Synchronous Reset (FA) High speed synchronous expansion Typical count rate of 0MHz Industrial range ( 0 C to + C) available -bit binary counters feature an internal carry look-ahead and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the Parallel Enable (PE) input disables the counting action and causes the data at the 0 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at Count Enable (CEP, CET) inputs. A Low level at the Master Reset (MR) input sets all the four outputs of the flip-flops (0 ) in FA to Low levels, regardless of the levels at, PE, CET and CEP inputs (thus providing an asynchronous clear function). For the FA, the clear function is synchronous. A Low level at the Synchronous Reset (SR) input sets all four outputs of the flip-flops (0 ) to Low levels after the next positive-going transition on the clock () input (provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at PE, CET, and CEP inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAN gate (see Figure ). The carry look-ahead simplifies serial cascading of the counters. Both Count Enable (CEP and CET) inputs must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of 0. This pulse can be used to enable the next cascaded stage (see Figure ). The TC output is subjected to decoding spikes due to internal race conditions. Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters. TYPE FA FA f MAX 0MHz SUPPLY CURRENT (TOTAL) ma ORERING INFORMATION COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C ORER COE INUSTRIAL RANGE V CC = V ±0%, T amb = 0 C to + C RAWING NUMBER -pin plastic IP NFAN, NFAN IFAN, IFAN SOT- -pin plastic SO NFA, NFA IFA, IFA SOT0- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE PINS F (U.L.) LOA VALUE 0 ata inputs.0/.0 0µA/0.mA CEP Count Enable Parallel input.0/.0 0µA/0.mA CET Count Enable Trickle input.0/.0 0µA/.mA Clock input (active rising edge).0/.0 0µA/0.mA PE Parallel Enable input (active Low).0/.0 0µA/.mA MR SR Asynchronous Master Reset input (active Low) for FA Synchronous Reset input (active Low) for FA.0/.0 0µA/0.mA.0/.0 0µA/0.mA TC Terminal count output 0/.0mA/0mA 0 Flip-flop outputs 0/.0mA/0mA NOTE: One (.0) FAST unit load is defined as: 0µA in the High state and 0.mA in the Low state. 000 Jun 0 0 0

32 -bit binary counters FA, FA FA PIN CONFIGURATION FA PIN CONFIGURATION MR V CC SR V CC TC TC CEP 0 CET CEP 0 CET GN PE GN PE SF00 SF00 FA LOGIC SYMBOL FA LOGIC SYMBOL PE 0 PE 0 CEP CEP 0 CET TC 0 CET TC MR 0 SR 0 V CC = Pin GN = Pin SF00 V CC = Pin GN = Pin SF00 FA LOGIC SYMBOL (IEEE/IEC) FA LOGIC SYMBOL (IEEE/IEC) 0 CTR IV R M G G C /,,+ 0 CTR IV R M G G C /,,+,, CT= CT= SF000 SF Jun 0

33 -bit binary counters FA, FA STATE IAGRAM APPLICATIONS +V CC 0 0 PE CEP CET FA TC CLOCK SR 0 0 SF00 SF00 Figure. Maximum count modifying scheme Terminal count = H H = Enable count or L L = isable count 0 PE CEP 0 PE CEP 0 PE CEP 0 PE CEP 0 PE CEP CET FA TC CET FA TC CET FA TC CET FA TC CET FA TC SR 0 SR 0 SR 0 SR 0 SR 0 SF00 Figure. Synchronous multistage counting scheme FA MOE SELECT FUNCTION TABLE INPUTS OUTPUTS MR CEP CET PE n n TC OPERATING MOE L X X X X X L L Reset (clear) H X X l l L L H X X l h H () Parallel load H h h h X count () Count H X l X h X q n () H X X l h X q n L Hold (do nothing) 000 Jun 0

34 -bit binary counters FA, FA FA MOE SELECT FUNCTION TABLE INPUTS OUTPUTS SR CEP CET PE n n TC OPERATING MOE l X X X X L L Reset (clear) h X X l l L L h X X l h H () h h h h X count () Count h X l X h X q n () h X X l h X q n L Parallel load Hold (do nothing) H = High voltage level h = High voltage level one setup prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one setup prior to the Low-to-High clock transition q n = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition X = on t care = Low-to-High clock transition () = The TC output is High when CET is High and the counter is at Terminal Count (HHHH for FA) () = The TC output is High when CET is High and the counter is at Terminal Count (HHHH for FA) FA LOGIC IAGRAM MR PE CET CEP 0 0 R 0 R R R TC V CC = Pin GN = Pin SF Jun 0

35 -bit binary counters FA, FA FA LOGIC IAGRAM SR PE CET CEP TC V CC = Pin GN = Pin SF00 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V CC Supply voltage 0. to +.0 V V IN Input voltage 0. to +.0 V I IN Input current 0 to + ma V OUT Voltage applied to output in High output state 0. to V CC V I OUT Current applied to output in Low output state 0 ma T amb Operating free-air temperature range Commercial range 0 to +0 C Industrial range 0 to + C T stg Storage temperature range to +0 C 000 Jun 0

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38 Up/own binary counter with reset and ripple clock F FEATURES High speed MHz typical f MAX Synchronous, reversible counting -Bit binary Asynchronous parallel load capability Cascadable without external logic Single up/down control input The F is a -bit binary counter. It contains four edge-triggered master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operations. Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs ( 0 - ) is loaded into the counter and appears on the outputs when the Parallel Load (PL) input is Low. This operation overrides the counting function. Counting is inhibited by a High level on the count enable (CE) input. When CE is Low, internal state changes are initiated. Overflow/underflow indications are provided by two types of outputs, the Terminal Count (TC) and Ripple Clock (RC). The TC output is normally Low and goes High when: ) the count reaches zero in the countdown mode or ) reaches in the count up mode. The TC output will remain High until a state change occurs, either by counting or presetting, or until U/ is changed. TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is High and CE is Low, the RC follows the clock pulse. The RC output essentially duplicates the Low clock pulse width, although delayed in time by two gate delays. PIN CONFIGURATION 0 CE U/ GN 0 SF00 V CC TYPE f MAX SUPPLY CURRENT (TOTAL) F MHz 0mA ORERING INFORMATION 0 RC TC PL COMMERCIAL RANGE V CC = V ±0%, T amb = 0 C to +0 C PKG WG # -pin plastic IP NFN SOT- -pin plastic SO NF SOT0- INPUT AN OUTPUT LOAING AN FAN-OUT TABLE PINS F(U.L.) LOA VALUE 0 - ata inputs.0/.0 0µA/0.mA CE Count enable input (active Low).0/.0 0µA/.mA Clock pulse input (active rising edge).0/.0 0µA/0.mA PL Asynchronous parallel load control input (active Low).0/.0 0µA/0.mA U/ Up/down count control input.0/.0 0µA/0.mA 0 - Flip-flop outputs 0/.0mA/0mA RC Ripple clock output (active low) 0/.0mA/0mA TC Terminal count output 0/.0mA/0mA NOTE: One (.0) FAST Unit Load (U.L.) is defined as: 0µA in the High state and 0.mA in the Low state. Jul 0

39 Up/own binary counter with reset and ripple clock F LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) V CC =Pin GN=Pin 0 0 CE U/ RC TC PL 0 SF000 0 EN CTR IV 0 M[OWN] (CT=0)Z M[UP] (CT=)Z, /,+ G C [LOA] [] [] [] [],, + SF00 LOGIC IAGRAM 0 PL 0 U/ CE J S K R J S K R J S K R J S K R V CC = Pin GN = Pin RC TC 0 SF00 Jul

40 Up/own binary counter with reset and ripple clock F MOE SELECT FUNCTION TABLE INPUTS OUTPUTS OPERATING MOE PL U/ CE n n L L X X X X X X L H L H Parallel load H L l X Count up Count up H H l X Count down Count down H X H X X No change Hold (do nothing) TC AN RC FUNCTION TABLE INPUTS TERMINAL COUNT STATE OUTPUTS U/ CE 0 TC RC H H X H H H H L H L H X H H H H H H L L H H H H H L H X L L L L L H H H X L L L L H H H L L L L L H H = High voltage level steady state L = Low voltage level steady state X = on t care = Low pulse = Low-to-High clock transition l = Low voltage level one set-up time prior to the Low-to-High clock transition Jul

41 Up/own binary counter with reset and ripple clock F APPLICATIONS IRECTION CONTROL ENABLE CLOCK U/ CE RC U/ RC U/ RC CE CE a. N-Stage Counter Using Ripple Clock IRECTION CONTROL ENABLE U/ CE RC U/ RC U/ RC CE CE CLOCK b. Synchronous N-Stage Counter with Common Clock Using Ripple/Clock IRECTION CONTROL ENABLE U/ CE * U/ CE * U/ CE TC TC TC CLOCK * = Carry Gate c. Synchronous N-Stage Counter with Common Clock and Terminal Count SF00 Figure. The F simplifies the design of multi-stage counters, as indicated in Figure, each RC output is used as the clock input for the next higher stage. When the clock source has a limited drive capability this configuration is particularly advantageous, since the clock source drives only the first stage. It is only necessary to inhibit the first stage to prevent counting in all stages, since a High signal on CE inhibits the RC output pulse as indicated in the Mode Select Table. The timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. This is a disadvantage of the configuration in some applications. Figure b shows a method of causing state changes to occur simultaneously in all stages. The RC output signals propagate in ripple fashion and all clock inputs are driven in parallel. The Low state duration of the clock in this configuration must be long enough to allow the negative-going edge of the RC signal to ripple through to the last stage before the clock goes High. Since the RC output of any package goes High shortly after its clock input goes High, there is no such restriction on the High state duration of the clock. In Figure c, the configuration shown avoids ripple delays and their associated restrictions. The combined TC signals from all the preceding stages forms the CE input signal for a given stage. An enable signal must also be included in each carry gate in order to inhibit counting. The TC output of a given stage is not affected by its own CE, therefore, the simple inhibit scheme of Figure a and b does not apply. Jul

42 MLS -Bit Binary Adder with Fast Carry General escription These full adders perform the addition of two -bit binary numbers. The sum ( ) outputs are provided for each bit and the resultant carry (C) is obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial lookahead performance at the economy and reduced package count of a ripple-carry implementation. The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accomplished without the need for logic or level inversion. Ordering Code: Features evices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. August Revised March 000 Full-carry look-ahead across the four bits Systems achieve partial look-ahead performance with the economy of ripple carry Typical add times Two -bit words ns Two -bit words ns Typical power dissipation per -bit adder mw Order Number Package Number Package escription MLSM MA -Lead Small Outline Integrated Circuit (SOIC), JEEC MS-0, 0.0 Narrow MLSN NE -Lead Plastic ual-in-line Package (PIP), JEEC MS-00, 0.00 Wide MLS -Bit Binary Adder with Fast Carry Connection iagram 000 Fairchild Semiconductor Corporation S00

43 MLS Function Table H = HIGH Level, L = LOW Level Input conditions at A, B, A, B, and C0 are used to determine outputs and and the value of the internal carry C. The values at C, A, B, A, and B are then used to determine outputs,, and C. Logic iagram