74HC165; 74HCT bit parallel-in/serial out shift register
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1 Rev December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of V CC. Asynchronous 8-bit parallel load Synchronous serial input Complies with JEDEC standard no. 7A Input levels: For 74HC165: CMOS level For 74HCT165: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from 40 C to+85c and from 40 C to+125c Parallel-to-serial data conversion Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC165D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT HCT165D 74HC165DB 74HCT165DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
2 Table 1. Ordering information continued Type number Package Temperature range Name Description Version 74HC165PW 74HCT165PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm 74HC165BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin 74HCT165BQ quad flat package; no leads; 16 terminals; body mm 5. Functional diagram SOT403-1 SOT763-1 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Functional diagram Product data sheet Rev December of 21
3 6. Pinning information 6.1 Pinning (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration (SO16 and (T)SSOP16) Fig 5. Pin configuration (DHVQFN16) 6.2 Pin description Table 2. Pin description Symbol Pin Description PL 1 asynchronous parallel load input (active LOW) CP 2 clock input (LOW-to-HIGH edge-triggered) Q7 7 complementary output from the last stage GND 8 ground (0 V) Q7 9 serial output from the last stage DS 10 serial data input D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn) CE 15 clock enable input (active LOW) V CC 16 positive supply voltage Product data sheet Rev December of 21
4 7. Functional description Table 3. Function table [1] Operating modes Inputs Qn registers Outputs PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7 parallel load L X X X L L L to L L H L X X X H H H to H H L serial shift H L l X L q0 to q5 q6 q6 H L h X H q0 to q5 q6 q6 H L l X L q0 to q5 q6 q6 H L h X H q0 to q5 q6 q6 hold do nothing H H X X X q0 q1 to q6 q7 q7 H X H X X q0 q1 to q6 q7 q7 [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition; X = don t care; = LOW-to-HIGH clock transition. Fig 6. Timing diagram Product data sheet Rev December of 21
5 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC +0.5V [1] - 20 ma I OK output clamping current V O < 0.5 V or V O >V CC +0.5V [1] - 20 ma I O output current 0.5 V < V O < V CC +0.5V - 25 ma I CC supply current - 50 ma I GND ground current 50 - ma T stg storage temperature C P tot total power dissipation T amb = 40 C to +125 C SO16 package [2] mw (T)SSOP16 package [3] mw DHVQFN16 package [4] mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] P tot derates linearly with 8 mw/k above 70 C. [3] P tot derates linearly with 5.5 mw/k above 60 C. [4] P tot derates linearly with 4.5 mw/k above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC165 74HCT165 Unit Min Typ Max Min Typ Max V CC supply voltage V V I input voltage 0 - V CC 0 - V CC V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature C t/v input transition rise and fall rate V CC = 2.0 V ns/v V CC = 4.5 V ns/v V CC = 6.0 V ns/v Product data sheet Rev December of 21
6 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC165 V IH HIGH-level V CC = 2.0 V V input voltage V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level V CC = 2.0 V V input voltage V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I = V IH or V IL I O = 20 A; V CC = 2.0 V V I O = 20 A; V CC = 4.5 V V I O = 20 A; V CC = 6.0 V V I O = 4.0 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V V OL LOW-level output voltage V I = V IH or V IL I O = 20 A; V CC = 2.0 V V I O = 20 A; V CC = 4.5 V V I O = 20 A; V CC = 6.0 V V I O = 4.0 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V I I input leakage V I = V CC or GND; A current V CC =6.0V I CC supply current V I = V CC or GND; I O =0A; A V CC =6.0V C I input capacitance pf 74HCT165 V IH HIGH-level V CC = 4.5 V to 5.5 V V input voltage V IL LOW-level V CC = 4.5 V to 5.5 V V input voltage V OH HIGH-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 20 A V I O = 4.0 ma V V OL LOW-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 20 A; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V I I input leakage current V I = V CC or GND; V CC =6.0V A Product data sheet Rev December of 21
7 Table 6. Static characteristics continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max I CC supply current V I = V CC or GND; I O =0A; V CC =6.0V I CC C I additional supply current input capacitance 11. Dynamic characteristics A per input pin; V I =V CC 2.1 V; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V Dn and DS inputs A CP CE, and PL inputs A pf Table 7. Dynamic characteristics GND (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC165 t pd t t propagation delay transition time CP or CE to Q7, Q7; [1] see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 5.0 V; C L =15pF ns PL to Q7, Q7; see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 5.0 V; C L =15pF ns D7 to Q7, Q7; see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 5.0 V; C L =15pF ns Q7, Q7 output; see Figure 7 [2] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev December of 21
8 Table 7. Dynamic characteristics continued GND (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit t W pulse width CP input HIGH or LOW; see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns PL input LOW; see Figure 8 t rec recovery time PL to CP, CE; see Figure 8 t su set-up time DS to CP, CE; see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns CE to CP and CP to CE; see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Dn to PL; see Figure 11 t h hold time DS to CP, CE and Dn to PL; see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns CE to CP and CP to CE; see Figure 10 Min Typ Max Min Max Min Max V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev December of 21
9 Table 7. Dynamic characteristics continued GND (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max f max maximum CP input; see Figure 7 frequency V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz V CC = 5.0 V; C L =15pF MHz C PD power dissipation capacitance per package; V I =GNDtoV CC [3] pf 74HCT165 t pd t t propagation delay transition time CE, CP to Q7, Q7; [1] see Figure 7 V CC = 4.5 V ns V CC = 5.0 V; C L =15pF ns PL to Q7, Q7; see Figure 8 V CC = 4.5 V ns V CC = 5.0 V; C L =15pF ns D7 to Q7, Q7; see Figure 9 V CC = 4.5 V ns V CC = 5.0 V; C L =15pF ns Q7, Q7 output; see Figure 7 [2] V CC = 4.5 V ns t W pulse width CP input; see Figure 7 V CC = 4.5 V ns PL input; see Figure 8 V CC = 4.5 V ns t rec recovery time PL to CP, CE; see Figure 8 V CC = 4.5 V ns t su set-up time DS to CP, CE; see Figure 10 V CC = 4.5 V ns CE to CP and CP to CE; see Figure 10 V CC = 4.5 V ns Dn to PL; see Figure 11 V CC = 4.5 V ns t h hold time DS to CP, CE and Dn to PL; see Figure 10 V CC = 4.5 V ns CE to CP and CP to CE; see Figure 10 V CC = 4.5 V ns Product data sheet Rev December of 21
10 Table 7. Dynamic characteristics continued GND (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max f max maximum CP input; see Figure 7 frequency V CC = 4.5 V MHz V CC = 5.0 V; C L =15pF MHz C PD power dissipation capacitance per package; V I =GNDtoV CC 1.5 V [3] pf [1] t pd is the same as t PHL and t PLH. [2] t t is the same as t THL and t TLH. [3] C PD is used to determine the dynamic power dissipation (P D in W). P D = C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; (C L V 2 CC f o ) = sum of outputs; C L = output load capacitance in pf; V CC = supply voltage in V. 12. Waveforms Fig 7. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the maximum clock frequency and the output transition times Product data sheet Rev December of 21
11 Fig 8. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) recovery time Fig 9. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW Product data sheet Rev December of 21
12 Fig 10. The shaded areas indicate when the input is permitted to change for predictable output performance Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. (1) CE may change only from HIGH-to-LOW while CP is LOW, see Section 1. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE) Fig 11. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL) Table 8. Measurement points Type Input Output V I V M V M 74HC165 V CC 0.5V CC 0.5V CC 74HCT165 3 V 1.3 V 1.3 V Product data sheet Rev December of 21
13 Test data is given in Table 9. Definitions for test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistance. S1 = Test selection switch Fig 12. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH 74HC165 V CC 6ns 15pF, 50 pf 1k open 74HCT165 3V 6ns 15pF, 50 pf 1k open Product data sheet Rev December of 21
14 13. Package outline Fig 13. Package outline SOT109-1 (SO16) Product data sheet Rev December of 21
15 Fig 14. Package outline SOT338-1 (SSOP16) Product data sheet Rev December of 21
16 Fig 15. Package outline SOT403-1 (TSSOP16) Product data sheet Rev December of 21
17 Fig 16. Package outline SOT763-1 (DHVQFN16) Product data sheet Rev December of 21
18 14. Abbreviations Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes v Product data sheet - v.3 Modifications: Type numbers 74HC165N and 74HCT165N (SOT38-4) removed. v Product data sheet - _CNV v.2 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Package SOT763-1 (DHVQFN16) added to Section 4 Ordering information and Section 13 Package outline. Family data added, see Section 10 Static characteristics _CNV v.2 December 1990 Product specification - - Product data sheet Rev December of 21
19 16. Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Product data sheet Rev December of 21
20 Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia s specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia s standard warranty and Nexperia s product specifications. Translations A non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Product data sheet Rev December of 21
21 18. Contents 1 General description Features and benefits Applications Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Date of release: 28 December 2015
22 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: 74HC165BQ,115 74HC165D,652 74HC165DB,112 74HC165DB,118 74HC165D,653 74HC165PW,112 74HC165PW,118 74HCT165BQ,115 74HCT165D,652 74HCT165DB,112 74HCT165DB,118 74HCT165D,653 74HCT165PW,112 74HCT165PW,118
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Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.
Rev. 12 5 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH
3-to-8 line decoder/demultiplexer; inverting
Rev. 4 4 March 2016 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The is a 3-to-8 line decoder/demultiplexer.
74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger
Rev. 4 26 January 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,
Octal buffer/line driver; 3-state
Rev. 4 1 March 2016 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC244 and 74HCT244. The is an octal non-inverting buffer/line
74HC390; 74HCT General description. 2. Features and benefits. Dual decade ripple counter
Rev. 3 16 August 2016 Product data sheet 1. General description The is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two
74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate
Rev. 4 17 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use
74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate
8-input NND gate Rev. 6 27 December 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-input NND gate. Inputs include clamp diodes. This enables
74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate
Rev. 3 3 September 2012 Product data sheet 1. General description 2. Features and benefits The is a dual 4-input NND gate. Inputs include clamp diodes. This enables the use of current limiting resistors
74HC32-Q100; 74HCT32-Q100
Rev. 1 1 ugust 2012 Product data sheet 1. General description The is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages
74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter
Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW
74HC597-Q100; 74HCT597-Q100
Rev. 1 26 May 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit
The 74AXP1G04 is a single inverting buffer.
Rev. 1 25 August 2014 Product data sheet 1. General description The is a single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This
74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops
74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
Rev. 04 2 May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified
74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger
Rev. 4 8 pril 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and
74LVC1G125-Q100. Bus buffer/line driver; 3-state
Rev. 2 8 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).
74HC4040-Q100; 74HCT4040-Q100
74HC4040-100; 74HC4040-100 Rev. 1 24 March 2014 Product data sheet 1. General description he 74HC4040-100; 74HC4040-100 is a with a clock input (CP), an overriding asynchronous master reset input (MR)
74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.
Rev. 3 27 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description
1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description The is a 1-of-2 non-inverting demultiplexer with a 3-state output. The
74HC08; 74HCT08. Temperature range Name Description Version. -40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.
Rev. 6 13 June 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number Package The is a quad 2-input ND gate. Inputs include
74HC08; 74HCT General description. 2. Features and benefits. 3. Ordering information. Quad 2-input AND gate
Quad 2-input ND gate Rev. 4 6 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input ND gate. Inputs include clamp diodes. This
Bus buffer/line driver; 3-state
Rev. 12 2 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).
74HC08-Q100; 74HCT08-Q100
Rev. 1 16 July 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC08-Q100; 7 4HCT08-Q100 is a quad 2-input ND gate. Inputs include clamp diodes. This
The 74AUP2G34 provides two low-power, low-voltage buffers.
Rev. 6 17 September 2015 Product data sheet 1. General description The provides two low-power, low-voltage buffers. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise
74HC373-Q100; 74HCT373-Q100
Rev. 1 10 August 2012 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
74HC03-Q100; 74HCT03-Q100
Rev. 1 4 July 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NND gate with open-drain outputs. Inputs include clamp diodes that enable
74HC2G125; 74HCT2G125
Rev. 5 17 March 2014 Product data sheet 1. General description 2. Features and benefits The 74HC2G125; 74HC2G125 are dual buffer/line drivers with 3-state outputs controlled by the output enable inputs
74HC2G08-Q100; 74HCT2G08-Q100
Rev. 1 11 November 2013 Product data sheet 1. General description The is a dual 2-input ND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to s in
14-stage binary ripple counter with oscillator
Rev. 4 17 March 2016 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4060; 74HCT4060. The is a 14-stage ripple-carry counter/divider
74LVC2G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger
Rev. 11 15 December 2016 Product data sheet 1. General description The is a single positive-edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs,
4-bit magnitude comparator
Rev. 6 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a that compares two 4-bit words, A and B, and determines whether A is greater than
74HC04; 74HCT General description. 2. Features and benefits. 3. Ordering information. Hex inverter
Rev. 4 3 ugust 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The is a hex inverter. The inputs include clamp diodes that enable the use of current limiting
74LVC823A-Q General description. 2. Features and benefits
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Rev. 1 15 September 2016 Product data sheet 1. General description The is a 9-bit D-type flip-flop with common clock
74AHC30-Q100; 74AHCT30-Q100
Rev. 1 20 November 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky
74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.
Rev. 03 September 200 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible
74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
Rev. 2 16 March 2015 Product data sheet 1. General description The is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.
Low-power configurable multiple function gate
Rev. 2 16 September 2015 Product data sheet 1. General description The is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions
74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate
Rev. 5 14 March 2018 Product data sheet 1 General description 2 Features 3 Ordering information Table 1. Ordering information Type number 74HC1G08GW 74HCT1G08GW 74HC1G08GV 74HCT1G08GV The is a single.
74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function.
Quad 2-input NND gate Rev. 5 25 November 200 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard
74LVC1G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger
Rev. 13 5 December 2016 Product data sheet 1. General description The is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs,
74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting
Rev. 3 21 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit inverting buffer/line driver with 3-state outputs. The device features
Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.
Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance
74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.
Rev. 1 20 March 2013 Product data sheet 1. General description The is a triple 3-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators
74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.
Rev. 4 4 September 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
Low-power dual Schmitt trigger inverter
Rev. 1 9 October 2014 Product data sheet 1. General description The is a dual inverter with Schmitt-trigger inputs. It transforms slowly changing input signals into sharply defined, jitter-free output
74HC1G32-Q100; 74HCT1G32-Q100
Rev. 1 8 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G32-Q100 and 74HCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input
74HC1G02-Q100; 74HCT1G02-Q100
Rev. 1 7 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G02-Q100 and 74HCT1G02-Q100 are high speed Si-gate CMOS devices. They provide a 2-input
Low-power configurable multiple function gate
Rev. 8 23 September 2015 Product data sheet 1. General description The provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the
74LVC594A-Q bit shift register with output register
Rev. 1 15 November 2013 Product data sheet 1. General description The is an 8-bit serial-in/serial or parallel-out shift register with a storage register. Separate clock and reset inputs are provided on
2-input EXCLUSIVE-OR gate
Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output
2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.
74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function
74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate
Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current
HEF4024B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. 7-stage binary counter
Rev. 7 18 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master
The 74LV08 provides a quad 2-input AND function.
Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0
HEF40175B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Quad D-type flip-flop
Rev. 8 2 November 20 Product data sheet. General description 2. Features and benefits 3. pplications The is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP),
Dual inverting Schmitt trigger with 5 V tolerant input
Rev. 10 15 December 2016 Product data sheet 1. General description The provides two inverting buffers with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply
Low-power triple buffer with open-drain output
Rev. 2 5 October 2016 Product data sheet 1. General description The is a triple non-inverting buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain
74AHC1G00; 74AHCT1G00
74HC1G00; 74HCT1G00 Rev. 06 30 May 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G00 and 74HCT1G00 are high-speed Si-gate CMOS devices. They provide a 2-input
Octal bus transceiver; 3-state
Rev. 2 3 November 2016 Product data sheet 1. General description The is an 8-bit transceiver with 3-state outputs. The device features an output enable (OE) and send/receive (DIR) for direction control.
74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.
Rev. 02 5 November 2007 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
74HC139; 74HCT139. Dual 2-to-4 line decoder/demultiplexer
Rev. 3 28 March 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes two binary weighted address inputs (n0, n1) to four mutually exclusive outputs
74AHC14-Q100; 74AHCT14-Q100
Rev. 9 July 202 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.
Rev. 3 16 August 2013 Product data sheet 1. General description The is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.
Triple inverting Schmitt trigger with 5 V tolerant input
Rev. 14 15 December 2016 Product data sheet 1. General description The provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply
The 74LVC10A provides three 3-input NAND functions.
Triple 3-input NND gate Rev. 5 7 November 20 Product data sheet. General description The provides three 3-input NND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows
Dual buffer/line driver; 3-state
Rev. 14 15 December 2016 Product data sheet 1. General description The is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE
74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.
Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
74HC166-Q100; 74HCT166-Q100
Rev. 1 25 September 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit serial or parallel-in/serial-out shift register. The device features
74AHC14; 74AHCT14. Hex inverting Schmitt trigger
Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
The 74LV32 provides a quad 2-input OR function.
Rev. 03 9 November 2007 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32.