NL17SZ125. Non-Inverting 3-State Buffer. The NL17SZ125 is a high performance non inverting buffer operating from a 1.65 V to 5.5 V supply.

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Non-Inverting 3-State Buffer The N7SZ is a high performance non inverting buffer operating from a.6 to. supply. Features Extremely High Speed: t PD.6 ns (typical) at =.0 Designed for.6 to. Operation Overvoltage Tolerant Inputs and Outputs TT Compatible Interface Capability With.

1 Non-Inverting 3-State Buffer The N7SZ is a high performance non inverting buffer operating from a.6 to. supply. Features Extremely High Speed: t PD.6 ns (typical) at =.0 Designed for.6 to. Operation Overvoltage Tolerant Inputs and Outputs TT Compatible Interface Capability With.0 TT ogic with = CMOS Compatible m Balanced Output Sink and Source Capability Near Zero Static Supply Current Substantially Reduces System Power Requirements 3 State Input is ctive ow Replacement for NC7SZ Chip Complexity = 36 FETs N Prefix for utomotive and Other pplications Requiring Unique Site and Control Change Requirements; EC Q00 Qualified and PPP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant IN EN SC 88 (SOT 33) DF SUFFIX CSE 9 SOT 3 X SUFFIX CSE 63B TSOP DT SUFFIX CSE 83 MRKING DIGRMS M M0 M M0 M M0 M Figure. ogic Symbol UDFN6.0 x.0 CSE 7BX Y M SOT 93 CSE 7E F M M0 or F = Specific Device Code (F with 90 degree clockwise rotation) M = Date Code = Pb Free Package (*Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Semiconductor Components Industries, C, 03 June, 03 Rev. Publication Order Number: N7SZ/D

2 IN 6 IN IN NC (SOT 33/TSOP /SC 88/ SOT 3) SOT 93 Figure. Pinout (Top iew) UDFN6 PIN SSIGNMENT (SOT 33/ TSOP /SC 88/SOT 3) PIN SSIGNMENT (SOT 93) PIN SSIGNMENT (UDFN) Pin Function Pin Function IN Pin Function IN IN NC 6 FUNCTION TBE Input H X = Don t Care H X Output Y H Z

3 MXIMUM RTINGS Symbol Parameter alue Units DC Supply oltage 0. to +7.0 IN DC Input oltage 0. to +7.0 OUT DC Output oltage (SOT 33/TSOP /SC 88/SOT 3/UDFN Packages) 0. to +0. OUT DC Output oltage Output at High or ow State (SOT 93 Package) Power Down Mode ( = 0 ) 0. to to +0. I IK DC Input Diode Current 0 m I OK DC Output Diode Current OUT <, OUT > (SOT 33/TSOP /SC 88/SOT 3/UDFN Packages) ±0 m I OK DC Output Diode Current (SOT 93 Package) OUT < 0 m I OUT DC Output Sink Current ±0 m I CC DC Supply Current per Supply Pin ±00 m T STG Storage Temperature Range 6 to +0 C T ead Temperature, mm from Case for 0 Seconds 60 C T J Junction Temperature Under Bias +0 C J Thermal Resistance (Note ) SC 88/SOT 3 TSOP C/W P D Power Dissipation in Still ir at 8 C 0 mw MS Moisture Sensitivity evel F R Flammability Rating Oxygen Index: 8 to 3 U 9 0. in ESD ESD Withstand oltage Human Body Model (Note ) Machine Model (Note 3) Charged Device Model (Note ) N/ I TCHUP atchup Performance bove and Below at C (Note ) ±00 m Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Measured with minimum pad spacing on an FR board, using 0 mm by inch, ounce copper trace with no air flow.. Tested to EI/JESD. 3. Tested to EI/JESD.. Tested to JESD C0.. Tested to EI/JESD78. 3

4 RECOMMENDED OPERTING CONDITIONS Symbol Parameter Min Max Units DC Supply oltage.6. IN DC Input oltage 0. OUT DC Output oltage (SOT 33/TSOP /SC 88/SOT 3/UDFN Packages) 0. OUT DC Output oltage (SOT 93 Package) 0 T Operating Temperature Range + C t r, t f Input Rise and Fall Time =.8 ±0. =. ±0. = ±0.3 =.0 ± ns/ DEICE JUNCTION TEMPERTURE ERSUS TIME TO 0.% BOND FIURES Junction Temperature C Time, Hours Time, Years 80,03, , , , , , ,900.0 NORMIZED FIURE RTE FIURE RTE OF PSTIC = CERMIC UNTI INTERMETICS OCCUR T J = 30 C T J = 0 C T J = 0 C T J = 00 C TIME, YERS Figure 3. Failure Rate vs. Time Junction Temperature T J = 90 C T J = 80 C DC EECTRIC CHRCTERISTICS Symbol Parameter () T = C C T C Min Typ Max Min Max Units Condition IH High evel Input oltage.6 to.9 to I ow evel Input oltage.6 to.9 to OH High evel Output oltage IN = IH I OH = I OH = m I OH = 8 m I OH = 6 m I OH = m I OH = 3 m O ow evel Output oltage IN = I I O = I O = m I O = 8 m I O = 6 m I O = m I O = 3 m

5 DC EECTRIC CHRCTERISTICS Symbol Parameter () Min T = C Typ Max C T C Min Max Units Condition I IN Input eakage Current 0 to. ±0. ±.0 IN =. or I OZ 3 State Output eakage.6 to. ±0. ±.0 IN = IH or I 0 OUT. I OFF I CC Power Off eakage Current (SOT 33/ TSOP /SC 88/ SOT 3/ UDFN Packages) Quiescent Supply Current IN =. or OUT = IN =. or C EECTRIC CHRCTERISTICS (t R = t F = ns) Symbol Parameter Condition t PH t PH Propagation Delay N to YN (Figures and, Table ) () T = C C T C Min Typ Max Min Max R = M C = pf.8 ± ns R = M C = pf. ± R = M R = 00 C = pf C = 0 pf 3.3 ± Units t PZH t PZ t PHZ t PZ Output Enable Time (Figures 6, 7and 8, Table ) Output Disable Time (Figures 6, 7and 8, Table ) R = M R = 00 C = pf C = 0 pf.0 ± R = 0 C = 0 pf.8 ± ns ± ± ± R and R = 00 C = 0 pf.8 ± ns. ± ± ± CPCITIE CHRCTERISTICS Symbol Parameter Condition Typical Units C IN Input Capacitance =., I = 0 or. pf C OUT Output Capacitance =., I = 0 or. pf C PD Power Dissipation Capacitance (Note 6) 0 MHz, = 3.3, I = 0 or 9 0 MHz, =., I = 0 or pf 6. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. verage operating current can be obtained by the equation: I CC(OPR) = C PD f in + I CC. C PD is used to determine the no load dynamic power consumption; P D = C PD f in + I CC.

6 = t PH 0% t PH INPUT C * R OUTPUT 0% Y Figure. Switching Waveform *Includes all probe and jig capacitance. MHz square input wave is recommended for propagation delay tests. Figure. t PH or t PH INPUT R = 00 INPUT OUTPUT OUTPUT C = 0 pf R = 00 C = 0 pf R = 0 MHz square input wave is recommended for propagation delay tests. Figure 6. t PZ or t PZ MHz square input wave is recommended for propagation delay tests. Figure 7. t PZH or t PHZ.7 mi mi 0 t PZH t PHZ On mo OH t PZ t PZ On mo O Figure 8. C Output Enable and Disable Waveform Table. OUTPUT ENBE ND DISBE TIMES t R = t F =. ns, 0% to 90%; f = MHz; t W = 00 ns Symbol mi.. / mo.. / 6

7 DEICE ORDERING INFORMTION N7SZDFTG Device Package Shipping SC 88 (SOT 33) (Pb Free) 3000 / Tape & Reel N7SZDFTG* N7SZXTG N7SZDTTG SC 88 (SOT 33) (Pb Free) SOT 3 (Pb Free) TSOP (Pb Free) 3000 / Tape & Reel 000 / Tape & Reel 3000 / Tape & Reel N7SZCMUTCG UDFN6,.0 x.0 x 0.3P (Pb Free) 3000 / Tape & Reel N7SZPTG SOT 93 (Pb Free) 8000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *N Prefix for utomotive and Other pplications Requiring Unique Site and Control Change Requirements; EC Q00 Qualified and PPP Capable. 7

8 PCKGE DIMENSIONS SC 88 (SC 70 /SOT 33) CSE 9 0 ISSUE S G B 3 D P 0. (0.008) M B M N NOTES:. DIMENSIONING ND TOERNCING PER NSI Y.M, 98.. CONTROING DIMENSION: INCH OBSOETE. NEW STNDRD DIMENSIONS ND B DO NOT INCUDE MOD FSH, PROTRUSIONS, OR GTE BURRS. INCHES MIIMETERS DIM MIN MX MIN MX B C D G 0.06 BSC 0.6 BSC H J K N REF 0.0 REF S C J H K SODER FOOTPRINT* SCE 0: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. 8

9 PCKGE DIMENSIONS SOT 3, ED CSE 63B ISSUE B D X 3 e E Y b P 0.08 (0.003) M X Y H E c NOTES:. DIMENSIONING ND TOERNCING PER NSI Y.M, 98.. CONTROING DIMENSION: MIIMETERS 3. MXIMUM ED THICKNESS INCUDES ED FINISH THICKNESS. MINIMUM ED THICKNESS IS THE MINIMUM THICKNESS OF BSE MTERI. MIIMETERS INCHES DIM MIN NOM MX MIN NOM MX b c D E e 0.0 BSC 0.00 BSC H E SODERING FOOTPRINT* SCE 0: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. 9

10 PCKGE DIMENSIONS TSOP CSE 83 0 ISSUE H X X NOTE 0.0 T 0.0 T H G B C D X 0.0 C B T S SETING PNE J K DETI Z SODERING FOOTPRINT* M DETI Z NOTES:. DIMENSIONING ND TOERNCING PER SME Y.M, 99.. CONTROING DIMENSION: MIIMETERS. 3. MXIMUM ED THICKNESS INCUDES ED FINISH THICKNESS. MINIMUM ED THICKNESS IS THE MINIMUM THICKNESS OF BSE MTERI.. DIMENSIONS ND B DO NOT INCUDE MOD FSH, PROTRUSIONS, OR GTE BURRS.. OPTION CONSTRUCTION: N DDITION TRIMMED ED IS OWED IN THIS OCTION. TRIMMED ED NOT TO EXTEND MORE THN 0. FROM BODY. MIIMETERS DIM MIN MX 0 BSC B.0 BSC C D G 0.9 BSC H J K M 0 0 S SCE 0: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. 0

11 PCKGE DIMENSIONS PIN ONE REFERENCE X X 0.08 C 0.08 C 0.0 C 0.0 C ÉÉÉ e DETI D TOP IEW DETI B SIDE IEW 3 B E 3 6X C SETING PNE UDFN6, x, 0.3P CSE 7BX ISSUE O 3 DETI TERNTE TERMIN CONSTRUCTION EXPOSED Cu ÉÉ ÇÇ MOD CMPD DETI B TERNTE CONSTRUCTION 6X 0. NOTES:. DIMENSIONING ND TOERNCING PER SME Y.M, 99.. CONTROING DIMENSION: MIIMETERS. 3. DIMENSION b PPIES TO PTED TERMIN ND IS MESURED BETWEEN 0. ND 0.0 MM FROM TERMIN TIP.. PCKGE DIMENSIONS EXCUSIE OF BURRS ND MOD FSH. MIIMETERS DIM MIN MX REF b D.00 BSC E.00 BSC e RECOMMENDED SODERING FOOTPRINT* 6X BOTTOM IEW 6X b 0.07 M C B 0.0 M C NOTE 3 PCKGE OUTINE 0.3 PITCH DIMENSION: MIIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D.

12 PCKGE DIMENSIONS SOT 93 CSE 7E ISSUE E PIN ONE INDICTOR D 3 TOP IEW e X Y E X C SIDE IEW H E NOTES:. DIMENSIONING ND TOERNCING PER SME Y.M, 99.. CONTROING DIMENSION: MIIMETERS 3. MXIMUM ED THICKNESS INCUDES ED FINISH. MINIMUM ED THICKNESS IS THE MINIMUM THICKNESS OF THE BSE MTERI.. DIMENSIONS D ND E DO NOT INCUDE MOD FSH, PROTRUSIONS, OR GTE BURRS. MIIMETERS DIM MIN NOM MX b C D E e 0.3 BSC H E REF X 3 X SODERING FOOTPRINT* X b BOTTOM IEW 0.08 X Y PCKGE OUTINE.0 X 0.0 X PITCH DIMENSIONS: MIIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of SCIC s product/patent coverage may be accessed at Marking.pdf. SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICTION ORDERING INFORMTION ITERTURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 807 US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative N7SZ/D

NL17SZ02. 2-Input NOR Gate

NL17SZ02. 2-Input NOR Gate N7SZ0 -Input NOR Gate The N7SZ0 is a single input NOR Gate in three tiny footprint packages. The device performs much as CX multi gate products in speed and drive. Features Tiny SOT, SOT and SOT 9 Packages.