Features Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
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1 CD4025 CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors They have equal source and sink current capabilities and conform to standard B series output drive The devices also have buffered outputs which improve transfer characteristics by providing very high gain All inputs are protected against static discharge with diodes to V DD and V SS Connection Diagrams CD4023BM CD4023BC Dual-In-Line Package Features Y Wide supply voltage range 3 0V to 15V Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L compatibility or 1 driving 74LS Y 5V 10V 15V parametric ratings Y Symmetrical output characteristics Y Maximum input leakage 1 ma at 15V over full temperature range CD4025BM CD4025BC Dual-In-Line Package CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate Top View TL F Top View TL F Order Number CD4023B or CD4025B
2 Absolute Maximum Ratings (Notes1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications DC Supply Voltage (V DD ) b0 5 V DC to a18 V DC Input Voltage (V IN ) b0 5 V DC to V DD a0 5 V DC Storage Temp Range (T S ) b65 Ctoa150 C Power Dissipation (P D ) Dual-In-Line 700 mw Small Outline 500 mw Lead Temperature (T L ) (Soldering 10 seconds) 260 C Recommended Operating Conditions DC Supply Voltage (V DD ) Input Voltage (V IN ) Operating Temperature Range (T A ) CD4023BM CD4025BM CD4023BC CD4025BC 5V DC to 15 V DC 0V DC to V DD V DC b55 Ctoa125 C b40 Ctoa85 C DC Electrical Characteristics CD4023BM CD4025BM (Note 2) Symbol Parameter Conditions b55 C a25 C a125 C Min Typ Min Typ Max Min Max I DD Quiescent Device Current V DD e 5V ma V DD e 10V ma V DD e 15V ma V OL Low Level Output Voltage V DD e 5V V V DD e 10V V V DD e 15V V V OH High Level Output Voltage V DD e 5V V V DD e 10V V V DD e 15V V V IL Low Level Input Voltage V DD e5v V O e4 5V V V DD e10v V O e9 0V li Ol k 1mA V V DD e15v V O e13 5V( V V IH High Level Input Voltage V DD e5v V O e0 5V V V DD e10v V O e1 0V li Ol k 1mA V V DD e15v V O e1 5V( V I OL Low Level Output Current V DD e5v V O e 0 4V ma (Note 3) V DD e 10V V O e 0 5V ma V DD e 15V V O e 1 5V ma I OH High Level Output Current V DD e 5V V O e 4 6V b0 64 b0 51 b0 88 b0 36 ma (Note 3) V DD e 10V V O e 9 5V b1 6 b1 3 b2 2 b0 90 ma V DD e 15V V O e 13 5V b4 2 b3 4 b8 b2 4 ma I IN Input Current V DD e 15V V IN e 0V b0 10 b10b5 b0 10 b1 0 ma V DD e 15V V IN e 15V b ma Units Schematic Diagram CD4023BC CD4023BM Device Shown All Inputs Protected by Standard CMOS Input Protection Circuit TL F
3 DC Electrical Characteristics CD4023BC CD4025BC (Note 2) Symbol Parameter Conditions b40 C a25 C a85 C Min Typ Min Typ Max Min Max I DD Quiescent Device Current V DD e 5V ma V DD e 10V ma V DD e 15V ma V OL Low Level Output Voltage V DD e 5V V V DD e 10V V V DD e 15V V V OH High Level Output Voltage V DD e 5V V V DD e 10V V V DD e 15V V V IL Low Level Input Voltage V DD e5v V O e4 5V V V DD e10v V O e9 0V li Ol k 1mA V V DD e15v V O e13 5V( V V IH High Level Input Voltage V DD e5v V O e0 5V V V DD e10v V O e1 0V li Ol k 1mA V V DD e15v V O e1 5V( V I OL Low Level Output Current V DD e5v V O e 0 4V ma (Note 3) V DD e 10V V O e 0 5V ma V DD e 15V V O e 1 5V ma I OH High Level Output Current V DD e 5V V O e 4 6V b0 52 b0 44 b0 88 b0 36 ma (Note 3) V DD e 10V V O e 9 5V b1 3 b1 1 b2 2 b0 90 ma V DD e 15V V O e 13 5V b3 6 b3 0 b8 b2 4 ma I IN Input Current V DD e 15V V IN e 0V b0 3 b10b5 b0 3 b1 0 ma V DD e 15V V IN e 15V b ma Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The table of Recommended Operating Conditions and Electrical Characteristics provides conditions for actual device operation Note 2 V SS e 0V unless otherwise specified Note 3 I OH and I OL are tested one output at a time Schematic Diagram CD4025BM CD4025BC Units Device Shown All Inputs Protected by Standard CMOS Input Protection Circuit TL F
4 AC Electrical Characteristics T A e 25 C C L e 50 pf R L e 200k unless otherwise specified CD4023BC CD4025BC Symbol Parameter Conditions CD4023BM CD4025BM Units Min Typ Max Min Typ Max t PHL Propagation Delay High-to-Low Level V DD e 5V ns V DD e 10V ns V DD e 15V ns t PLH Propagation Delay Low-to-High Level V DD e 5V ns V DD e 10V ns V DD e 15V ns t THL Transition Time V DD e 5V ns t TLH V DD e 10V ns V DD e 15V ns C IN Average Input Capacitance Any Input pf C PD Power Dissipation Capacity (Note 4) Any Gate pf AC Parameters are guaranteed by DC correlated testing Note 4 C PD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90 4
5 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4023BMJ CD4023BCJ CD4025BMJ or CD4025BCJ NS Package Number J14A 5
6 CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number CD4023BMN CD4023BCN CD4025BMN or CD4025BCN NS Package Number N14A
Features. Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
Features. Y Low power TTL Fan out of 2 driving 74L. Y 5V 10V 15V parametric ratings. Y Symmetrical output characteristics
CD4001BM CD4001BC Quad 2-Input NOR Buffered B Series Gate CD4011BM CD4011BC Quad 2-Input NAND Buffered B Series Gate General Description These quad gates are monolithic complementary MOS (CMOS) integrated
Features. Y Low power TTL Fan out of 2 driving 74L. Y 5V 10V 15V parametric ratings. Y Symmetrical output characteristics
CD4071BM CD4071BC Quad 2-Input OR Buffered B Series Gate CD4081BM CD4081BC Quad 2-Input AND Buffered B Series Gate General Description These quad gates are monolithic complementary MOS (CMOS) integrated
Features. Y Low power TTL Fan out of 2 driving 74L. Y 5V 10V 15V parametric ratings. Y Symmetrical output characteristics
CD4001BM CD4001BC Quad 2-Input NOR Buffered B Series Gate CD4011BM CD4011BC Quad 2-Input NAND Buffered B Series Gate General Description These quad gates are monolithic complementary MOS (CMOS) integrated
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-
Features. Y Wide supply voltage range 3V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL compatibility Fan out of 2
CD40192BM CD40192BC Synchronous 4-Bit Up Down Decade Counter CD40193BM CD40193BC Synchronous 4-Bit Up Down Binary Counter General Description These up down counters are monolithic complementary MOS (CMOS)
CD4070BM CD4070BC Quad 2-Input EXCLUSIVE-OR Gate CD4077BM CD4077BC Quad 2-Input EXCLUSIVE-NOR Gate
CD4070BM CD4070BC Quad 2-Input EXCLUSIVE-OR Gate CD4077BM CD4077BC Quad 2-Input EXCLUSIVE-NOR Gate General Description Employing complementary MOS (CMOS) transistors to achieve wide power supply operating
Features. Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD40160BM CD40160BC Decade Counter with Asynchronous Clear CD40161BM CD40161BC Binary Counter with Asynchronous Clear CD40162BM CD40162BC Decade Counter with Synchronous Clear CD40163BM CD40163BC Binary
CD4070BM CD4070BC Quad 2-Input EXCLUSIVE-OR Gate CD4077BM CD4077BC Quad 2-Input EXCLUSIVE-NOR Gate
CD4070BM CD4070BC Quad 2-Input EXCLUSIVE-OR Gate CD4077BM CD4077BC Quad 2-Input EXCLUSIVE-NOR Gate General Description Employing complementary MOS (CMOS) transistors to achieve wide power supply operating
CD4013BM CD4013BC Dual D Flip-Flop
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CD4029BM CD4029BC Presettable Binary Decade Up Down Counter
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CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed
CD4028BM CD4028BC BCD-to-Decimal Decoder
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CD4723BM CD4723BC Dual 4-Bit Addressable Latch CD4724BM CD4724BC 8-Bit Addressable Latch
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CD4093BM CD4093BC Quad 2-Input NAND Schmitt Trigger
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CD40106BC Hex Schmitt Trigger
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CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
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CD4093BM CD4093BC Quad 2-Input NAND Schmitt Trigger
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CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset
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CD4021BC 8-Stage Static Shift Register
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MM54HC148 MM74HC Line Priority Encoder
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MM74HC175 Quad D-Type Flip-Flop With Clear
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