MC10E131, MC100E131. 5VНECL 4-Bit D Flip-Flop

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1 5VНECL 4-Bit Flip-Flop escription The MC10E/100E131 is a quad master-slave -type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (C C ) LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE inputs LOW and using C C to clock all four flip-flops. In this case, the CE inputs perform the function of controlling the common clock, to each flip-flop. Individual asynchronous resets are provided (). Asynchronous set controls () are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry. ata enters the master when both C C and CE are LOW, and transfers to the slave when either C C or CE (or both) go HIGH. The 100 eries contains temperature compensation. Features 1100 MHz Min. Toggle Frequency ifferential Outputs Individual and Common Clocks Individual esets (asynchronous) Paired ets (asynchronous) PECL Mode Operating ange: V CC = 4.2 V to 5.7 V with V EE = 0 V NECL Mode Operating ange: V CC = 0 V with V EE = 4.2 V to 5.7 V Metastability Time Constant is 200 ps. Internal Input 50 k Pulldown esistors E Protection: Human Body Model; > 2 kv, Machine Model; > 200 V Meets or Exceeds JEEC pec EIA/JE78 IC Latchup Test Moisture ensitivity Level: Pb = 1 Pb Free = 3 For Additional Information, see Application Note AN8003/ Flammability ating: UL 94 V in, Oxygen Index: 28 to 34 Transistor Count = 240 devices Pb Free Packages are Available* FN UFFIX CAE 776 MAKING IAGAM* MCxxxE131G AWLYYWW xxx = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb Free Package *For additional marking information, refer to Application Note AN8002/. OEING INFOMATION ee detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. 1 *For additional information on our Pb Free strategy and soldering details, please download the ON emiconductor oldering and Mounting Techniques eference Manual, OLEM/. emiconductor Components Industries, LLC, 2006 November, 2006 ev Publication Order Number: MC10E131/

2 CE 2 2 V CCO 3 3 CE CE CE V EE 28 1 Pinout: 28-Lead PLCC (Top View) V CC 1 2 C C C C 1 CE CE CE 1 1 NC V CCO CE 0 0 * All V CC and V CCO pins are tied together on the die. Warning: All V CC, V CCO, and V EE pins must be externally connected to Power upply to guarantee proper operation. 0 0 Figure 1. Pinout iagram Figure 2. Logic iagram Table 1. PIN ECIPTION PIN 0 3 CE 0 CE C C 03, , 0 3 V CC, V CCO V EE NC ECL ata Inputs ECL Clock Enables (Individual) ECL esets ECL Common Clock ECL ets (paired) ECL ifferential Outputs Positive upply Negative upply No Connect FUNCTION 2

3 Table 2. MAXIMUM ATING Parameter Condition 1 Condition 2 ating Unit V CC PECL Mode Power upply V EE = 0 V 8 V V EE NECL Mode Power upply V CC = 0 V 8 V V I PECL Mode Input Voltage NECL Mode Input Voltage V EE = 0 V V CC = 0 V I out Output Current Continuous urge V I V CC 6 V I V EE 6 T A Operating Temperature ange 0 to +85 C T stg torage Temperature ange 65 to + C JA Thermal esistance (Junction to Ambient) 0 lfpm 500 lfpm JC Thermal esistance (Junction to Case) tandard Board 22 to 26 C/W T sol Wave older Pb Pb Free tresses exceeding Maximum atings may damage the device. Maximum atings are stress ratings only. Functional operation above the ecommended Operating Conditions is not implied. Extended exposure to stresses above the ecommended Operating Conditions may affect device reliability V V ma ma C/W C/W C Table 3. 10E EIE PECL C CHAACTEITIC V CCx = 5.0 V; V EE = 0.0 V (Note 1) 40 C 0 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max Min Typ Max I EE Power upply Current ma V OH Output HIGH Voltage (Note 2) mv V OL Output LOW Voltage (Note 2) mv V IH Input HIGH Voltage mv V IL Input LOW Voltage mv I IH Input HIGH Current C C, CE I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 1. Input and output parameters vary 1:1 with V CC. V EE can vary 0.46 V / V. 2. Outputs are terminated through a 50 resistor to V CC 2.0 V. Unit A 3

4 Table 4. 10E EIE NECL C CHAACTEITIC V CCx = 0.0 V; V EE = 5.0 V (Note 3) I EE V OH V OL Power upply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) 40 C 0 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit ma mv mv V IH Input HIGH Voltage mv V IL Input LOW Voltage mv I IH Input HIGH Current C C, CE I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 3. Input and output parameters vary 1:1 with V CC. V EE can vary 0.46 V / V. 4. Outputs are terminated through a 50 resistor to V CC 2.0 V. A Table E EIE PECL C CHAACTEITIC V CCx = 5.0 V; V EE = 0.0 V (Note 5) 40 C 0 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max Min Typ Max I EE Power upply Current ma V OH V OL Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Unit mv mv V IH Input HIGH Voltage mv V IL Input LOW Voltage mv I IH Input HIGH Current C C, CE I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 5. Input and output parameters vary 1:1 with V CC. V EE can vary 0.46 V / +0.8 V. 6. Outputs are terminated through a 50 resistor to V CC 2.0 V. A 4

5 Table E EIE NECL C CHAACTEITIC V CCx = 0.0 V; V EE = 5.0 V (Note 7) 40 C 0 C 25 C 85 C I EE V OH V OL V IH V IL I IH I IL Power upply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage Input LOW Voltage Input HIGH Current C C, CE Input LOW Current Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit ma mv mv mv mv A A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 7. Input and output parameters vary 1:1 with V CC. V EE can vary 0.46 V / +0.8 V. 8. Outputs are terminated through a 50 resistor to V CC 2.0 V. Table 7. AC CHAACTEITIC V CCx = 5.0 V; V EE = 0.0 V or V CCx = 0.0 V; V EE = 5.0 V (Note 7) 40 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max f MAX Maximum Toggle Frequency MHz t PLH Propagation elay to Output CE t PHL C C t etup Time (Note 10) ps t H Hold Time (Note 10) ps t eset ecovery Time ps t PW Minimum Pulse Width CLK, t KEW Within-evice kew (Note 11) ps t JITTE andom Clock Jitter < 1 < 1 < 1 ps t r /t f ise/fall Time (20 80%) ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit eries: V EE can vary 0.46 V / V. 100 eries: V EE can vary 0.46 V / +0.8 V. 10.etup/hold times guaranteed for both C C and CE. 11. Within-device skew is defined as identical transitions on similar paths through a device Unit ps ps 5

6 river evice Z o = 50 Z o = 50 eceiver evice V TT V TT = V CC 2.0 V Figure 3. Typical Termination for Output river and evice Evaluation (ee Application Note AN8020/ Termination of ECL Logic evices.) OEING INFOMATION evice Package hipping MC10E131FN 37 Units / ail MC10E131FNG (Pb Free) 37 Units / ail MC10E131FN2 500 / Tape & eel MC10E131FN2G (Pb Free) 500 / Tape & eel MC100E131FN 37 Units / ail MC100E131FNG (Pb Free) 37 Units / ail MC100E131FN2 500 / Tape & eel MC100E131FN2G (Pb Free) 500 / Tape & eel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and eel Packaging pecifications Brochure, B8011/. esource eference of Application Notes AN1405/ ECL Clock istribution Techniques AN1406/ esigning with PECL (ECL at +5.0 V) AN3/ ECLinP I/O PiCE Modeling Kit AN4/ Metastability and the ECLinP Family AN1568/ Interfacing Between LV and ECL AN1672/ The ECL Translator Guide AN8001/ Odd Number Counters esign AN8002/ Marking and ate Codes AN8020/ Termination of ECL Logic evices AN8066/ Interfacing with ECLinP AN8090/ AC s of ECL evices 6

7 PACKAGE IMENION FN UFFIX PLATIC PLCC PACKAGE CAE IUE E N Y BK B U L M Z 28 1 V W X VIEW G (0.250) T L M N Z A H C E K1 G G1 J VIEW (0.100) T EATING PLANE K F (0.250) T L M N VIEW NOTE: 1. ATUM L, M, AN N ETEMINE WHEE TOP OF LEA HOULE EXIT PLATIC BOY AT MOL PATING LINE. 2. IMENION G1, TUE POITION TO BE MEAUE AT ATUM T, EATING PLANE. 3. IMENION AN U O NOT INCLUE MOL FLAH. ALLOWABLE MOL FLAH I (0.250) PE IE. 4. IMENIONING AN TOLEANCING PE ANI Y14.5M, CONTOLLING IMENION: INCH. 6. THE PACKAGE TOP MAY BE MALLE THAN THE PACKAGE BOTTOM BY UP TO (0.). IMENION AN U AE ETEMINE AT THE OUTEMOT EXTEME OF THE PLATIC BOY EXCLUIVE OF MOL FLAH, TIE BA BU, GATE BU AN INTELEA FLAH, BUT INCLUING ANY MIMATCH BETWEEN THE TOP AN BOTTOM OF THE PLATIC BOY. 7. IMENION H OE NOT INCLUE AMBA POTUION O INTUION. THE AMBA POTUION() HALL NOT CAUE THE H IMENION TO BE GEATE THAN (0.940). THE AMBA INTUION() HALL NOT CAUE THE H IMENION TO BE MALLE THAN (0.635). INCHE MILLIMETE IM MIN MAX MIN MAX A B C E F G BC 1.27 BC H J K U V W X Y Z G K

8 ECLinP is a trademark of emiconductor Components Industries, LLC (CILLC). ON emiconductor and are registered trademarks of emiconductor Components Industries, LLC (CILLC). CILLC reserves the right to make changes without further notice to any products herein. CILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does CILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in CILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. CILLC does not convey any license under its patent rights nor the rights of others. CILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the CILLC product could create a situation where personal injury or death may occur. hould Buyer purchase or use CILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold CILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that CILLC was negligent regarding the design or manufacture of the part. CILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION OEING INFOMATION LITEATUE FULFILLMENT: Literature istribution Center for ON emiconductor P.O. Box 5163, enver, Colorado UA Phone: or Toll Free UA/Canada Fax: or Toll Free UA/Canada orderlit@onsemi.com N. American Technical upport: Toll Free UA/Canada Europe, Middle East and Africa Technical upport: Phone: Japan Customer Focus Center Phone: ON emiconductor Website: Order Literature: For additional information, please contact your local ales epresentative MC10E131/

MC10E171, MC100E171. 5VНECL 3-Bit 4:1 Multiplexer

MC10E171, MC100E171. 5VНECL 3-Bit 4:1 Multiplexer 5VНECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading pairs (see logic symbol). The