MC14008B. 4 Bit Full Adder

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1 4 Bi Full Adder The MC4008B 4 bi full adder is consruced wih MOS P Channel and N Channel enhancemen mode devices in a single monolihic srucure. This device consiss of four full adders wih fas inernal look ahead carry oupu. I is useful in binary addiion and oher arihmeic applicaions. The fas parallel carry oupu bi allows high speed operaion when used wih oher adders in a sysem. Feaures Look Ahead Carry Oupu Diode Proecion on All Inpus All Oupus Buffered Supply Volage Range = 3.0 Vdc o 8 Vdc Capable of Driving Two Low Power TTL Loads or One Low Power Schoky TTL Load Over he Raed Temperaure Range Pin for Pin Replacemen for CD4008B Pb Free Packages are Available* MAXIMUM RATINGS (Volages Referenced o V SS ) Symbol Parameer Value Uni DC Supply Volage Range 0.5 o +8.0 V V in, V ou Inpu or Oupu Volage Range (DC or Transien) 0.5 o V I in, I ou P D Inpu or Oupu Curren (DC or Transien) per Pin Power Dissipaion, per Package (Noe ) ±0 ma 500 mw T A Ambien Temperaure Range 55 o +25 C T sg Sorage Temperaure Range 65 o +50 C T L Lead Temperaure (8 Second Soldering) 260 C Maximum raings are hose values beyond which device damage can occur. Maximum raings applied o he device are individual sress limi values (no normal operaing condiions) and are no valid simulaneously. If hese limis are exceeded, device funcional operaion is no implied, damage may occur and reliabiliy may be affeced.. Temperaure Deraing: Plasic P and D/DW Packages: 7.0 mw/ C From 65 C To 25 C A WL, L YY, Y WW, W PDIP P SUFFIX CASE 648 SOIC D SUFFIX CASE 75B MARKING DIAGRAMS MC4008BCP AWLYYWW 4008B AWLYWW = Assembly Locaion = Wafer Lo = Year = Work Week ORDERING INFORMATION See deailed ordering and shipping informaion in he package dimensions secion on page 2 of his daa shee. This device conains proecion circuiry o guard agains damage due o high saic volages or elecric fields. However, precauions mus be aken o avoid applicaions of any volage higher han maximum raed volages o his high impedance circui. For proper operaion, V in and V ou should be consrained o he range V SS (V in or V ou ). Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher V SS or ). Unused oupus mus be lef open. *For addiional informaion on our Pb Free sraegy and soldering deails, please download he ON Semiconducor Soldering and Mouning Techniques Reference Manual, SOLDERRM/D. Semiconducor Componens Indusries, LLC, 2005 February, 2005 Rev. 5 Publicaion Order Number: MC4008B/D

2 PIN ASSIGNMENT C ou B2 4 3 S4 5 2 S3 B 6 S2 7 0 S V SS 8 9 TRUTH TABLE (One Sage) B A C ou S BLOCK DIAGRAM HIGH SPEED PARALLEL CARRY 4МC ou B2 4 5 B ADDER 4 C4 ADDER 3 C3 ADDER 2 C2 ADDER 3МS4 2МS3 МS2 0МS = PIN V SS = PIN 8 ORDERING INFORMATION Device Package Shipping MC405BCP PDIP 500 Unis / Rail MC405BCPG PDIP 500 Unis / Rail (Pb Free) MC405BDR2 SOIC 2500 Unis / Tape & Reel MC405BDR2G SOIC (Pb Free) 2500 Unis / Tape & Reel For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD80/D. 2

3 ELECTRICAL CHARACTERISTICS (Volages Referenced o V SS ) Î 55 C 25 C ÎÎ 25 C Î Characerisic Î Symbol Vdc Min MaxÎ Min Typ Î Max Min Max Uni (Noe 2) Oupu Volage 0 Level V Î V in = Î OL Vdc ÎÎ or Î 0 Î Î V in = 0 or LevelÎ V OH Î Î 4.95 Vdc Î Inpu Volage 0 Level V IL ÎÎ Vdc Î (V O = 4.5 or 0.5 Vdc) 5.0.5Î 2.25Î.5.5 (V Î O = 9.0 or.0 Vdc) (V O = 3.5 or.5 Vdc) 5 4.0Î 6.75Î Î (V O Î = 0.5 or 4.5 Vdc) Level V IH 5.0 Î (V O =.0 or 9.0 Vdc) Î 3.5 Î Î 7.0 Vdc (V O =.5 or 3.5 Vdc) Oupu Drive Curren I Î (V OH = 2.5 Vdc) Source Î OH madc Î Î.7 Î (V OH = 4.6 Vdc) Î Î 0.36 (V Î OH = 9.5 Vdc) (V OH = 3.5 Vdc) Î Î 2.4 Î (V OL = 0.4 Vdc) Sink Î I OL Î (V OL = 0.5 Vdc) Î 0.36 Î Î 0.9 madc (V OL =.5 Vdc) ÎÎ Î Inpu Curren I in 5 ± 0. ± ± 0. ±.0 Adc Inpu Capaciance C Î (V in = 0) Î in Î Î Î pf Î Quiescen Curren Î I DD 5.0 Î (Per Package) Î 5.0 0Î 0.00Î Adc Toal Supply Curren (Noes 3 & 4) I Î (Dynamic plus Quiescen, Î T 5.0 I 0 ÎÎ T = (.7 A/kHz) f + I DD Adc I T = (3.4 A/kHz) f + I DD Î Per Package) 5 ÎÎ I T = (5.0 A/kHz) f + I DD (C Î L = 50 pf on all oupus, all buffers swiching) 2. Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he IC s poenial performance. 3. The formulas given are for he ypical characerisics only a 25 C. 4. To calculae oal supply curren a loads oher han 50 pf: I T ( ) = I T (50 pf) + ( 50) Vfk where: I T is in A (per package), in pf, V = ( V SS ) in vols, f in khz is inpu frequency, and k =

4 SWITCHING CHARACTERISTICS (Noe 5) ( = 50 pf, T A = 25 C) Î V Characerisic Symbol DD Î Min Î Typ Î Max Vdc (Noe 6) Uni Oupu Rise and Fall Time Î TLH, ns Î Î Î TLH, THL = (.5 ns/pf) + 25 ns TLH, THL = (0.75 ns/pf) ns ÎÎ THL Î 0 Î Î 50 Î 00 TLH, THL = (0.55 ns/pf) ns ÎÎ 5 Î Î 40 Î 80 Propagaion Delay Time ÎÎ PLH, PHL Î Î Î ns Sum in o Sum Ou PLH, PHL = (.7 ns/pf) Î + 35 ns PLH, PHL = (0.66 ns/pf) + 27 ns ÎÎ 0 Î Î 0 Î 320 PLH, PHL = (0.5 ns/pf) + 90 ns ÎÎ 5 Î Î 5 Î 230 Sum In o Carry Ou PLH, PHL = (.7 ns/pf) ns ÎÎ 5.0 Î Î 305 Î 60 PLH, PHL = (0.66 ns/pf) + 2 ns ÎÎ 0 Î Î 45 Î 290 PLH, PHL = (0.5 ns/pf) + 85 ns Î Carry In o Sum Ou PLH, PHL = (.7 ns/pf) ns ÎÎ 5.0 Î Î 375 Î 750 PLH, PHL = (0.66 ns/pf) + 22 ns ÎÎ 0 Î Î 55 Î 30 PLH, PHL = (0.5 ns/pf) + 90 ns Carry In o Carry Ou Î PLH, PHL = (.7 ns/pf) + 85 ns ÎÎ 5.0 Î Î 70 Î 340 PLH, PHL = (0.66 ns/pf) + 42 ns ÎÎ Î PLH, PHL = (0.5 ns/pf) + 30 ns 5. The formulas given are for he ypical characerisics only a 25 C. 6. Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he IC s poenial performance = V GS V ou = V GS V ou S4 S3 B2 S2 B S I OH C ou 8 V SS POWER SUPPLY EXTERNAL B2 B S4 S3 S2 S C ou 8 V SS I OL EXTERNAL POWER SUPPLY Figure. Typical Source Curren Characerisics Tes Circui Figure 2. Typical Sink Curren Characerisics Tes Circui 4

5 20 ns 20 ns V in 90% 0% V SS PULSE GENERATOR B2 B S4 S3 S2 S C ou 8 V SS 500 F I DD Figure 3. Dynamic Power Dissipaion Tes Circui and Waveform PULSE GENERATOR B2 B S4 S3 S2 S C ou 8 V SS I DD 20 ns 20 ns S S4 C ou 90% 50% 0% 50% PHL 90% 50% 0% PLH THL V SS PLH V OH V OL TLH V OH V OL PHL Figure 4. Swiching Time Tes Circui and Waveforms 5

6 C ou S4 S3 B2 S2 B S Figure 5. Logic Diagram TYPICAL APPLICATION WORD A + B INPUTS CHIP CHIP CHIP CHIP C ou C ou C ou C ou S S4 S S4 S S4 S S4 SUM OUTPUTS Calculaion of bi adder speed: P oal = P (Sum o Carry) + P (Carry o Sum) + 2 P (Carry o Carry) The guaraneed bi adder speed a 0 V, 25 C, = 50 pf is: p oal = = 900 ns Figure 6. Using he MC4008B in a Bi Adder Configuraion 6

7 PACKAGE DIMENSIONS PDIP P SUFFIX PLASTIC DIP PACKAGE CASE ISSUE T A 8 9 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. H G F D PL S C K 0.25 (0.00) M T SEATING T PLANE A M J L M INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G 0.00 BSC 2.54 BSC H BSC.27 BSC J K L M S

8 PACKAGE DIMENSIONS SOIC D SUFFIX PLASTIC SOIC PACKAGE CASE 75B 05 ISSUE J A 9 8 B P 8 PL 0.25 (0.00) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G K C D PL 0.25 (0.00) M T B S A S M R X 45 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC BSC J K M P R ON Semiconducor and are regisered rademarks of Semiconducor Componens Indusries, LLC (SCILLC). SCILLC reserves he righ o make changes wihou furher noice o any producs herein. SCILLC makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SCILLC assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Typical parameers which may be provided in SCILLC daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SCILLC does no convey any license under is paen righs nor he righs of ohers. SCILLC producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he SCILLC produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SCILLC producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SCILLC and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SCILLC was negligen regarding he design or manufacure of he par. SCILLC is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON Semiconducor P.O. Box 632, Phoenix, Arizona USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderli@onsemi.com N. American Technical Suppor: Toll Free USA/Canada Japan: ON Semiconducor, Japan Cusomer Focus Cener 2 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconducor Websie: Order Lieraure: hp:// For addiional informaion, please conac your local Sales Represenaive. MC4008B/D

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