High Performance Silicon Gate CMOS
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1 High Performance Silicon Gae MOS The M7H7A is idenical in pinou o he LS7. The device inpus are compaible wih sandard MOS oupus; wih pull up resisors, hey are compaible wih LSTTL oupus. This device coiss of six D flip flops wih common lock and Rese inpus. Each flip flop is loaded wih a low o high raiion of he lock inpu. Rese is asynchronous and acive low. Oupu Drive apabiliy: 0 LSTTL Loads Oupus Direcly Inerface o MOS, NMOS, and TTL Operaing olage Range: 2 o 6 Low Inpu urren:.0 A In ompliance wih he Requiremens Defined by JEDE Sandard No. 7A hip omplexiy: 2 FETs or 0.5 Equivalen Gaes RESET 0 D0 D D Figure. Pin Assignmen 9 5 D5 D D3 3 LOK PDIP N SUFFIX ASE 68 SO D SUFFIX ASE 75B TSSOP DT SUFFIX ASE 98F MARKING DIAGRAMS M7H7AN AWLYYWW H7A AWLYWW H 7A ALYW FUNTION TABLE Inpus Oupu Rese lock D L X X L H H H H L L H L X No hange H X No hange A = Assembly Locaion L, WL = Wafer Lo Y, YY = Year W, WW = Work Week ORDERING INFORMATION Device Package Shipping M7H7AN PDIP 2000/Box M7H7AD SOI 8/Rail M7H7ADR2 SOI 2500/Reel M7H7ADT TSSOP 96/Rail M7H7ADTR2 TSSOP 2500/Reel Semiconducor omponens Indusries, LL, 200 May, 200 Rev. 8 Publicaion Order Number: M7H7A/D
2 M7H7A DATA INPUTS D0 D D2 D3 D D NONINERTING OUTPUTS LOK RESET 9 PIN = PIN 8 = Figure 2. Logic Diagram DESIGN/ALUE TABLE Design rieria alue Unis Inernal Gae oun* 0.5 ea. Inernal Gae Propagaion Delay.5 Inernal Gae Power Dissipaion W Speed Power Produc.0075 pj *Equivalen o a wo inpu NAND gae. 2
3 M7H7A MAXIMUM RATINGS (Noe ) Symbol Parameer alue Uni D Supply olage (Referenced o ) 0.5 o 7.0 IN D Inpu olage (Referenced o ).5 o.5 OUT D Oupu olage (Referenced o ) (Noe 2) 0.5 o 0.5 I IN D Inpu urren, per Pin 20 ma I OUT D Oupu urren, per Pin 25 ma I D Supply urren, and Pi 50 ma T STG Sorage Temperaure Range 65 o 50 T L Lead Temperaure, mm from ase for 0 Seconds PDIP, SOI, TSSOP 260 T J Juncion Temperaure Under Bias 50 JA Thermal Resisance PDIP SOI TSSOP P D Power Dissipaion in Sill Air a 85 PDIP SOI TSSOP MSL Moisure Seiiviy Level F R Flammabiliy Raing Oxygen Index: 30% 35% UL 9 O (0.25 in) ESD ESD Wihsand olage Human Body Model (Noe 3) Machine Model (Noe ) harged Device Model (Noe 5) I LATH UP Lach Up Performance Above and Below a 85 (Noe 6) 300 ma. Absolue maximum coninuous raings are hose values beyond which damage o he device may occur. Exended exposure o hese condiio or condiio beyond hose indicaed may adversely affec device reliabiliy. Funcional operaion under absolue maximum raed condiio is no implied. 2. I O absolue maximum raing mus be observed. 3. Tesed o EIA/JESD22 A A.. Tesed o EIA/JESD22 A5 A. 5. Tesed o JESD22 0 A. 6. Tesed o EIA/JESD For high frequency or heavy load coideraio, see he ON Semiconducor High Speed MOS Daa Book (DL29/D). /W mw REOMMENDED OPERATING ONDITIONS Symbol Parameer Min Max Uni Î D Supply olage (Referenced o ) Î Î IN, OUT D Inpu olage, Oupu olage (Referenced o ) (Noe 8) 0 T A Operaing Temperaure, All Package Types Î r, f Inpu Rise and Fall Time (Figure ) Î = = Î Î = 6.0 Î Unused inpus may no be lef open. All inpus mus be ied o a high or low logic inpu volage level. 3
4 M7H7A D ELETRIAL HARATERISTIS (olages Referenced o ) Guaraneed Limi Symbol Parameer Tes ondiio 55 o Uni IH Î Minimum High Level Inpu Î OUT = 0. or Î.5 olage I OUT 20 A Î Î IL Maximum Low Level Inpu Î olage Î OUT = 0. or I OUT 20 A Î Î.8.8 OH Î Minimum High Level Oupu Î IN = IH or IL olage I OUT 2.0 Î A Î Î Î Î IN = IH or IL I Î OUT.0 ma 3.98 I OUT 5.2 ma Î OL Î Î Maximum Low Level Oupu IN = IH or IL olage Î I OUT 20 A Î Î Î Î Î IN = IH or IL I OUT.0 ma 0.26 Î I OUT 5.2 ma 6.0 Î I IN Î Maximum Inpu Leakage urrenî IN = or 6.0 Î 0..0 A Maximum uiescen Supply Î IN = or 6.0 Î A I urren (per Package) I OUT = 0 A 9. Informaion on ypical parameric values, along wih high frequency or heavy load coideraio, can be found in he ON Semiconducor High Speed MOS Daa Book (DL29/D). A ELETRIAL HARATERISTIS ( L = 50 pf, Inpu r = f = 6.0 ) Guaraneed Limi Symbol Parameer 55 o Uni f max Î Maximum lock Frequency ( Duy ycle) 2.0 Î MHz (Figures and 7) Î PLH Maximum Propagaion Delay, lock o PHL Î (Figures 5 and 7) Î Î PLH Maximum Propagaion Delay, Rese o PHL Î (Figures 2 and 7) Î Î TLH Î Maximum Oupu Traiion Time, Any Oupu 2.0 Î THL (Figures and 7) Î 3 9 Maximum Inpu apaciance pf in 0.For propagaion delays wih loads oher han 50 pf, and informaion on ypical parameric values, see he ON Semiconducor High Speed MOS Daa Book (DL29/D). 25, = PD Power Dissipaion apaciance, per Enabled Oupu (Noe ) 62 pf. Used o deermine he no load dynamic power coumpion: P D = PD 2 f + I. For load coideraio, see he ON Semiconducor High Speed MOS Daa Book (DL29/D).
5 M7H7A TIMING REUIREMENTS ( L = 50 pf, Inpu r = f = 6.0 ) Guaraneed Limi 55 o Symbol Parameer Figure Min Max Min Max Min Max Uni su Î Minimum Seup Time, Daa o lock h Minimum Hold Time, lock o Daa rec Î Minimum Recovery Time, 5 Rese Inacive o lock w Î Minimum Pulse Widh, lock w Minimum Pulse Widh, Rese r, f Maximum Inpu Rise and Fall Times LOK D0 RESET D 5 D D3 0 3 D 3 2 D5 5 5 Figure 3. Expanded Logic Diagram 5
6 M7H7A r f LOK 90% 0% w /f max RESET PHL w PLH PHL 90% 0% TLH THL LOK rec Figure. Swiching Waveform Figure 5. Swiching Waveform ALID TEST POINT DATA su h DEIE UNDER TEST OUTPUT L * LOK *Includes all probe and jig capaciance Figure 6. Swiching Waveform Figure 7. Tes ircui 6
7 M7H7A PAKAGE DIMENSIONS PDIP N SUFFIX ASE ISSUE R H A G B F S K D PL T J L M SOI D SUFFIX ASE 75B 05 ISSUE J T G A D PL K B P 8 PL M R X 5 J F 7
8 M7H7A PAKAGE DIMENSIONS T L PIN IDENT. D 2X L/2 X K REF 9 8 A G TSSOP DT SUFFIX ASE 98F 0 ISSUE O B U H N N J J F DETAIL E DETAIL E K K ÇÇÇ ÉÉÉ SETION N N M W ON Semiconducor and are rademarks of Semiconducor omponens Indusries, LL (SILL). SILL reserves he righ o make changes wihou furher noice o any producs herein. SILL makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SILL assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, coequenial or incidenal damages. Typical parameers which may be provided in SILL daa shees and/or specificaio can and do vary in differen applicaio and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SILL does no convey any licee under is paen righs nor he righs of ohers. SILL producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaio inended o suppor or susain life, or for any oher applicaion in which he failure of he SILL produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SILL producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SILL and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agai all claims, coss, damages, and expees, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SILL was negligen regarding he design or manufacure of he par. SILL is an Equal Opporuniy/Affirmaive Acion Employer. PUBLIATION ORDERING INFORMATION NORTH AMERIA Lieraure Fulfillmen: Lieraure Disribuion ener for ON Semiconducor P.O. Box 53, Denver, olorado 8027 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada ONli@hibberco.com Fax Respoe Line: or Toll Free USA/anada N. American Technical Suppor: Toll Free USA/anada EUROPE: LD for ON Semiconducor European Suppor German Phone: (+) (Mon Fri 2:30pm o 7:00pm ET) ONli german@hibberco.com French Phone: (+) (Mon Fri 2:00pm o 7:00pm ET) ONli french@hibberco.com English Phone: (+) (Mon Fri 2:00pm o 5:00pm GMT) ONli@hibberco.com EUROPEAN TOLL FREE AESS*: *Available from Germany, France, Ialy, UK, Ireland ENTRAL/SOUTH AMERIA: Spanish Phone: (Mon Fri 8:00am o 5:00pm MST) ONli spanish@hibberco.com Toll Free from Mexico: Dial for Access hen Dial ASIA/PAIFI: LD for ON Semiconducor Asia Suppor Phone: (Tue Fri 9:00am o :00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: ONli asia@hibberco.com JAPAN: ON Semiconducor, Japan usomer Focus ener 32 Nishi Goanda, Shinagawa ku, Tokyo, Japan 003 Phone: r525@oemi.com ON Semiconducor Websie: For addiional informaion, please conac your local Sales Represenaive. 8 M7H7A/D
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of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC74HCT38A is identical in pinout to the LS38. The HCT38A may be used as a level converter for interfacing
MC14015B. Dual 4 Bit Static Shift Register
M0B Dual Bi Saic Shif egiser The M0B dual bi saic shif regiser is coruced wih MOS Phannel and Nhannel enhancemen mode devices in a single monolihic srucure. I coiss of wo idenical, independen sae serialinpu/paralleloupu
MC14015B. Dual 4 Bit Static Shift Register
M405B ual 4Bi Saic Shif egiser The M405B dual 4bi saic shif regiser is consruced wih MOS Phannel and Nhannel enhancemen mode devices in a single monolihic srucure. I consiss of wo idenical, independen
MC74AC109, MC74ACT109. Dual JK Positive Edge Triggered Flip Flop
MC9, MC9 Dual JK Positive EdgeTriggered FlipFlop The MC9/9 coists of two highspeed completely independent traition clocked JK flipflops. The clocking operation is independent of rise and fall times of
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in
Figure 1. Pinout: 16 Lead Packages Conductors (Top View) ORDERING INFORMATION Figure 2. Logic Symbol PIN ASSIGNMENT
The MC74AC138/74ACT138 is a high speed 1 of 8 decoder/demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel
74HC of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The 74HC38 is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are
74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 4HC4 is identical in pinout to the LS4. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they
HV513 8-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs, POL, Hi-Z, and Short Circuit Detect
H513 8-Channel Serial o Parallel Converer wih High olage Push-Pull s, POL, Hi-Z, and Shor Circui Deec Feaures HCMOS echnology Operaing oupu volage of 250 Low power level shifing from 5 o 250 Shif regiser
Schmitt Trigger Inputs Outputs Source/Sink 24 ma ACT132 Has TTL Compatible Inputs. ORDERING INFORMATION
The MC74AC/74ACT132 contains four 2 input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter free output signals. In addition, they have greater noise
74HCT245. Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs. High-Performance Silicon-Gate CMOS
Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS The 74HCT245 is identical in pinout to LS245. The device has TTL-Compatible Inputs. The HCT245
MC74HC4020A. 14-Stage Binary Ripple Counter. High Performance Silicon Gate CMOS
M74H20A 4-Stage Binary Ripple ounter High Performance Silicon Gate MOS The M7420A is identical in pinout to the standard MOS M20B. The device inputs are compatible with standard MOS outputs; with pullup
MC74HC4040A. 12 Stage Binary Ripple Counter. High Performance Silicon Gate CMOS
M74HA 2 Stage Binary Ripple ounter High Performance Silicon Gate MOS The M74A is identical in pinout to the standard MOS M. The device inputs are compatible with standard MOS outputs; with pullup resistors,
MC14543B. MARKING DIAGRAMS ORDERING INFORMATION. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) PDIP 16 P SUFFIX CASE 648
The MC14543B BCD to seven segment latch/decoder/driver is designed for use with liquid crystal readouts, and is cotructed with complementary MOS (CMOS) enhancement mode devices. The circuit provides the
74HC244 Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with
74HC245. Octal 3 State Noninverting Bus Transceiver. High Performance Silicon Gate CMOS
Octal 3 State Noninverting Bus Traceiver High Performance Silicon Gate CMOS The 74HC245 is identical in pinout to the LS245. The device inputs are compatible with standard CMOS outputs; with pull up resistors,
LOW POWER SCHOTTKY. ESD > 3500 Volts. GUARANTEED OPERATING RANGES ORDERING INFORMATION V CC 8 7 GND
ESD > 3500 Volts V CC 8 4 3 2 0 9 LOW POWER SCHOTTKY 2 3 4 5 6 7 GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage 4.75 5.0 5.25 V T A Operating Ambient Temperature
MC74VHC1GT125. Noninverting Buffer / CMOS Logic Level Shifter with LSTTL Compatible Inputs
C74CGT Noninvering Buffer / COS ogic evel Shifer wih STT Compaible Inpus The C74CGT is a single gae noninvering buffer fabricaed wih silicon gae COS echnology. I achieves high speed operaion similar o
MC74AC138, MC74ACT of 8 Decoder/Demultiplexer
1 of 8 Decoder/Demultiplexer The MC74AC138/74ACT138 is a high speed 1 of 8 decoder/demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple
MC74ACT Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
8 Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins The MC74ACT323 is an 8-bit universal shift/storage register with3-state outputs. Its function is similar to the MC74ACT299
with LSTTL Compatible Inputs
with STT Compatible Inputs The MC74HC259 is an 8 bit Addressable atch fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT devices while
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC06 contains six high speed, master slave type D flip flops. Clocking is common to all six flip flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place
74HC86. Quad 2 Input Exclusive OR Gate. High Performance Silicon Gate CMOS
Quad 2 Input Exclusive OR Gate MARKING DIAGRAMS High Performance Silicon Gate CMOS The is identical in pinout to the LS86. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10138L AWLYYWW
The MC101 is a four bit counter capable of divide by two, five, or ten functions. It is composed of four set reset master slave flip flops. Clock inputs trigger on the positive going edge of the clock
MC74VHC14. Hex Schmitt Inverter
MC74HC4 Hex Schmitt Inverter The MC74HC4 is an advanced high speed CMOS Schmitt inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky
The MC10107 is a triple 2 input exclusive OR/NOR gate. P D = 40 mw typ/gate (No Load) t pd = 2.8 ns typ t r, t f = 2.
The MC10107 is a triple input exclusive OR/NOR gate. P D = 0 mw typ/gate (No Load) t pd =. ns typ t r, t f =. ns typ (0% 0%) LOGIC DIAGRAM MARKING DIAGRAMS CDIP 16 L SUFFIX CASE 60 16 1 MC10107L AWLYYWW
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC10176 contains six high-speed, master slave type D flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes
CMOS MSI (Low Power Complementary MOS)
CMOS MSI (Low Power Complementary MOS) The MC14513B BCD to seven segment latch/decoder/driver is cotructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single
MC74AC74, MC74ACT74. Dual D Type Positive Edge Triggered Flip Flop
Dual D Type Positive Edge Triggered Flip Flop The MC74AC74/74ACT74 is a dual D type flip flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is traferred
MC74HCT573A/D. Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC74HCT573A is identical in pinout to the LS573. This device may be used as a level converter
MC74LCX138MEL. With 5 V Tolerant Inputs
With 5 V Tolerant Inputs The MC74LCX38 is a high performance, 3 to 8 decoder/demultiplexer operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading
PI74STX1G126. SOTiny Gate STX Buffer with 3-State Output. Features. Descriptio n. Block Diagram. Pin Configuration
PI74STXG6 4567890456789045678904567890456789045678904567890456789045678904567890456789045678904567890 4567890456789045678904567890456789045678904567890456789045678904567890456789045678904567890 SOTiny
Type Marking Pin Configuration Package SMBT3904/MMBT3904 SOT23 SMBT3904S 2=E 1=B 3=C 1=E1 2=B1 3=C2
SMBT94...MMBT94 NPN Silicon Swiching Transisors High D curren gain:. ma o ma Low collecoremier sauraion volage For SMBT94S: Two (galvanic) inernal isolaed ransisors wih good maching in one package omplemenary
MC74HC138A. 1-of-8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
MC74HC38A -of-8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The MC74HC38A is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163. Synchronous Presettable Binary Counter
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 Synchronous Presettable Binary Counter The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high speed synchronous modulo 16 binary counters. They are synchronously
NE522 High Speed Dual Differential Comparator/Sense Amp
HighSpeed DualDifferential Comparator/Sense Amp Features 5 ns Maximum Guaranteed Propagation Delay 0 A Maximum Input Bias Current TTL-Compatible Strobes and Outputs Large Common-Mode Input oltage Range
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10173L AWLYYWW
The MC03 is a quad two channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data
MC74VHC132. Quad 2 Input NAND Schmitt Trigger
MC74HC32 Quad 2 Input NAND Schmitt Trigger The MC74HC32 is an advanced high speed CMOS Schmitt NAND trigger fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
MC14020B. 14-Bit Binary Counter
M4020B 4-Bit Binary ounter The M4020B 4stage binary counter is cotructed with MOS Phannel and Nhannel enhancement mode devices in a single monolithic structure. This part is designed with an input wave
High Performance Silicon Gate CMOS
igh Performance Silicon Gate MOS The M7400A is identical in pinout to the S00. The device inputs are compatible with Standard MOS outputs; with pullup resistors, they are compatible with STT outputs. Output
MC14511B. MARKING DIAGRAMS 16. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2) ORDERING INFORMATION
The MC14511B BCD to seven segment latch/decoder/driver is cotructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides
MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10161L AWLYYWW
The MC10161 is designed to decode a three bit input word to a one of eight line output. The selected output will be low while all other outputs will be high. The enable inputs, when either or both are
MC74HC244A Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs;