MC74HC74A. Dual D Flip-Flop with Set and Reset. High Performance Silicon Gate CMOS

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Barry Bailey
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1 Dual D Flip-Flop wih Se and Rese High Performance Silicon Gae CMOS The MC4HC4A is idenical in pinou o he LS4. The device inpus are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible wih LSTTL oupus. This device consiss of wo D flip flops wih individual Se, Rese, and Clock inpus. Informaion a a D inpu is ransferred o he corresponding Q oupu on he nex posiive going edge of he clock inpu. Boh Q and Q oupus are available from each flip flop. The Se and Rese inpus are asynchronous. Feaures Oupu Drive Capabiliy: 0 LSTTL Loads Oupus Direcly Inerface o CMOS, NMOS, and TTL Operaing Volage Range: 2.0 o 6.0 V Low Inpu Curren:.0 A High Noise Immuniy Characerisic of CMOS Devices In Compliance wih he JEDEC Sandard No..0 A Requiremens Chip Complexiy: 28 FETs or 32 Equivalen Gaes These Devices are Pb Free, Halogen Free and are RoHS Complian PDIP 4 N SUFFIX CASE 646 SOIC 4 D SUFFIX CASE 5A TSSOP 4 DT SUFFIX CASE 948G 4 MARKING DIAGRAMS MC4HC4AN AWLYYWWG 4 HC4AG AWLYWW HC 4A ALYW 4 4 SOEIAJ 4 F SUFFIX CASE 965 4HC4A ALYWG A = Assembly Locaion L, WL = Wafer Lo Y, YY = Year W, WW = Work Week G or = Pb Free Package (Noe: Microdo may be in eiher locaion) ORDERING INFORMATION See deailed ordering and shipping informaion in he package dimensions secion on page 4 of his daa shee. Semiconducor Componens Indusries, LLC, 20 May, 20 Rev. 2 Publicaion Order Number: MC4HC4A/D

2 PIN ASSIGNMENT LOGIC DIAGRAM RESET 4 RESET DATA CLOCK SET Q Q FUNCTION TABLE Inpus Oupus Se Rese Clock Daa Q Q L H X X H L H L X X L H L L X X H* H* H H H H L H H L L H H H L X No Change H H H X No Change H H X No Change RESET 2 DATA 2 CLOCK 2 SET 2 Q2 Q2 DATA CLOCK SET RESET 2 DATA 2 CLOCK 2 SET PIN 4 = PIN = Q Q Q2 Q2 *Boh oupus will remain high as long as Se and Rese are low, bu he oupu saes are unpredicable if Se and Rese go high simulaneously. MAXIMUM RATINGS ÎÎ Symbol Parameer Value Uni ÎÎ DC Supply Volage (Referenced o ) 0.5 o +.0 V V in ÎÎ DC Inpu Volage (Referenced o ) Î 0.5 o V V ou ÎÎ DC Oupu Volage (Referenced o ) Î 0.5 o V I in ÎÎ DC Inpu Curren, per Pin Î ± 20 ma I ou DC Oupu Curren, per Pin ± 25 ma I CC DC Supply Curren, and Pins ± 50 ma P D Power Dissipaion in Sill Air, Plasic DIP 50 mw Î SOIC Package Î 500 Î TSSOP Package Î 450 T sg Sorage Temperaure 65 o + 50 C T L Lead Temperaure, mm from Case for 0 Seconds C (Plasic DIP, SOIC or TSSOP Package) 260 Î 300 Sresses exceeding Maximum Raings may damage he device. Maximum Raings are sress raings only. Funcional operaion above he Recommended Operaing Condiions is no implied. Exended exposure o sresses above he Recommended Operaing Condiions may affec device reliabiliy. Deraing Plasic DIP: 0 mw/ C from 65 o 25 C SOIC Package: mw/ C from 65 o 25 C TSSOP Package: 6. mw/ C from 65 o 25 C RECOMMENDED OPERATING CONDITIONS ÎÎ Symbol Parameer Min Max Uni DC Supply Volage (Referenced o ) V V in, V ou ÎÎ DC Inpu Volage, Oupu Volage (Referenced o ) 0 VCC V T A ÎÎ Operaing Temperaure, All Package Types C r, f ÎÎ Inpu Rise and Fall Time = 2.0 V ns (Figures, 2, 3) V Î CC = 3.0 V = 4.5 V Î = 6.0 V This device conains proecion circuiry o guard agains damage due o high saic volages or elecric fields. However, precauions mus be aken o avoid applicaions of any volage higher han maximum raed volages o his high impedance circui. For proper operaion, V in and V ou should be consrained o he range (V in or V ou ). Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher or ). Unused oupus mus be lef open. 2

3 DC ELECTRICAL CHARACTERISTICS (Volages Referenced o ) Guaraneed Limi 55 o Symbol Parameer Tes Condiions V 25 C 85 C 25 C Uni V IH Î Î Minimum High Level Inpu V ou = 0. V or 0. V V Volage Î I ou 20 A ÎÎ V IL Maximum Low Level Inpu V Î Volage Î ou = 0. V or 0. V V I ou 20 A ÎÎ V OH Minimum High Level Oupu V Î Î in = V IH or V IL V Volage I ou 20 A V in = V IH or V IL I ou 2.4 ma I ou 4.0 ma I ou 5.2 ma V OL Î Maximum Low Level Oupu Î V in = V IH or V IL ÎÎ Volage Î I ou 20 A V ÎÎ V in = V IH or V IL I ou 2.4 ma I ou 4.0 ma I ou 5.2 ma I in Maximum Inpu Leakage Curren V in = or 6.0 ± 0. ±.0 ±.0 A Î ÎÎ I CC Maximum Quiescen Supply V Î Î in = or ÎÎ ÎÎ A Curren (per Package) I ou = 0 A AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Inpu r = f = 6.0 ns) ÎÎ Guaraneed Limi 55 o SymbolÎ Parameer V 25 C 85 C 25 C Uni f max Î Maximum Clock Frequency ( Duy Cycle) MHz (Figures and 4) PLH, Maximum Propagaion Delay, Clock o Q or Q ns PHL (Figures and 4) ÎÎ PLH, Maximum Propagaion Delay, Se or Rese o Q or Q ns PHL Î (Figures 2 and 4) TLH, Maximum Oupu Transiion Time, Any Oupu ns THL Î (Figures and 4) ÎÎ Maximum Inpu Capaciance pf C in C PD Power Dissipaion Capaciance (Per Flip Flop)* * Used o deermine he no load dynamic power consumpion: P D = C PD V 2 CC f + I CC. 25 C, = 5.0 V 32 pf 3

4 TIMING REQUIREMENTS (Inpu r = f = 6.0 ns) Guaraneed Limi 55 o Symbol Parameer V 25 C 85 C 25 C ÎÎ Uni su Minimum Seup Time, Daa o Clock ns (Figure 3) ÎÎ h Minimum Hold Time, Clock o Daa ns (Figure 3) ÎÎ rec Minimum Recovery Time, Se or Rese Inacive o Clock ns (Figure 2) ÎÎ w Minimum Pulse Widh, Clock ns (Figure ) ÎÎ w Minimum Pulse Widh, Se or Rese ns (Figure 2) ÎÎ r, f Maximum Inpu Rise and Fall Times ns (Figures, 2, 3) ÎÎ ORDERING INFORMATION MC4HC4ANG Device Package Shipping PDIP 4 25 Unis / Rail MC4HC4ADG MC4HC4ADR2G SOIC 4 SOIC 4 55 Unis / Rail 2500 / Tape & Reel MC4HC4ADTR2G TSSOP 4* 2500 / Tape & Reel MC4HC4AFG SOEIAJ 4 50 Unis / Rail MC4HC4AFELG SOEIAJ / Tape & Reel For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD80/D. *This package is inherenly Pb Free. 4

5 SWITCHING WAVEFORMS CLOCK 90% 0% w f r /f max SET OR RESET Q OR Q w PHL Q or Q 90% 0% PLH TLH PHL THL Q OR Q CLOCK PLH rec Figure. Figure 2. DATA CLOCK su VALID h DEVICE UNDER TEST OUTPUT TEST POINT C L * *Includes all probe and jig capaciance Figure 3. Figure 4. 4, 0 SET DATA 2, 2 5, 9 Q 3, CLOCK 6, 8 Q, 3 RESET Figure 5. EXPANDED LOGIC DIAGRAM 5

6 PACKAGE DIMENSIONS PDIP 4 N SUFFIX CASE ISSUE P 4 8 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. T N SEATING PLANE A INCHES MILLIMETERS DIM MIN MAX MIN MAX A B F L C D C F G 0.00 BSC 2.54 BSC H J K K J L M 0 0 H G D 4 PL M N (0.005) M 6

7 T SEATING PLANE G A 4 8 D 4 PL B K P PL C 0.25 (0.00) M T B S A S MC4HC4A PACKAGE DIMENSIONS SOIC 4 D SUFFIX CASE 5A 03 ISSUE J 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.2 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES R X 45 F DIM MIN MAX MIN MAX A B C D M J F G.2 BSC BSC J K M 0 0 P R SOLDERING FOOTPRINT 4X 0.58 X.04 4X.52.2 PITCH DIMENSIONS: MILLIMETERS

8 PACKAGE DIMENSIONS TSSOP 4 DT SUFFIX CASE 948G 0 ISSUE B 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C 4 G 4X K REF A V 0.0 (0.004) M T U S V S 8 B U H N N J J F DETAIL E DETAIL E 0.25 (0.00) K K M ÇÇÇ ÉÉÉ SECTION N N W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLDERING FOOTPRINT PITCH 4X X.26 DIMENSIONS: MILLIMETERS 8

9 PACKAGE DIMENSIONS SOEIAJ 4 F SUFFIX CASE ISSUE B e 4 8 Z D E A H E VIEW P M L E Q L DETAIL P NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INCHES A b A A DIM MIN MAX MIN MAX 0.3 (0.005) M 0.0 (0.004) b c D E e.2 BSC BSC H E L L E M Q Z c ON Semiconducor and are regisered rademarks of Semiconducor Componens Indusries, LLC (SCILLC). SCILLC reserves he righ o make changes wihou furher noice o any producs herein. SCILLC makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SCILLC assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Typical parameers which may be provided in SCILLC daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SCILLC does no convey any license under is paen righs nor he righs of ohers. SCILLC producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he SCILLC produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SCILLC producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SCILLC and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SCILLC was negligen regarding he design or manufacure of he par. SCILLC is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON Semiconducor P.O. Box 563, Denver, Colorado 802 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderli@onsemi.com N. American Technical Suppor: Toll Free USA/Canada Europe, Middle Eas and Africa Technical Suppor: Phone: Japan Cusomer Focus Cener Phone: ON Semiconducor Websie: Order Lieraure: hp:// For addiional informaion, please conac your local Sales Represenaive MC4HC4A/D

MC74HC138A. 1 of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS

MC74HC138A. 1 of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS of 8 Decoder/ Demuliplexer High Performance Silicon Gae CMOS The is idenical in pinou o he LS8. The device inpus are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible wih LSTTL oupus.