MC14007UBF. MARKING DIAGRAMS. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) ORDERING INFORMATION
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1 The MC007UB muli purpose device consiss of hree N channel and hree P channel enhancemen mode devices packaged o provide access o each device. These versaile pars are useful in inverer circuis, pulse shapers, linear amplifiers, high inpu impedance amplifiers, hreshold deecors, ransmission gaing, and funcional gaing. Diode Proecion on All Inpus Supply Volage Range = 3.0 Vdc o 18 Vdc Capable of Driving Two Low power TTL Loads or One Low power Schoky TTL Load Over he Raed Temperaure Range Pin for Pin Replacemen for CD4007A or CD4007UB This device has 2 oupus wihou ESD Proecion. Ani saic precauions mus be aken. MAXIMUM RATINGS (Volages Referenced o V SS ) (Noe 2.) Symbol Parameer Value Uni V DD DC Supply Volage Range 0.5 o V V in, V ou Inpu or Oupu Volage Range (DC or Transien) 0.5 o V DD V I in, I ou P D Inpu or Oupu Curren (DC or Transien) per Pin Power Dissipaion, per Package (Noe 3.) ±10 ma 500 mw T A Ambien Temperaure Range 55 o +125 C T sg Sorage Temperaure Range 65 o +150 C T L Lead Temperaure (8 Second Soldering) 260 C 2. Maximum Raings are hose values beyond which damage o he device may occur. 3. Temperaure Deraing: Plasic P and D/DW Packages: 7.0 mw/c From 65C To 125C This device conains proecion circuiry o guard agains damage due o high saic volages or elecric fields. However, precauions mus be aken o avoid applicaions of any volage higher han maximum raed volages o his high impedance circui. For proper operaion, V in and V ou should be consrained o he range V SS (V in or V ou ) V DD. Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher V SS or V DD ). Unused oupus mus be lef open. A WL, L YY, Y WW, W = Assembly Locaion = Wafer Lo = Year = Work Week ORDERING INFORMATION Device Package Shipping MC007UBCP PDIP 2000/Box MC007UBD SOIC 55/Rail MC007UBDR2 SOIC 2500/Tape & Reel MC007UBDT MC007UBF PDIP P SUFFIX CASE 646 SOIC D SUFFIX CASE 751A TSSOP DT SUFFIX CASE 948G SOEIAJ F SUFFIX CASE 965 TSSOP SOEIAJ MARKING DIAGRAMS MC007UBCP AWLYYWW U AWLYWW 1 007U ALYW MC007U ALYW 96/Rail See Noe 1. MC007UBFEL SOEIAJ See Noe For ordering informaion on he EIAJ version of he SOIC packages, please conac your local ON Semiconducor represenaive. Semiconducor Componens Indusries, LLC, 2000 Augus, 2000 Rev. 4 1 Publicaion Order Number: MC007UB/D
2 PIN ASSIGNMENT SCHEMATIC Subsraes of P channel devices inernally conneced o V DD ; subsraes of N channel devices inernally conneced o V SS. Figure 1. Typical Applicaion: 2 Inpu Analog Muliplexer 2
3 ELECTRICAL CHARACTERISTICS (Volages Referenced o V SS ) ÎÎ ÎÎ 55C 25C ÎÎ 125C V DD Characerisic Î Symbol Vdc Min MaxÎ Min Î Typ (4.) Max Min Max Uni Oupu Volage 0 Level Î V OL Î Î Vdc V in = V DD or Î V in = 0 or V DD 1 LevelÎ V OH Î 5.0 ÎÎ Î 9.95 Î Vdc Inpu Volage 0 Level V (V O = 4.5 Vdc) Î IL Vdc 5.0 (V O = 9.0 Vdc) Î Î Î (V O = 13.5 Vdc) (V O = 0.5 Vdc) 1 Level V (V O = 1.0 Vdc) Î IH Vdc Î 8.0 Î (V O = 1.5 Vdc) Î 12.5 Î Oupu Drive Curren Î I OH Î madc (V OH = 2.5 Vdc) Source (V OH = 4.6 Vdc) Î 0.51 Î (V OH = 9.5 Vdc) Î 1.3 Î (V OH = 13.5 Vdc) (V OL = 0.4 Vdc) Sink I (V OL = 0.5 Vdc) Î OL madc Î 1.3 Î (V OL = 1.5 Vdc) Î 3.4 Î Inpu Curren Î I in 15 ± 0.1 Î Î ± ± 0.1 ± 1.0 µadc Inpu Capaciance Î C in (V in = 0) Î Î pf Quiescen Curren I (Per Package) Î DD µadc Î Î ÎÎ Î Î Toal Supply Curren (5.) (6.) Î I T 5.0 Î I T = (0.7 µa/khz) f + I DD /6 µadc (Dynamic plus Quiescen, 10 I Per Gae) (C L = 50 pf) 15 Î T = (1.4 µa/khz) f + I DD /6 I T = (2.2 µa/khz) f + I DD /6 4. Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he IC s poenial performance. 5. The formulas given are for he ypical characerisics only a 25C. 6. To calculae oal supply curren a loads oher han 50 pf: I T (C L ) = I T (50 pf) + (C L 50) Vfk where: I T is in µa (per package), C L in pf, V = (V DD V SS ) in vols, f in khz is inpu frequency, and k =
4 SWITCHING CHARACTERISTICS (7.) (C L = 50 pf, T A = 25C) ÎÎ V DD Î Î Characerisic Symbol Vdc Min Typ ÎÎ (8.) Max Uni Oupu Rise Time TLH ns Î Î Î ÎÎ TLH = (1.2 ns/pf) C L + 30 ns TLH = (0.5 ns/pf) C L + 20 ns ÎÎ 10 Î Î 45 Î 90 ÎÎ TLH = (0.4 ns/pf) C L + 15 ns ÎÎ 15 Î Î 35 Î 70 ÎÎ Oupu Fall Time ÎÎ THL Î Î Î ns ÎÎ THL = (1.2 ns/pf) C L + 15 ns THL = (0.5 ns/pf) C L + 15 ns ÎÎ THL = (0.4 ns/pf) C L + 10 ns ÎÎ 15 Î Î 30 Î 60 ÎÎ Turn Off Delay Time ÎÎ PLH Î Î Î ns ÎÎ PLH = (1.5 ns/pf) C L + 35 ns ÎÎ 5.0 Î Î 60 Î 125 ÎÎ PLH = (0.2 ns/pf) C L + 20 ns PLH = (0.15 ns/pf) C L ns ÎÎ 15 Î Î 25 Î 55 Turn On Delay Time PHL Î Î Î ns ÎÎ PHL = (1.0 ns/pf) C L + 10 ns ÎÎ 5.0 Î Î 60 Î 125 ÎÎ PHL = (0.3 ns/pf) C L + 15 ns PHL = (0.2 ns/pf) C L + 15 ns 7. The formulas given are for he ypical characerisics only. Swiching specificaions are for device conneced as an inverer. 8. Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he IC s poenial performance All unused inpus conneced o ground. All unused inpus conneced o ground. Figure 2. Typical Oupu Source Characerisics Figure 3. Typical Oupu Sink Characerisics These ypical curves are no guaranees, bu are design aids. Cauion: The maximum curren raing is 10 ma per pin. 4
5 µ µ Figure 4. Swiching Time and Power Dissipaion Tes Circui and Waveforms APPLICATIONS The MC007UB dual pair plus inverer, which has access o all is elemens offers a number of unique circui applicaions. Figures 1, 5, and 6 are a few examples of he device flexibiliy. X = Don Care Subsraes of P channel devices inernally conneced o V DD ; Subsraes of N channel devices inernally conneced o V SS. Figure 6. AOI Funcions Using Tree Logic Figure 5. 3 Sae Buffer 5
6 PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE ISSUE M B T N A F L C K J H G D PL M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A 03 ISSUE F A B P 7 PL T G D PL K C R X 45 F M J 6
7 PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G 01 ISSUE O L T 2X L/2 PIN 1 IDENT. D C X K REF N M B U A V G H N J J1 F DETAIL E K K1 ÇÇÇ ÉÉ SECTION N N DETAIL E W Z D e b E A H E A 1 VIEW P F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE ISSUE O M L E Q 1 L DETAIL P c 7
8 ON Semiconducor and are rademarks of Semiconducor Componens Indusries, LLC (SCILLC). SCILLC reserves he righ o make changes wihou furher noice o any producs herein. SCILLC makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SCILLC assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Typical parameers which may be provided in SCILLC daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SCILLC does no convey any license under is paen righs nor he righs of ohers. SCILLC producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he SCILLC produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SCILLC producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SCILLC and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SCILLC was negligen regarding he design or manufacure of he par. SCILLC is an Equal Opporuniy/Affirmaive Acion Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Lieraure Fulfillmen: Lieraure Disribuion Cener for ON Semiconducor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONli@hibberco.com Fax Response Line: or Toll Free USA/Canada N. American Technical Suppor: Toll Free USA/Canada EUROPE: LDC for ON Semiconducor European Suppor German Phone: (+1) (Mon Fri 2:30pm o 7:00pm CET) ONli german@hibberco.com French Phone: (+1) (Mon Fri 2:00pm o 7:00pm CET) ONli french@hibberco.com English Phone: (+1) (Mon Fri 12:00pm o 5:00pm GMT) ONli@hibberco.com EUROPEAN TOLL FREE ACCESS*: *Available from Germany, France, Ialy, UK CENTRAL/SOUTH AMERICA: Spanish Phone: (Mon Fri 8:00am o 5:00pm MST) ONli spanish@hibberco.com ASIA/PACIFIC: LDC for ON Semiconducor Asia Suppor Phone: (Tue Fri 9:00am o 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: ONli asia@hibberco.com JAPAN: ON Semiconducor, Japan Cusomer Focus Cener Nishi Goanda, Shinagawa ku, Tokyo, Japan Phone: r525@onsemi.com ON Semiconducor Websie: For addiional informaion, please conac your local Sales Represenaive. 8 MC007UB/D
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MC74HC273A. Octal D Flip Flop with Common Clock and Reset. High Performance Silicon Gate CMOS
M74H273A Ocal D Flip Flop wih ommon lock and Rese High Performance Silicon Gae MOS The M74H273A is idenical in pinou o he LS273. The device inpus are compaible wih sandard MOS oupus; wih pullup resisors,
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC10176 contains six high-speed, master slave type D flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648
The SN74LS247 is a BCD-to-Seven-Segment Decoder/Drivers. The LS247 composes the and with the tails. The LS247 has active-low outputs for direct drive of indicators. The LS247 features a lamp test input
MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10161L AWLYYWW
The MC10161 is designed to decode a three bit input word to a one of eight line output. The selected output will be low while all other outputs will be high. The enable inputs, when either or both are
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC06 contains six high speed, master slave type D flip flops. Clocking is common to all six flip flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place
MC74HCT373A/D. Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs. High Performance Silicon Gate CMOS
Ocal -Sae Noninvering Traparen Lach wih LSTTL-Compaible Inpus High Performance Silicon Gae CMOS The MC7HCT7A may be used as a level converer for inerfacing TTL or NMOS oupus o High Speed CMOS inpus. The
MC74HC573A. Octal 3-State Noninverting Transparent Latch. High Performance Silicon Gate CMOS
Ocal 3-Sae Noninvering Transparen Lach High Performance Silicon Gae CMOS The MC74HC573 is idenical in pinou o he LS573. The devices are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible
MC14015B. Dual 4 Bit Static Shift Register
M0B Dual Bi Saic Shif egiser The M0B dual bi saic shif regiser is coruced wih MOS Phannel and Nhannel enhancemen mode devices in a single monolihic srucure. I coiss of wo idenical, independen sae serialinpu/paralleloupu
MC14584B. Hex Schmitt Trigger
MC4584B Hex Schmitt Trigger The MC4584B Hex Schmitt Trigger is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. These devices find primary use where
MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10138L AWLYYWW
The MC101 is a four bit counter capable of divide by two, five, or ten functions. It is composed of four set reset master slave flip flops. Clock inputs trigger on the positive going edge of the clock
Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS
TECHNICAL DATA IW0B Analog Muliplexer Demuliplexer HighPerformance SiliconGae CMOS The IW0B analog muliplexer/demuliplexer is digially conrolled analog swiches having low ON impedance and very low OFF
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION
These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS22 has an internal
MARKING DIAGRAMS DIP PIN ASSIGNMENT ORDERING INFORMATION FUNCTION TABLE CDIP 16 L SUFFIX CASE 620 MC10136L AWLYYWW
The MC16 is a high speed synchronous counter that can count up, count down, preset, or stop count at frequencies exceeding 1 MHz. The flexibility of this device allows the designer to use one basic counter
Quad 2-Input OR Gate High-Performance Silicon-Gate CMOS
TECNICAL DATA Quad 2-Inpu OR ae igh-performance Silicon-ae CMOS The is idenical in pinou o he LS/ALS32. The device inpus are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible wih
SN74LS157MEL. Quad 2 Input Multiplexer LOW POWER SCHOTTKY
Quad 2 Input Multiplexer The LSTTL/ MSI is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs
SN74LS145MEL. 1 of 10 Decoder/Driver Open Collector LOW POWER SCHOTTKY
of 0 Decoder/Driver Open Collector The SN74LS45, -of-0 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 0-digit incandescent displays. All outputs remain off for
MC74HC132A. Quad 2 Input NAND Gate with Schmitt Trigger Inputs. High Performance Silicon Gate CMOS
Quad 2 Input NAND Gate with Schmitt Trigger Inputs High Performance Silicon Gate CMOS The is identical in pinout to the LS32. The device inputs are compatible with standard CMOS outputs; with pull up resistors,
MC14015B. Dual 4 Bit Static Shift Register
M405B ual 4Bi Saic Shif egiser The M405B dual 4bi saic shif regiser is consruced wih MOS Phannel and Nhannel enhancemen mode devices in a single monolihic srucure. I consiss of wo idenical, independen
MC74HC165A. 8 Bit Serial or Parallel Input/ Serial Output Shift Register. High Performance Silicon Gate CMOS
MC74CA 8 Bi Serial or Parallel Inpu/ Serial Oupu Shif Regiser igh Performance Silicon Gae CMOS The MC74CA is idenical in pinou o he S. The device inpus are compaible wih sandard CMOS oupus; wih pullup
MC74AC138, MC74ACT of 8 Decoder/Demultiplexer
1 of 8 Decoder/Demultiplexer The MC74AC138/74ACT138 is a high speed 1 of 8 decoder/demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple
MC74HC393A. Dual 4-Stage Binary Ripple Counter. High Performance Silicon Gate CMOS
Dual 4-Sage Binary Ripple ouner High Performance Silicon Gae MOS The M74H393A is idenical in pinou o he LS393. The device inpus are compaible wih sandard MOS oupus; wih pullup resisors, hey are compaible
MC74LCX138MEL. With 5 V Tolerant Inputs
With 5 V Tolerant Inputs The MC74LCX38 is a high performance, 3 to 8 decoder/demultiplexer operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading
NE522 High Speed Dual Differential Comparator/Sense Amp
HighSpeed DualDifferential Comparator/Sense Amp Features 5 ns Maximum Guaranteed Propagation Delay 0 A Maximum Input Bias Current TTL-Compatible Strobes and Outputs Large Common-Mode Input oltage Range
SN74LS132MEL. Quad 2 Input Schmitt Trigger NAND Gate LOW POWER SCHOTTKY
Quad 2 Input Schmitt Trigger NAND Gate The SN74LS32 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly
MC74AC109, MC74ACT109. Dual JK Positive Edge Triggered Flip Flop
MC9, MC9 Dual JK Positive EdgeTriggered FlipFlop The MC9/9 coists of two highspeed completely independent traition clocked JK flipflops. The clocking operation is independent of rise and fall times of
74HC of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The 74HC38 is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are
MC74HC573A. Octal 3-State Noninverting Transparent Latch. High Performance Silicon Gate CMOS
Ocal 3-Sae Noninvering Traparen Lach High Performance Silicon Gae COS The C74HC573 is idenical in pinou o he LS573. The devices are compaible wih sandard COS oupus; wih pullup resisors, hey are compaible
SN74LS125A, SN74LS126A. Quad 3 State Buffers LOW POWER SCHOTTKY. LS125A LS126A TRUTH TABLES ORDERING INFORMATION
Quad 3 State Buffers V CC E D O E D O 4 3 2 0 9 8 LOW POWER SCHOTTKY 2 3 4 5 6 E D O E D O LS25A GND V CC E D O E D O 4 3 2 0 9 8 4 PLASTIC N SUFFIX CASE 646 LS25A INPUTS 2 3 4 5 6 E D O E LS26A D O GND
MC14060B. 14 Bit Binary Counter and Oscillator
4Bit Binary Counter and Oscillator The MC4060B is a 4stage binary ripple counter with an onchip oscillator buffer. The oscillator configuration allows design of either RC or crystal oscillator circuits.
PIN ASSIGNMENT LOGI DIAGRAM LOK a RESET a a 2 a LOK b RESET b b LOK, 3 BINARY OUNTER 3, 4, 0 5, 9 6, a 4 a b 3 b RESET
Dual 4 Sage Binary Ripple ouner High Performance Silicon Gae MOS The M74H393A is idenical in pinou o he LS393. The device inpus are compaible wih sandard MOS oupus; wih pullup resisors, hey are compaible
MC74VHC132. Quad 2 Input NAND Schmitt Trigger
MC74HC32 Quad 2 Input NAND Schmitt Trigger The MC74HC32 is an advanced high speed CMOS Schmitt NAND trigger fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
SN74LS74AMEL LOW POWER SCHOTTKY
The SN74S74A dual edge-triggered flip-flop utilizes Schottky TT circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.
SN74LS151MEL. 8 Input Multiplexer LOW POWER SCHOTTKY
8 Input Multiplexer The TTL/MSI SN74LS5 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS5 can be used as
MC14099B. 8-Bit Addressable Latches
-Bit Addressable Latches The MC99B is an bit addressable latch. Data is entered in serial form when the appropriate latch is addressed (via address pi A, A, A) and write disable is in the low state. For
LOW POWER SCHOTTKY. MODE SELECT TRUTH TABLE ORDERING INFORMATION GUARANTEED OPERATING RANGES OPERATING MODE
The SN74S74A dual edge-triggered flip-flop utilizes Schottky TT circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary and outputs.
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate Description: The NTE4501 is a triple gate device in a 16 Lead DIP type package constructed with MOS P
with LSTTL Compatible Inputs
with STT Compatible Inputs The MC74HC259 is an 8 bit Addressable atch fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT devices while
SN74LS85MEL LOW POWER SCHOTTKY
The SN74LS85 is a 4-Bit Magnitude Camparator which compares two 4-bit words (A, B), each word having four Parallel Inputs (A0 A3, B0 B3); A3, B3 being the most significant inputs. Operation is not restricted
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION
The LSTTL/MSI SN74LS18 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION
The SN74S240 and SN74S244 are Octal Buffers and ine Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density.
MC74HC139A. Dual 1 of 4 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
MC74HC39A Dual of 4 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The MC74HC39A is identical in pinout to the LS39. The device inputs are compatible with standard CMOS outputs; with pull up
MC14017B. Decade Counter
M407B ecade ouner The M407B is a five sage Johon decade couner wih buil in code converer. High speed operaion and spike free oupus are obained by use of a Johon decade couner design. The en decoded oupus
SN74LS373, SN74LS374. Octal Transparent Latch with 3 State Outputs; Octal D Type Flip Flop with 3 State Output LOW POWER SCHOTTKY
Octal Transparent Latch with 3 State Outputs; Octal Type Flip Flop with 3 State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops
MC Bit Magnitude Comparator
Bit Magnitude Comparator The MC0 is a high speed expandable bit comparator for comparing the magnitude of two binary words. Two outputs are provided: and. A = B can be obtained by NORing the two outputs