MC14029B. Binary/Decade Up/Down Counter
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1 MC4029B Binary/Decade Up/Down Couner The MC4029B Binary/Decade up/down couner is coruced wih MOS P channel and N channel enhancemen mode devices in a single monolihic srucure. The couner coiss of ype D flip flop sages wih a gaing srucure o provide oggle flip flop capabiliy. The couner can be used in eiher Binary or BCD operaion. This complemenary MOS couner finds primary use in up/down and difference couning and frequency synhesizer applicaio where low power dissipaion and/or high noise immuniy is desired. I is also useful in A/D and D/A conversion and for magniude and sign generaion. Feaures Diode Proecion on All Inpus Supply Volage Range = 3.0 Vdc o 8 Vdc Inernally Synchronous for High Speed Logic Edge Clocked Design Coun Occurs on Posiive Going Edge of Clock Asynchronous Prese Enable Operaion Capable of Driving Two Low Power TTL Loads or One Low Power Schoky TTL Load Over he Raed Temperaure Range Pin for Pin Replacemen for CD4029B Pb Free Packages are Available* MAXIMUM RATINGS (Volages Referenced o ) Symbol Parameer Value Uni DC Supply Volage Range 0.5 o +8.0 V V in, V ou Inpu or Oupu Volage Range (DC or Traien) 0.5 o V I in, I ou P D Inpu or Oupu Curren (DC or Traien) per Pin Power Dissipaion, per Package (Noe ) ±0 ma 500 mw T A Ambien Temperaure Range 55 o +25 C T sg Sorage Temperaure Range 65 o +50 C T L Lead Temperaure 260 C (8 Second Soldering) Maximum raings are hose values beyond which device damage can occur. Maximum raings applied o he device are individual sress limi values (no normal operaing condiio) and are no valid simulaneously. If hese limis are exceeded, device funcional operaion is no implied, damage may occur and reliabiliy may be affeced.. Temperaure Deraing: Plasic P and D/DW Packages: 7.0 mw/ C From 65 C To 25 C This device conai proecion circuiry o guard agai damage due o high saic volages or elecric fields. However, precauio mus be aken o avoid applicaio of any volage higher han maximum raed volages o his high impedance circui. For proper operaion, V in and V ou should be corained o he range (V in or V ou ). Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher or ). Unused oupus mus be lef open. hp://oemi.com A WL, L YY, Y WW, W PDIP 6 P SUFFIX CASE 648 SOIC 6 D SUFFIX CASE 75B SOEIAJ 6 F SUFFIX CASE 966 MARKING DIAGRAMS MC4029BCP AWLYYWW 4029B AWLYWW MC4029B AWLYWW = Assembly Locaion = Wafer Lo = Year = Work Week ORDERING INFORMATION See deailed ordering and shipping informaion in he package dimeio secion on page 2 of his daa shee PIN ASSIGNMENT Q3 P3 P0 Q0 C ou *For addiional informaion on our Pb Free sraegy and soldering deails, please download he ON Semiconducor Soldering and Mouning Techniques Reference Manual, SOLDERRM/D CLK Q2 P2 P Q Semiconducor Compone Indusries, LLC, 2005 February, 2005 Rev. 5 Publicaion Order Number: MC4029
2 MC4029B TRUTH TABLE X = Don Care Carry In Up/Down Prese Enable Acion X 0 No Coun 0 0 Coun Up Coun Down X X Prese ORDERING INFORMATION Device Package Shipping MC4029BCP PDIP Unis / Rail MC4029BCPG PDIP Unis / Rail (Pb Free) MC4029BDR2 SOIC Unis / Tape & Reel MC4029BDR2G SOIC Unis / Tape & Reel (Pb Free) MC4029BFEL SOEIAJ Unis / Tape & Reel For informaion on ape and reel specificaio, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaio Brochure, BRD80/D. ELECTRICAL CHARACTERISTICS (Volages Referenced o ) Î 55 C 25 C 25 C Î Characerisic Symbol Vdc Min Max Min Typ Max (Noe 2) Min Max Î Uni Oupu Volage 0 Level V OL Vdc V in = or Level OH V in = 0 or V Î Vdc Inpu Volage 0 Level V IL Vdc (V O = 4.5 or 0.5 Vdc) (V O = 9.0 or.0 Vdc) (V O = 3.5 or.5 Vdc) Level V IH Vdc (V O = 0.5 or 4.5 Vdc) (V O =.0 or 9.0 Vdc) (V O =.5 or 3.5 Vdc) Oupu Drive Curren I OHÎ madc (V OH = 2.5 Vdc) Source (V OH = 4.6 Vdc) (V OH = 9.5 Vdc) (V OH = 3.5 Vdc) Î (V OL = 0.4 Vdc) Sink I (V OL = 0.5 Vdc) OL madc (V OL =.5 Vdc) Inpu Curren I in 5 ± 0. ± ± 0. ±.0 Adc Î Inpu Capaciance, (V in = 0) Cin 7.5 pf Quiescen Curren (Per Package) I DD Adc Î Toal Supply Curren (Noes 3 & 4) I T I T = (0.58 A/kHz) f + I DD Adc (Dynamic plus Quiescen, Per Package) 0 I T = (.20 A/kHz) f + I DD (C L = 50 pf on all oupus, all buffers 5 I T = (.70 A/kHz) f + I DD swiching) 2. Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he IC s poenial performance. 3. The formulas given are for he ypical characerisics only a 25 C. 4. To calculae oal supply curren a loads oher han 50 pf: I T ( ) = I T (50 pf) + ( 50) Vfk where: I T is in A (per package), in pf, V = ( ) in vols, f in khz is inpu frequency, and k = hp://oemi.com 2
3 MC4029B Î SWITCHING CHARACTERISTICS (.) ( = 50 pf, T A = 25 C) All Types Characerisic Î Symbol Min Typ (2.) Max Uni Oupu Rise and Fall Time Î TLH, TLH, THL = (.5 /pf) + 25 TLH, THL = (0.75 /pf) Î THL TLH, THL = (0.55 /pf) Propagaion Delay Time Î PLH, Clk o Q PLH, PHL = (.7 /pf) Î PHL PLH, PHL = (0.66 /pf) PLH, PHL = (0.5 /pf) Î Clk o C ou PLH, PHL = (.7 /pf) Î PLH, PHL PLH, PHL = (0.66 /pf) PLH, PHL = (0.5 /pf) Î C in o C ou PLH, PHL = (.7 /pf) + 95 Î PLH, PHL PLH, PHL = (0.66 /pf) PLH, PHL = (0.5 /pf) Î o Q PLH, PHL = (.7 /pf) Î PLH, PHL PLH, PHL = (0.66 /pf) PLH, PHL = (0.5 /pf) Î o C ou PLH, PHL = (. 7 /pf) Î PLH, PHL PLH, PHL = (0.66 /pf) PLH, PHL = (0.5 /pf) Î Clock Pulse Widh W(cl) Clock Pulse Frequency Î f cl MHz Prese Removal Time Î rem The Prese Signal mus be low prior o a posiive going raiion of he clock Î Clock Rise and Fall Time r(cl) 5 s f(cl) Carry In Seup Time Î su Up/Down Seup Time Î Î Binary/Decade Seup Time Prese Enable Pulse Widh Î W Î. The formulas given are for he ypical characerisics only a 25 C. 2. Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he IC s poenial performance hp://oemi.com 3
4 MC4029B 500 pf I D 0.0 F CERAMIC PULSE GENERATOR CLK P0 P P2 P3 Q0 Q Q2 Q3 C ou CLK 50% 90% 0% VARIABLE WIDTH Figure. Power Dissipaion Tes Circui and Waveform PROGRAMMABLE PULSE GENERATOR CLK P0 P P2 P3 Q0 Q Q2 Q3 C ou W CARRY IN OR UP/DOWN OR BINARY/DECADE PRESET ENABLE Q0 OR CARRY OUT su rem /f cl 50% 50% W 20 C ou ONLY TLH 90% 90% 0% 0% PLH V OH V OL THL PHL PLH Figure 2. Swiching Time Tes Circui and Waveforms hp://oemi.com 4
5 MC4029B TIMING DIAGRAM CARRY IN UP/DOWN BINARY/DECADE P0 P P2 P3 Q0 Q Q2 Q3 CARRY OUT COUNT Q3 Q2 Q Q0 C ou MC4029B MSD P3 P2 P P0 CLK Q3 Q2 Q Q0 C ou MC4029B P3 P2 P P0 CLK Q3 Q2 Q Q0 C ou MC4029B LSD P3 P2 P P0 CLK OUTPUT INPUT V " DD V 2" DD 3" C ou (LSD) C ou 2 C ou 3 (MSD) COUNT * W = 5 V Figure 3. Divide by N BCD Down Couner and Timing Diagram (Shown for N = 23) hp://oemi.com 5
6 9 BINARY/DECADE 4 P0 2 P 3 P2 3 P3 PRESET ENABLE hp://oemi.com 6 5 CARRY IN P0 TE Q0 CLK Q0 P TE Q CLK Q P2 TE Q2 CLK Q2 P3 TE Q3 CLK Q3 7 CARRY OUT LOGIC DIAGRAM MC4029B 0 UP/DOWN 5 6 Q0 Q 4 Q2 2 Q3
7 MC4029B PACKAGE DIMENSIONS PDIP 6 P SUFFIX PLASTIC DIP PACKAGE CASE ISSUE T 6 A 8 9 B NOTES:. DIMENSIONING AND TOLERANCING R ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. H G F D 6 PL S C K 0.25 (0.00) M T SEATING T PLANE A M J L M INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G 0.00 BSC 2.54 BSC H BSC.27 BSC J K L M S SOIC 6 D SUFFIX PLASTIC SOIC PACKAGE CASE 75B 05 ISSUE J A B P 8 PL 0.25 (0.00) M B S NOTES:. DIMENSIONING AND TOLERANCING R ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) R SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G K C D 6 PL 0.25 (0.00) M T B S A S M R X 45 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC BSC J K M P R hp://oemi.com 7
8 MC4029B PACKAGE DIMENSIONS SOEIAJ 6 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE ISSUE O e 6 9 Z b D A H E A 0.3 (0.005) M 0.0 (0.004) 8 E VIEW P M L E Q L DETAIL P c NOTES: М. DIMENSIONING AND TOLERANCING R ANSI Y4.5M, 982. М 2. CONTROLLING DIMENSION: MILLIMETER. М 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.5 (0.006) R SIDE. М 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. М 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INCHES DIM MIN MAX MIN MAX A A b c D E e.27 BSC BSC H E L L E M Q Z ON Semiconducor and are regisered rademarks of Semiconducor Compone Indusries, LLC (SCILLC). SCILLC reserves he righ o make changes wihou furher noice o any producs herein. SCILLC makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SCILLC assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, coequenial or incidenal damages. Typical parameers which may be provided in SCILLC daa shees and/or specificaio can and do vary in differen applicaio and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SCILLC does no convey any licee under is paen righs nor he righs of ohers. SCILLC producs are no designed, inended, or auhorized for use as compone in sysems inended for surgical implan ino he body, or oher applicaio inended o suppor or susain life, or for any oher applicaion in which he failure of he SCILLC produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SCILLC producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SCILLC and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agai all claims, coss, damages, and expees, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SCILLC was negligen regarding he design or manufacure of he par. SCILLC is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON Semiconducor P.O. Box 632, Phoenix, Arizona USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderli@oemi.com N. American Technical Suppor: Toll Free USA/Canada Japan: ON Semiconducor, Japan Cusomer Focus Cener 2 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: hp://oemi.com 8 ON Semiconducor Websie: hp://oemi.com Order Lieraure: hp:// For addiional informaion, please conac your local Sales Represenaive. MC4029
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The MC4532B is constructed with complementary MOS (CMOS) enhancement mode devices. The primary function of a priority encoder is to provide a binary address for the active input with the highest priority.
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The SN74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in
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Is Now Par of To learn more abou ON Semiconducor, please visi our websie a www.onsemi.com ON Semiconducor and he ON Semiconducor logo are rademarks of Semiconducor Componens Indusries, LLC dba ON Semiconducor
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