MC74VHC244. Octal Bus Buffer
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1 Ocal Bus Buffer The MC74HC244 is an advanced high speed CMOS ocal bus buffer fabricaed wih silicon gae CMOS echnology. The MC74HC244 is a noninvering 3 sae buffer, and has wo acive low oupu enables. This device is designed o be used wih 3 sae memory address drivers, ec. The inernal circui is composed of hree sages, including a buffer oupu which provides high noise immuniy and sable oupu. The inpus olerae volages up o 7, allowing he inerface of 5 sysems o 3 sysems. High Speed: PD = 3.9 ns (Typ) a CC = 5 Low Power Dissipaion: I CC = 4 A (Max) a T A = 25 C High Noise Immuniy: NIH = NIL = 28% CC Power Down Proecion Provided on Inpus Balanced Propagaion Delays Designed for 2 o Operaing Range Low Noise: OLP = 0.9 (Max) Pin and Funcion Compaible wih Oher Sandard Logic Families Lachup Performance Exceeds 300 ma ESD Performance: Human Body Model > 00 Machine Model > 0 Chip Complexiy: 36 FETs NL Prefix for Auomoive and Oher Applicaions Requiring Unique Sie and Conrol Change Requiremens; AEC Q00 Qualified and PPAP Capable These Devices are Pb Free and are RoHS Complian SOIC DW SUFFIX CASE 75D TSSOP DT SUFFIX CASE 948E MARKING DIAGRAMS HC244 AWLYYWWG HC 244 ALYW HC244 = Specific Device Code A = Assembly Locaion WL, L = Wafer Lo Y = Year WW, W = Work Week G or = Pb Free Package (Noe: Microdo may be in eiher locaion) A 2 8 YA PIN ASSIGNMENT OEA CC A2 A YA2 YA3 A YB4 A OEB YA B4 DATA INPUTS A4 B B YA4 YB YB2 NONINERTING OUTPUTS YB3 5 A3 6 YB2 7 A4 8 YB YA2 B3 YA3 B2 YA4 B3 5 5 YB3 GND 0 B B4 7 3 YB4 ORDERING INFORMATION See deailed ordering and shipping informaion in he Ordering Informaion Table on page 2 of his daa shee. OUTPUT ENABLES OEA OEB 9 Figure. Logic Diagram Semiconducor Componens Indusries, LLC, 3 March, 3 Rev. 9 Publicaion Order Number: MC74HC244/D
2 FUNCTION TABLE INPUTS OUTPUTS OEA, OEB A, B YA, YB L L L L H H H X Z ORDERING INFORMATION MC74HC244DWR2G MC74HC244DTG MC74HC244DTR2G NL74HC244DTR2G* Device Package Shipping SOIC WB (Pb Free) TSSOP (Pb Free) 000/Tape & Reel 75 Unis/Rail 2500/Tape & Reel 2500/Tape & Reel For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD80/D. *NL Prefix for Auomoive and Oher Applicaions Requiring Unique Sie and Conrol Change Requiremens; AEC Q00 Qualified and PPAP Capable. MAXIMUM RATINGS (Noe ) Symbol Parameer alue Uni CC Posiive DC Supply olage 0.5 o +7.0 IN Digial Inpu olage 0.5 o +7.0 OUT DC Oupu olage 0.5 o CC +0.5 I IK Inpu Diode Curren ma I OK Oupu Diode Curren ma I OUT DC Oupu Curren, per Pin 25 ma I CC DC Supply Curren, CC and GND Pins 75 ma P D Power Dissipaion in Sill Air SOIC TSSOP T STG Sorage Temperaure Range 65 o +50 C ESD ESD Wihsand olage Human Body Model (Noe 2) Machine Model (Noe 3) Charged Device Model (Noe 4) >00 >0 >00 I LATCHUP Lachup Performance Above CC and Below GND a 25 C (Noe 5) 300 ma JA Thermal Resisance, Juncion o Ambien SOIC TSSOP Sresses exceeding Maximum Raings may damage he device. Maximum Raings are sress raings only. Funcional operaion above he Recommended Operaing Condiions is no implied. Exended exposure o sresses above he Recommended Operaing Condiions may affec device reliabiliy.. in and ou should be consrained o he range GND ( in or ou ) CC. Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher GND or CC ). Unused oupus mus be lef open. 2. Tesed o EIA/JESD22 A4 A 3. Tesed o EIA/JESD22 A5 A 4. Tesed o JESD22 C0 A 5. Tesed o EIA/JESD mw C/W 2
3 RECOMMENDED OPERATING CONDITIONS Symbol Characerisics Min Max Uni CC DC Supply olage IN DC Inpu olage 0 OUT DC Oupu olage 0 CC T A Operaing Temperaure Range, all Package Types C r, f Inpu Rise or Fall Time CC = CC = ns/ DEICE JUNCTION TEMPERATURE ERSUS TIME TO % BOND FAILURES Juncion Temperaure C Time, Hours Time, Years 80,032, , , , , , ,900.0 NORMALIZED FAILURE RATE FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 30 C TJ = C TJ = 0 C TJ = 00 C TJ = 90 C TJ = 80 C TIME, YEARS Figure 2. Failure Rae vs. Time Juncion Temperaure DC CHARACTERISTICS (olages Referenced o GND) CC T A = 25 C T A 85 C 55 C T A 25 C Symbol Parameer Condiion () Min Typ Max Min Max Min Max Uni IH Minimum High Level Inpu olage o.5 CCX.5 CCX.5 CCX.5 CCX IL Maximum Low Level Inpu olage o 0.5 CCX CCX CCX 0.3 OH Maximum High Level Oupu olage IN = IH or IL I OH = 50 A IN = IH or IL I OH = 4 ma I OH = 8 ma OL Maximum Low Level Oupu olage IN = IH or IL I OL = 50 A IN = IH or IL I OH = 4 ma I OH = 8 ma I IN Inpu Leakage Curren IN = or GND 0 o ± ±.0 ±.0 A I OZ Maximum 3 Sae Leakage Curren IN = IH or IL OUT = CC or GND ±0.25 ±2.5 ±2.5 A I CC Maximum Quiescen Supply Curren (per package) IN = CC or GND A 3
4 Î AC ELECTRICAL CHARACTERISTICS (Inpu r = f = ns) 55 C T A T A = 25 C T Î A 85 C 25 C Symbol Parameer Tes Condiions Min Î Typ Î Max Î Min Max Min Max Î Î Uni PLH, Maximum Propagaion PHL CC = 3.3 ± 0.3 C L = 5 pf Delay, A o YA or Î 5.8Î 8.4Î.0 Î 0.0 Î.0 Î.0 ns C L = 50 pf B o YB Î CC = 5.0 ± 0.5 C L = 5 pf Î C L = 50 pf Î Î Î Î Î Î 7.5Î.0.0 Î Î 9.5 PZL, Oupu Enable Time Î CC = 3.3 ± 0.3 C L = 5 pf PZH OEA o YA or R L = k C L = 50 pf 6.6 Î 9.Î 0.6 Î 4.Î.0 Î 2.5Î Î Î.0 Î 3.5 ns OEB o YB Î CC = 5.0 ± 0.5 C L = 5 pf 4.7Î 7.3Î.0 Î 8.5 Î.0 Î 9.5 R L = k C L = 50 pf PLZ, Oupu Disable Time PHZ OEA o YA or Î CC = 3.3 ± 0.3 C L = 50 pf R L = k 0.3Î Î 4.0Î Î Î Î Î Î ns OEB o YB Î CC = 5.0 ± 0.5 C L = 50 pf Î R L = k 6.7 Î 9.2 Î Î Î Î Î.0.5 OSLH, Oupu o Oupu Skew Î CC = 3.3 ± 0.3 C L = 50 pf.5 Î.5 Î.5 OSHL (Noe 6) ns Î Î CC = 5.0 ± 0.5 C L = 50 pf (Noe 6).0Î Î Î Î Î Î.0.5 Î C in Maximum Inpu Î Î Capaciance 4 Î 0 Î Î 0 Î Î 0 pf C ou Maximum Three Sae 6 Î Î Î Î pf Oupu Capaciance Î (Oupu in High ImpedanceÎ Î Sae) Î C PD Power Dissipaion Capaciance (Noe 7) 25 C, CC = Parameer guaraneed by design. OSLH = PLHm PLHn, OSHL = PHLm PHLn. 7. C PD is defined as he value of he inernal equivalen capaciance which is calculaed from he operaing curren consumpion wihou load. Average operaing curren can be obained by he equaion: I CC(OPR) = C PD CC f in + I CC / 8 (per bi). C PD is used o deermine he no load dynamic power consumpion; P D = C PD CC 2 f in + I CC CC. NOISE CHARACTERISTICS (Inpu r = f = ns, C L = 50 pf, CC = 5.0 ) Symbol Parameer 9 T A = 25 C OLP Quie Oupu Maximum Dynamic OL OL Quie Oupu Minimum Dynamic OL IHD Minimum High Level Dynamic Inpu olage 3.5 ILD Maximum Low Level Dynamic Inpu olage.5 Typ Max pf Uni 4
5 SWITCHING WAEFORMS A or B YA or YB PLH 50% 50% CC PHL CC GND OEA or OEB YA or YB YA or YB 50% PZL 50% CC PZH 50% CC PLZ PHZ CC GND HIGH IMPEDANCE OL +0.3 OH -0.3 HIGH IMPEDANCE Figure 3. Swiching Waveform Figure 4. Swiching Waveform TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C L * DEICE UNDER TEST OUTPUT k C L * CONNECT TO CC WHEN TESTING PLZ AND PZL. CONNECT TO GND WHEN TESTING PHZ AND PZH. *Includes all probe and jig capaciance *Includes all probe and jig capaciance Figure 5. Tes Circui Figure 6. Tes Circui INPUT Figure 7. Inpu Equivalen Circui 5
6 PACKAGE DIMENSIONS SOIC WB DW SUFFIX CASE 75D 05 ISSUE G D A H 0X 0.25 M B M 0 E h X 45 NOTES:. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME YM, DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 5 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 3 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. X B 0.25 M T A S 8X e B B S A A T SEATING PLANE C L MILLIMETERS DIM MIN MAX A A B C D E e.27 BSC H h L
7 PACKAGE DIMENSIONS 5 (0.006) T L 5 (0.006) T U 2X L/2 PIN IDENT U S S C 00 (0.004) T SEATING PLANE X K REF 0 (0.004) M T U S S 0 A D G H TSSOP CASE 948E 02 ISSUE C B U N J J N K K ÍÍÍÍ ÍÍÍÍ SECTION N N F DETAIL E 0.25 (0.00) DETAIL E SOLDERING FOOTPRINT 7.06 M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC W H J J K K L 6.40 BSC BSC M PITCH 6X X.26 DIMENSIONS: MILLIMETERS ON Semiconducor and are regisered rademarks of Semiconducor Componens Indusries, LLC (SCILLC). SCILLC owns he righs o a number of paens, rademarks, copyrighs, rade secres, and oher inellecual propery. A lising of SCILLC s produc/paen coverage may be accessed a Marking.pdf. SCILLC reserves he righ o make changes wihou furher noice o any producs herein. SCILLC makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SCILLC assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Typical parameers which may be provided in SCILLC daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SCILLC does no convey any license under is paen righs nor he righs of ohers. SCILLC producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he SCILLC produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SCILLC producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SCILLC and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SCILLC was negligen regarding he design or manufacure of he par. SCILLC is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON Semiconducor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderli@onsemi.com N. American Technical Suppor: Toll Free USA/Canada Europe, Middle Eas and Africa Technical Suppor: Phone: Japan Cusomer Focus Cener Phone: ON Semiconducor Websie: Order Lieraure: hp:// For addiional informaion, please conac your local Sales Represenaive MC74HC244/D
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NSN N-Channel Logic Level Enhancemen Mode Field Effec Transisor General escripion Feaures These N-Channel logic level enhancemen mode power field effec ransisors are produced using ON Semiconducor's proprieary,
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M74H273A Ocal D Flip Flop wih ommon lock and Rese High Performance Silicon Gae MOS The M74H273A is idenical in pinou o he LS273. The device inpus are compaible wih sandard MOS oupus; wih pullup resisors,
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Small Signal Fas Swiching Diode Feaures These diodes are also available in oher case syles including he DO- case wih he ype designaion N8, he MiniMELF case wih he ype designaion LL8, and he SOT- case wih
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Dual 4 Sage Binary Ripple ouner High Performance Silicon Gae MOS The M74H393A is idenical in pinou o he LS393. The device inpus are compaible wih sandard MOS oupus; wih pullup resisors, hey are compaible
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Dual 2-Input AND Gate The is a high performance dual 2 input AND Gate operating from a.65 to 5.5 supply. Features Extremely igh Speed: t PD 2.5 ns (typical) at = 5 Designed for.65 to 5.5 Operation Over
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High Performance Silicon Gae MOS The M7H7A is idenical in pinou o he LS7. The device inpus are compaible wih sandard MOS oupus; wih pull up resisors, hey are compaible wih LSTTL oupus. This device coiss
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