MC14174B/D. Hex Type D Flip Flop
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- Bartholomew Price
- 5 years ago
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1 7B Hex Type D FlipFlop The 7B hex ype D flipflop is coruced wih OS Pchannel and Nchannel enhancemen mode devices in a single monolihic srucure. Daa on he D inpus which mees he seup ime requireme is raferred o he Q oupus on he posiive edge of he clock pulse. All six flipflops share common clock and rese inpus. The rese is acive low, and independen of he clock. Feaures Saic Operaion All Inpus and Oupus Buffered Diode Proecion on All Inpus Supply Volage Range =.0 o 8 apable of Driving Two LowPower TTL Loads or One LowPower Schoky TTL Load Over he Raed Temperaure Range Funcional Equivalen o TTL 77 PbFree Packages are Available* AXIU RATINGS olages Referenced o V SS ) Parameer Symbol Value Uni D Supply Volage Range V DD 0. o +8.0 V Inpu or Oupu Volage Range (D or Traien) Inpu or Oupu urren (D or Traien) per Pin V in, V ou 0. o V DD + 0. I in, I ou ± ma Power Dissipaion, per Package (Noe ) P D 00 mw Ambien Temperaure Range T A o + Sorage Temperaure Range 6 o +0 Lead Temperaure (8Second Soldering) 60 Sresses exceeding aximum Raings may damage he device. aximum Raings are sress raings only. Funcional operaion above he Recommended Operaing ondiio is no implied. Exended exposure o sresses above he Recommended Operaing ondiio may affec device reliabiliy.. Temperaure Deraing: Plasic P and D/DW Packages: 7.0 mw/ From 6 To This device conai proecion circuiry o guard agai damage due o high saic volages or elecric fields. However, precauio mus be aken o avoid applicaio of any volage higher han maximum raed volages o his highimpedance circui. For proper operaion, V in and V ou should be corained o he range V SS in or V ou ) V DD. Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher V SS or V DD ). Unused oupus mus be lef open. V hp://oemi.com ORDERING INFORATION Device Package Shipping 7BP PDIP6 Unis/Rail 7BPG 7BD SOI6 8 Unis/Rail 7BDG 7BDR SOI6 00/Tape & Reel 7BDRG PDIP6 P SUFFIX ASE 68 A = Assembly Locaion WL = Wafer Lo YY, Y = Year WW = Work Week G = PbFree Package PDIP6 (PbFree) SOI6 (PbFree) SOI6 (PbFree) 6 6 SOI6 D SUFFIX ASE 7B ARKING DIAGRAS 7BP AWLYYWWG 7BG AWLYWW Unis/Rail 8 Unis/Rail 00/Tape & Reel For informaion on ape and reel specificaio, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaio Brochure, BRD80/D. *For addiional informaion on our PbFree sraegy and soldering deails, please download he ON Semiconducor Soldering and ouning Techniques Reference anual, SOLDERR/D. Semiconducor ompone Indusries, LL, 006 June, 006 Rev. 6 Publicaion Order Number: 7B/D
2 7B TRUTH TABLE (Posiive Logic) Inpus Oupu lock Daa Rese Q 0 0 X Q X X 0 0 X = Don are R Q0 D0 D Q D Q V SS Figure. Pin Assignmen No hange V DD Q D D Q D Q 6 LOK RESET D0 D D D D D Q0 Q Q Q Q Q V DD = PIN 6 V SS = PIN 8 Figure. Block Diagram 7 Figure. Timing Diagram Figure. Funcional Block Diagram hp://oemi.com
3 7B ELETRIAL HARATERISTIS olages Referenced o V SS ) ÎÎ ÎÎ V DD ÎÎ Typ haracerisic Symbol Î in ax in (Noe ) ax in ax Uni Oupu Volage 0 Level V V in = V DD or 0 Î OL Î 0 Î ÎÎ 0.0Î 0 Î Level V in = 0 or V DD Î V OH. Î. Î.... ÎÎ. Î. Î. Inpu Volage 0 Level Î V IL Î O =. or 0. ).... O =.0 or.0 ).0Î.0Î.0.0 O =. or. ).0Î 6.7Î.0.0 Level O = 0. or. ) Î V IH Î O =.0 or.0 ) O =. or. ) Î Î Oupu Drive urren I OH =. ) Source Î OH madc.0 Î..Î.7 OH =.6 ) OH Î =. ) OH =. ).. 8.8Î. OL = 0. ) Sink OL = 0. ) Î I OL 0.6 Î Î 0.6 madc OL =. ). Î. 8.8Î. Inpu urren Î I in ± 0.Î ±0.0000Î ± 0. ±.0 Adc Inpu apaciance, in = 0) Î in Î Î 7. pf Quiescen urren Î I DD (Per Package) ÎÎ 0.00Î 0.0 0Î 0.0Î Adc Toal Supply urren (Noe, ) Î I T Î I T = (. A/kHz) f + I DD Adc (Dynamic plus Quiescen, Î I T = (. A/kHz) f + I DD Per Package) I ( L = 0 pf on all oupus, all ÎÎ T = (.7 A/kHz) f + I DD buffers swiching). Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he I s poenial performance.. The formulas given are for he ypical characerisics only a.. To calculae oal supply curren a loads oher han 0 pf: I T ( L ) = I T (0 pf) + ( L 0) Vfk where: I T is in A (per package), L in pf, V = DD V SS ) in vols, f in khz is inpu frequency, and k = hp://oemi.com
4 7B SWITHING HARATERISTIS (Noe ) ( L = 0 pf, T A = ) Î All Types ÎÎ V DD Î Î Typ Î haracerisic Symbol in (Noe 6) ax Uni Oupu Rise and Fall Time TLH, THL Î Î Î ÎÎ TLH, THL = (. /pf) L + ÎÎ Î Î 0 Î 00 ÎÎ TLH, THL = (0.6 /pf) L TLH, THL = (0. /pf) L + 0 ÎÎ Î Î 0 Î 80 ÎÎ Propagaion Delay Time lock o Q ÎÎ PLH, PHL Î Î Î ÎÎ PLH, PHL = (0. /pf) L PLH, PHL = (0.6 /pf) L + 6 ÎÎ Î Î 8 Î 60 ÎÎ PLH, PHL = (0.6 /pf) L Propagaion Delay Time Rese o Q ÎÎ PHL = (0. /pf) L + 0 ÎÎ PHL Î Î Î 0 Î 00 ÎÎ PHL = (0.6 /pf) L + 7 PHL = (0.6 /pf) L ÎÎ Î Î 0 Î ÎÎ lock Pulse Widh ÎÎ WH Î Î 0 Î 7 Î ÎÎ Î 0 Î Î 70 Rese Pulse Widh WL Î Î Î 00 0 ÎÎ Î 0 Î 0 Î 80 0 lock Pulse Frequency f cl Î Î Î ÎÎ Î Î Î mhz. 6. lock Pulse Rise and Fall Time TLH, THL Î Î Î ÎÎ Î Î Î s.0 Daa Seup Time su 0 0 Î Î 0 Î Î 0 Daa Hold Time h 80 0 Î Î 0 Î 0 Î 0 Rese Removal Time rem 0 Î Î Î The formulas given are for he ypical characerisics only a. 6. Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he I s poenial performance. 0 0 hp://oemi.com
5 7B PAKAGE DIENSIONS PDIP6 ASE 6808 ISSUE T A 6 8 B NOTES:. DIENSIONING AND TOLERANING PER ANSI Y., 8.. ONTROLLING DIENSION: INH.. DIENSION L TO ENTER OF LEADS WHEN FORED PARALLEL.. DIENSION B DOES NOT INLUDE OLD FLASH.. ROUNDED ORNERS OPTIONAL. H G F D 6 PL S K 0. (0.0) T SEATING T PLANE A J L INHES ILLIETERS DI IN AX IN AX A B D F G 0.0 BS. BS H 0.00 BS.7 BS J K L S SOI6 ASE 7B0 ISSUE J A 6 8 B P 8 PL 0. (0.0) B S NOTES:. DIENSIONING AND TOLERANING PER ANSI Y., 8.. ONTROLLING DIENSION: ILLIETER.. DIENSIONS A AND B DO NOT INLUDE OLD PROTRUSION.. AXIU OLD PROTRUSION 0. (0.006) PER SIDE.. DIENSION D DOES NOT INLUDE DABAR PROTRUSION. ALLOWABLE DABAR PROTRUSION SHALL BE 0.7 (0.00) TOTAL IN EXESS OF THE D DIENSION AT AXIU ATERIAL ONDITION. T SEATING PLANE G K D 6 PL 0. (0.0) T B S A S R X J F ILLIETERS INHES DI IN AX IN AX A B D F G.7 BS 0.00 BS J K P R ON Semiconducor and are regisered rademarks of Semiconducor ompone Indusries, LL (SILL). SILL reserves he righ o make changes wihou furher noice o any producs herein. SILL makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SILL assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, coequenial or incidenal damages. Typical parameers which may be provided in SILL daa shees and/or specificaio can and do vary in differen applicaio and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SILL does no convey any licee under is paen righs nor he righs of ohers. SILL producs are no designed, inended, or auhorized for use as compone in sysems inended for surgical implan ino he body, or oher applicaio inended o suppor or susain life, or for any oher applicaion in which he failure of he SILL produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SILL producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SILL and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agai all claims, coss, damages, and expees, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SILL was negligen regarding he design or manufacure of he par. SILL is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLIATION ORDERING INFORATION LITERATURE FULFILLENT: Lieraure Disribuion ener for ON Semiconducor P.O. Box 6, Denver, olorado 807 USA Phone: 0677 or Toll Free USA/anada Fax: or Toll Free USA/anada orderli@oemi.com N. American Technical Suppor: Toll Free USA/anada Europe, iddle Eas and Africa Technical Suppor: Phone: 70 Japan usomer Focus ener Phone: hp://oemi.com ON Semiconducor Websie: Order Lieraure: hp:// For addiional informaion, please conac your local Sales Represenaive 7B/D
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MC14060B. 14 Bit Binary Counter and Oscillator
4Bit Binary Counter and Oscillator The MC4060B is a 4stage binary ripple counter with an onchip oscillator buffer. The oscillator configuration allows design of either RC or crystal oscillator circuits.
MC14516B. Binary Up/Down Counter
M456B Binary Up/Down ounter The M456B synchronous up/down binary counter is cotructed with MOS Pchannel and Nchannel enhancement mode devices in a monolithic structure. This counter can be preset by applying
MC14049B, MC14050B. Hex Buffer
MC4049B, MC4050B Hex Buffer The MC4049B Hex Inverter/Buffer and MC4050B Noninverting Hex Buffer are constructed with MOS PChannel and NChannel enhancement mode devices in a single monolithic structure.
MC74VHC1GT125. Noninverting Buffer / CMOS Logic Level Shifter with LSTTL Compatible Inputs
C74CGT Noninvering Buffer / COS ogic evel Shifer wih STT Compaible Inpus The C74CGT is a single gae noninvering buffer fabricaed wih silicon gae COS echnology. I achieves high speed operaion similar o
MC14543B. BCD-to-Seven Segment Latch/Decoder/Driver for Liquid Crystals
M4543B BD-to-Seven Segment Latch/Decoder/Driver for Liquid rystals The M4543B BDtoseven segment latch/decoder/driver is designed for use with liquid crystal readouts, and is cotructed with complementary
MC14175B. MARKING DIAGRAMS. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) ORDERING INFORMATION PDIP 16 P SUFFIX CASE 648
The MC14175B quad type D flip flop is cotructed with MOS P channel and N channel enhancement mode devices in a single monolithic structure. Each of the four flip flops is positive edge triggered by a common
NE522 High Speed Dual Differential Comparator/Sense Amp
HighSpeed DualDifferential Comparator/Sense Amp Features 5 ns Maximum Guaranteed Propagation Delay 0 A Maximum Input Bias Current TTL-Compatible Strobes and Outputs Large Common-Mode Input oltage Range
HV513 8-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs, POL, Hi-Z, and Short Circuit Detect
H513 8-Channel Serial o Parallel Converer wih High olage Push-Pull s, POL, Hi-Z, and Shor Circui Deec Feaures HCMOS echnology Operaing oupu volage of 250 Low power level shifing from 5 o 250 Shif regiser
MC74AC109, MC74ACT109. Dual JK Positive Edge Triggered Flip Flop
MC9, MC9 Dual JK Positive EdgeTriggered FlipFlop The MC9/9 coists of two highspeed completely independent traition clocked JK flipflops. The clocking operation is independent of rise and fall times of
SN74LS151MEL. 8 Input Multiplexer LOW POWER SCHOTTKY
8 Input Multiplexer The TTL/MSI SN74LS5 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS5 can be used as
MC14557B. 1-to-64 Bit Variable Length Shift Register
MC -to- it Variable Length Shift Register The MC is a static clocked serial shift register whose length may be programmed to be any number of bits between and. The number of bits selected is equal to the
SN74LS147, SN74LS Line to 4 Line and 8 Line to 3 Line Priority Encoders LOW POWER SCHOTTKY
0 Line to Line and 8 Line to 3 Line Priority Encoders The SN7LS7 and the SN7LS8 are Priority Encoders. They provide priority decoding of the inputs to eure that only the highest order data line is encoded.
MC74AC132, MC74ACT132. Quad 2 Input NAND Schmitt Trigger
MC74AC32, MC74ACT32 Quad 2 Input NAND Schmitt Trigger The MC74AC/74ACT32 contains four 2 input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter free
SN74LS145MEL. 1 of 10 Decoder/Driver Open Collector LOW POWER SCHOTTKY
of 0 Decoder/Driver Open Collector The SN74LS45, -of-0 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 0-digit incandescent displays. All outputs remain off for
MC14532B. MARKING DIAGRAMS. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) ORDERING INFORMATION PDIP 16 P SUFFIX CASE 648
The MC4532B is constructed with complementary MOS (CMOS) enhancement mode devices. The primary function of a priority encoder is to provide a binary address for the active input with the highest priority.
74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
MC14521B. 24 Stage Frequency Divider
24Stage Frequency Divider The coists of a chain of 24 flipflops with an input circuit that allows three modes of operation. The input will function as a crystal oscillator, an C oscillator, or as an input
74HC244 Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with
MC14511B. BCD To Seven Segment Latch/Decoder/Driver
BCDToSeven Segment Latch/Decoder/Driver The MC45B BCDtoseven segment latch/decoder/driver is cotructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single
74HC of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The 74HC38 is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in
MC74AC74, MC74ACT74. Dual D Type Positive Edge Triggered Flip Flop
Dual D Type Positive Edge Triggered Flip Flop The MC74AC74/74ACT74 is a dual D type flip flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is traferred
SN74LS157MEL. Quad 2 Input Multiplexer LOW POWER SCHOTTKY
Quad 2 Input Multiplexer The LSTTL/ MSI is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs
MC14518B. MARKING DIAGRAMS 16. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) ORDERING INFORMATION
The MC14518B dual BCD counter and the MC14520B dual binary counter are cotructed with MOS P channel and N channel enhancement mode devices in a single monolithic structure. Each coists of two identical,
MC74HC132A. Quad 2 Input NAND Gate with Schmitt Trigger Inputs. High Performance Silicon Gate CMOS
Quad 2 Input NAND Gate with Schmitt Trigger Inputs High Performance Silicon Gate CMOS The is identical in pinout to the LS32. The device inputs are compatible with standard CMOS outputs; with pull up resistors,
MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B
MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary
SN74LS132MEL. Quad 2 Input Schmitt Trigger NAND Gate LOW POWER SCHOTTKY
Quad 2 Input Schmitt Trigger NAND Gate The SN74LS32 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly
AMIS LIN Transceiver
AMIS-000 Transceiver General Descripion The single wire ransceiver AMIS 000 is a monolihic inegraed circui in a SOIC 8 package. I works as an inerface beween he proocol conroller and he physical bus. The
MC10H Bit Arithmetic Logic Unit/ Function Generator
C0H8 4Bit Arithmetic Logic Unit/ unction Generator The C0H8 is a highspeed arithmetic logic unit capable of performing 6 logic operatio and 6 arithmetic operatio on two fourbit words. ull internal carry
NLSV2T Bit Dual-Supply Inverting Level Translator
2-Bit Dual-Supply Inverting Level Translator The NLSV2T240 is a 2 bit configurable dual supply voltage level translator. The input A n and output B n ports are designed to track two different power supply
MC74HCT138A. 1 of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC74HCT38A is identical in pinout to the LS38. The HCT38A may be used as a level converter for interfacing
Type Marking Pin Configuration Package SMBT3904/MMBT3904 SOT23 SMBT3904S 2=E 1=B 3=C 1=E1 2=B1 3=C2
SMBT94...MMBT94 NPN Silicon Swiching Transisors High D curren gain:. ma o ma Low collecoremier sauraion volage For SMBT94S: Two (galvanic) inernal isolaed ransisors wih good maching in one package omplemenary
MC74AC259, MC74ACT Bit Addressable Latch
8 Bit Addressable Latch The MC74AC259/74ACT259 is a high speed 8 bit addressable latch designed for general purpose storage applicatio in digital systems. It is a multifunctional device capable of storing
MC Bit Magnitude Comparator
Bit Magnitude Comparator The MC0 is a high speed expandable bit comparator for comparing the magnitude of two binary words. Two outputs are provided: and. A = B can be obtained by NORing the two outputs
MC14553B. 3-Digit BCD Counter
MB -Digit BD ounter The MB digit BD counter coists of negative edge triggered BD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count.
LOW POWER SCHOTTKY. ESD > 3500 Volts. GUARANTEED OPERATING RANGES ORDERING INFORMATION V CC 8 7 GND
ESD > 3500 Volts V CC 8 4 3 2 0 9 LOW POWER SCHOTTKY 2 3 4 5 6 7 GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage 4.75 5.0 5.25 V T A Operating Ambient Temperature
PI74STX1G126. SOTiny Gate STX Buffer with 3-State Output. Features. Descriptio n. Block Diagram. Pin Configuration
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SN74LS373, SN74LS374. Octal Transparent Latch with 3 State Outputs; Octal D Type Flip Flop with 3 State Output LOW POWER SCHOTTKY
Octal Transparent Latch with 3 State Outputs; Octal Type Flip Flop with 3 State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops
LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES ORDERING INFORMATION. SN74LS37xN AWLYYWW PDIP 20 N SUFFIX CASE 738
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is
High Speed Optocoupler, 1 MBd, Photodiode with Transistor Output. i179081
High Speed Opocoupler, MBd, Phoodiode wih Transisor Oupu Feaures Isolaion Tes Volage: V RMS TTL Compaible High Bi Raes:. Mbi/s High Common-Mode Inerference Immuniy Bandwidh. MHz Open-Collecor Oupu Exernal
MC74HC138A. 1-of-8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
MC74HC38A -of-8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The MC74HC38A is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
MC74HC4020A. 14-Stage Binary Ripple Counter. High Performance Silicon Gate CMOS
M74H20A 4-Stage Binary Ripple ounter High Performance Silicon Gate MOS The M7420A is identical in pinout to the standard MOS M20B. The device inputs are compatible with standard MOS outputs; with pullup