MC74HC573A. Octal 3 State Noninverting Transparent Latch. High Performance Silicon Gate CMOS
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1 Ocal 3 Sae Noninvering Transparen Lach High Performance Silicon Gae CMOS The MC74HC573A is idenical in pinou o he LS573. The devices are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible wih LSTTL oupus. These laches appear ransparen o daa (i.e., he oupus change asynchronously) when Lach Enable is high. When Lach Enable goes low, daa meeing he seup and hold ime becomes lached. The HC573A is idenical in funcion o he HC373A bu has he daa inpus on he opposie side of he package from he oupus o faciliae PC board layou. Feaures Oupu Drive Capabiliy: 5 LSTTL Loads Oupus Direcly Inerface o CMOS, NMOS and TTL Operaing Volage Range: 2.0 o 6.0 V Low Inpu Curren:.0 A In Compliance wih he JEDEC Sandard No. 7.0 A Requiremens Chip Complexiy: 28 FETs or 54.5 Equivalen Gaes Pb Free Packages are Available* hp://onsemi.com PDIP N SUFFIX CASE 738 SOIC DW SUFFIX CASE 75D MARKING DIAGRAMS MC74HC573AN AWLYYWWG 74HC573A AWLYYWWG TSSOP DT SUFFIX CASE 948E HC 573A ALYW SOEIAJ F SUFFIX CASE HC573A AWLYWWG A = Assembly Locaion WL, L = Wafer Lo YY, Y = Year WW, W = Work Week G = Pb Free Package = Pb Free Package (Noe: Microdo may be in eiher locaion) ORDERING INFORMATION See deailed ordering and shipping informaion in he package dimensions secion on page 2 of his daa shee. *For addiional informaion on our Pb Free sraegy and soldering deails, please download he ON Semiconducor Soldering and Mouning Techniques Reference Manual, SOLDERRM/D. Semiconducor Componens Indusries, LLC, 05 July, 05 Rev. Publicaion Order Number: MC74HC573A/D
2 PIN ASSIGNMENT OUTPUT D0 2 D 3 D2 4 D3 5 D4 6 D5 7 D Q0 Q Q2 Q3 Q4 Q5 Q6 Design Crieria Value Unis Inernal Gae Coun* 54.5 ea. Inernal Gae Progaion Delay.5 ns Inernal Gae Power Dissipaion 5.0 W Speed Power Produc pj *Equivalen o a wo inpu NAND gae. D Q7 LATCH LOGIC DIAGRAM FUNCTION TABLE Inpus Oupu Oupu Lach Enable Enable D Q L H H H L H L L L L X No Change H X X Z X = Don Care Z = High Impedance DATA INPUTS D0 D D2 D3 D4 D5 D6 D7 LATCH OUTPUT 2 9 Q0 3 8 Q 4 7 Q2 5 6 Q3 6 5 Q4 7 4 Q5 8 3 Q6 9 2 Q7 PIN = PIN 0 = NONINVERTING OUTPUTS ORDERING INFORMATION Device Package Shipping MC74HC573AN PDIP 8 Unis / Rail MC74HC573ANG SOIC (Pb Free) 8 Unis / Rail MC74HC573ADW SOIC WIDE 38 Unis / Rail MC74HC573ADWG SOIC WIDE (Pb Free) 38 Unis / Rail MC74HC573ADWR2 SOIC WIDE 000 Tape & Reel MC74HC573ADWR2G SOIC WIDE (Pb Free) 000 Tape & Reel MC74HC573ADT TSSOP * 75 Unis / Rail MC74HC573ADTG TSSOP * 75 Unis / Rail MC74HC573ADTR2 TSSOP * 2500 Tape & Reel MC74HC573ADTR2G TSSOP * 2500 Tape & Reel MC74HC573AFEL SOEIAJ 00 Tape & Reel MC74HC573AFELG SOEIAJ (Pb Free) 00 Tape & Reel For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD80/D. *This package is inherenly Pb Free. hp://onsemi.com 2
3 MAXIMUM RATINGS Symbol Parameer Î Value Uni DC Supply Volage (Referenced o ) Î 0.5 o V V in DC Inpu Volage (Referenced o ) 0.5 o V V ou DC Oupu Volage (Referenced o ) 0.5 o V I in DC Inpu Curren, per Pin ± ma I ou DC Oupu Curren, per Pin Î ± 35 ma I CC DC Supply Curren, and Pins Î ± 75 ma P D Power Dissipaion in Sill Air, Plasic DIP Î 750 mw SOIC Package 500 Î TSSOP Package Î 450 T sg Sorage Temperaure Î 65 o + 50 C T L Lead Temperaure, mm from Case for 0 Seconds C Î (Plasic DIP, TSSOP or SOIC Package) 260 Maximum raings are hose values beyond which device damage can occur. Maximum raings applied o he device are individual sress limi values (no normal operaing condiions) and are no valid simulaneously. If hese limis are exceeded, device funcional operaion is no implied, damage may occur and reliabiliy may be affeced. Deraing Plasic DIP: 0 mw/ C from 65 o 25 C SOIC Package: 7 mw/ C from 65 o 25 C TSSOP Package: 6. mw/ C from 65 o 25 C For high frequency or heavy load consideraions, see Chaper 2 of he ON Semiconducor High Speed CMOS Daa Book (DL29/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameer Min Max Uni DC Supply Volage (Referenced o ) V V in, V ou DC Inpu Volage, Oupu Volage (Referenced o ) 0 V T A Operaing Temperaure, All Package Types C r, f Inpu Rise and Fall Time V CC = 2.0 V ns (Figure ) = 4.5 V Î = 6.0 V DC ELECTRICAL CHARACTERISTICS (Volages Referenced o ) Guaraneed Limi 55 o Symbol Parameer Tes Condiions V 25 C 85 C 25 C Uni V IH Minimum High Level Inpu Volage Î V ou = 0. V or 0. V V I Î ou A V IL Maximum Low Level Inpu Volage Î Î V ou = 0. V or 0. V V I ou A V OH Minimum High Level Oupu Î V in = V IH or V IL Î Volage Î I ou A Î V Î V in = V IH or V IL I ou 2.4mA Î I ou 6.0 ma I ou ma V OL Maximum Low Level Oupu Î V ou = 0. V or 0. V Î Volage Î I ou A Î V Î V in = V IH or V IL I ou 2.4mA Î I ou 6.0 ma I ou ma I in Maximum Inpu Leakage Curren Î V in = or 6.0 ± 0. ±.0 ±.0 A I OZ Maximum Three Sae Leakage Î Oupu in High Impedance Sae Curren V Î in = V IL or V IH V ou = or A I CC Maximum Quiescen Supply Î V in = or A Curren (per Package) II ou I = 0 A This device conains proecion circuiry o guard agains damage due o high saic volages or elecric fields. However, precauions mus be aken o avoid applicaions of any volage higher han maximum raed volages o his high impedance circui. For proper operaion, V in and V ou should be consrained o he range (V in or V ou ). Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher or ). Unused oupus mus be lef open. NOTE: Informaion on ypical parameric values can be found in Chaper 2 of he ON Semiconducor High Speed CMOS Daa Book (DL29/D). hp://onsemi.com 3
4 AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Inpu r = f = 6.0 ns) Guaraneed Limi Symbol Parameer V 55 o 25 C 85 C 25 C Uni Î PLH, Maximum Propagaion Delay, Inpu D o Q ns PHL Î (Figures and 5) 3.0Î Î PLH, Î Maximum Propagaion Delay, Lach Enable o Q 2.0Î ns PHL Î (Figures 2 and 5) 3.0Î Î PLZ, Î Maximum Propagaion Delay, Oupu Enable o Q 2.0Î ns PHZ (Figures 3 and 6) Î PZL, Î Maximum Propagaion Delay, Oupu Enable o Q 2.0Î ns PZH (Figures 3 and 6) Î Î TLH, Maximum Oupu Transiion Time, Any Oupu ns THL (Figures and 5) Î Î C in Maximum Inpu Capaciance pf C ou Î Maximum 3 Sae Oupu Capaciance (Oupu in High Impedance Sae) pf NOTE: For propagaion delays wih loads oher han 50 pf, and informaion on ypical parameric values, see Chaper 2 of he ON Semiconducor High Speed CMOS Daa Book (DL29/D). 25 C, = 5.0 V C PD Power Dissipaion Capaciance (Per Enabled Oupu)* 23 pf * Used o deermine he no load dynamic power consumpion: P D = C PD V 2 CC f + I CC. For load consideraions, see Chaper 2 of he ON Semiconducor High Speed CMOS Daa Book (DL29/D). Î TIMING REQUIREMENTS (C L = 50 pf, Inpu r = f = 6.0 ns) Guaraneed Limi Î 55 o 25 C Î 85 C 25 C Symbol Parameer Figure V Min Max Min Max Min Max Uni Î su Minimum Seup Time, Inpu D o Lach Enable ns Î h Minimum Hold Time, Lach Enable o Inpu D ns Î Î w Minimum Pulse Widh, Lach Enable ns Î Î r, f Maximum Inpu Rise and Fall Times ns Î Î hp://onsemi.com 4
5 SWITCHING WAVEFORMS INPUT D r 0% 90% f LATCH w Q PLH 0% 90% PHL PLH PHL TLH THL Q Figure. Figure 2. OUTPUT Q Q.3 V PZL PZH PLZ PHZ 0% 90% 3.0 V HIGH IMPEDANCE V OL V OH HIGH IMPEDANCE INPUT D LATCH Figure 3. Figure 4. SU VALID h TEST POINT D0 2 D 9 Q0 DEVICE UNDER TEST OUTPUT C L * D 3 D 8 Q D2 4 D 7 Q2 *Includes all probe and jig capaciance Figure 5. Tes Circui D3 5 D 6 Q3 D4 6 D 5 Q4 D5 7 D 4 Q5 DEVICE UNDER TEST TEST POINT OUTPUT k C L * CONNECT TO WHEN TESTING PLZ AND PZL. CONNECT TO WHEN TESTING PHZ AND PZH. D6 8 D 3 Q6 D7 9 D 2 Q7 LATCH *Includes all probe and jig capaciance OUTPUT Figure 6. Tes Circui Figure 7. EXPANDED LOGIC DIAGRAM hp://onsemi.com 5
6 PACKAGE DIMENSIONS PDIP N SUFFIX PLASTIC DIP PACKAGE CASE ISSUE E A 0 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. T SEATING PLANE G E F N K C D PL 0.25 (0.00) M T A M L M J PL 0.25 (0.00) M T B M INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D E BSC.27 BSC F G 0.00 BSC 2.54 BSC J K L BSC 7.62 BSC M N SOIC DW SUFFIX CASE 75D 05 ISSUE G H 0X 0.25 M B M D E A h X 45 NOTES:. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y4.5M, DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.3 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. X B 0.25 M T A S 8X e 0 B B S A A T SEATING PLANE C L MILLIMETERS DIM MIN MAX A A B C D E e.27 BSC H h L hp://onsemi.com 6
7 PACKAGE DIMENSIONS TSSOP DT SUFFIX CASE 948E 02 ISSUE B 0.5 (0.006) T L U 2X L/2 0.5 (0.006) T U S PIN IDENT S C 0.00 (0.004) T SEATING PLANE X K REF 0.0 (0.004) M T U S V S 0 A V D G H B U J J N N K K ÍÍÍÍ ÍÍÍÍ SECTION N N F DETAIL E 0.25 (0.00) DETAIL E M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M hp://onsemi.com 7
8 PACKAGE DIMENSIONS SOEIAJ F SUFFIX CASE ISSUE O e E H E 0 Z D A L E Q M L DETAIL P VIEW P c NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.08). b A 0.3 (0.005) M 0.0 (0.004) MILLIMETERS INCHES DIM MIN MAX MIN MAX A A b c D E e.27 BSC BSC H E L L E M Q Z ON Semiconducor and are regisered rademarks of Semiconducor Componens Indusries, LLC (SCILLC). SCILLC reserves he righ o make changes wihou furher noice o any producs herein. SCILLC makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SCILLC assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Typical parameers which may be provided in SCILLC daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SCILLC does no convey any license under is paen righs nor he righs of ohers. SCILLC producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he SCILLC produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SCILLC producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SCILLC and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SCILLC was negligen regarding he design or manufacure of he par. SCILLC is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON Semiconducor P.O. Box 632, Phoenix, Arizona USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderli@onsemi.com N. American Technical Suppor: Toll Free USA/Canada Japan: ON Semiconducor, Japan Cusomer Focus Cener 2 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: hp://onsemi.com 8 ON Semiconducor Websie: hp://onsemi.com Order Lieraure: hp:// For addiional informaion, please conac your local Sales Represenaive. MC74HC573A/D
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MC14099B. 8 Bit Addressable Latches
MC0B Bi ddressable Laches The MC0B is an bi addressable lach. Daa is enered in serial form when he appropriae lach is addressed (via address pi 0,, ) and wrie disable is in he low sae. For he MC0B he inpu
Quad 2-Input OR Gate High-Performance Silicon-Gate CMOS
TECNICAL DATA Quad 2-Inpu OR ae igh-performance Silicon-ae CMOS The is idenical in pinou o he LS/ALS32. The device inpus are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible wih
MC74HC373A. Octal 3 State Non Inverting Transparent Latch. High Performance Silicon Gate CMOS
Octal 3 State Non Inverting Transparent Latch High Performance Silicon Gate CMOS The MC74HC373A is identical in pinout to the LS373. The device inputs are compatible with standard CMOS outputs; with pullup
MC74AC138, MC74ACT of 8 Decoder/Demultiplexer
1 of 8 Decoder/Demultiplexer The MC74AC138/74ACT138 is a high speed 1 of 8 decoder/demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple
MC74VHC257. Quad 2-Channel Multiplexer with 3-State Outputs
MC74HC257 Quad 2-Channel Muliplexer wih 3-ae Oupus The MC74HC257 is an advanced high speed CMO quad 2 channel muliplexer fabricaed wih silicon gae CMO echnology. I achieves high speed operaion similar
74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 4HC4 is identical in pinout to the LS4. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they
MC14174B/D. Hex Type D Flip Flop
7B Hex Type D FlipFlop The 7B hex ype D flipflop is coruced wih OS Pchannel and Nchannel enhancemen mode devices in a single monolihic srucure. Daa on he D inpus which mees he seup ime requireme is raferred
MC74AC132, MC74ACT132. Quad 2 Input NAND Schmitt Trigger
MC74AC32, MC74ACT32 Quad 2 Input NAND Schmitt Trigger The MC74AC/74ACT32 contains four 2 input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter free
MJE18006G SWITCHMODE. NPN Bipolar Power Transistor For Switching Power Supply Applications POWER TRANSISTOR 6.0 AMPERES 1000 VOLTS 100 WATTS
SWITCHMODE NPN Bipolar Power Transisor For Swiching Power Supply Applicaions The has an applicaions specific saeofhear die designed for use in V lineoperaed SWITCHMODE Power supplies and elecronic ligh
MJE5740, MJE5742. NPN Silicon Power Darlington Transistors POWER DARLINGTON TRANSISTORS 8 AMPERES VOLTS 80 WATTS
is a Preferred Device NPN Silicon Power Darlingon Transisors The and Darlingon ransisors are designed for highvolage power swiching in inducive circuis. Feaures PbFree Packages are Available* Applicaions
MC14049B, MC14050B. Hex Buffer
MC4049B, MC4050B Hex Buffer The MC4049B Hex Inverter/Buffer and MC4050B Noninverting Hex Buffer are constructed with MOS PChannel and NChannel enhancement mode devices in a single monolithic structure.
MC14027B. Dual J K Flip Flop
M4027B Dual Flip Flop The M4027B dual flip flop has independen,, lock (), Se (S) and Rese (R) inpus for each flip flop. These devices may be used in conrol, regiser, or oggle funcio. Feaures Diode Proecion
MJE5740G, MJE5742G. NPN Silicon Power Darlington Transistors POWER DARLINGTON TRANSISTORS 8 AMPERES VOLTS 80 WATTS
MJE74G, MJE74G NPN Silicon Power Darlingon Transisors The MJE74G and MJE74G Darlingon ransisors are designed for highvolage power swiching in inducive circuis. Feaures These Devices are PbFree and are
High Performance Silicon Gate CMOS
High Performance Silicon Gae MOS The M74H574A is idenical in pinou o he LS574. The device inpus are compaible wih sandard MOS oupus; wih pull up resisors, hey are compaible wih LSTTL oupus. aa meeing he
74FST Bit Bus Switch
4FST32 4 Bit Bus Switch The ON Semiconductor 4FST32 is a quad, high performance switch. The device is CMOS TTL compatible when operating between 4 and. Volts. The device exhibits extremely low R ON and
FST Bit Bus Switch
FST32 4-Bit Bus Switch The ON Semiconductor FST32 is a quad, high performance switch. The device is CMOS TTL compatible when operating between 4 and. Volts. The device exhibits extremely low R ON and adds
MC14020B. 14 Bit Binary Counter
M4020B 4Bi Binary ouner The M4020B 4sage binary couner is coruced wih MOS Phannel and Nhannel enhancemen mode devices in a single monolihic srucure. This par is designed wih an inpu wave shaping circui
SN74LS157MEL. Quad 2 Input Multiplexer LOW POWER SCHOTTKY
Quad 2 Input Multiplexer The LSTTL/ MSI is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs
NE522 High Speed Dual Differential Comparator/Sense Amp
HighSpeed DualDifferential Comparator/Sense Amp Features 5 ns Maximum Guaranteed Propagation Delay 0 A Maximum Input Bias Current TTL-Compatible Strobes and Outputs Large Common-Mode Input oltage Range
SN74LS145MEL. 1 of 10 Decoder/Driver Open Collector LOW POWER SCHOTTKY
of 0 Decoder/Driver Open Collector The SN74LS45, -of-0 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 0-digit incandescent displays. All outputs remain off for
MC14049B, MC14050B. Hex Buffer
MC404B, MC4050B Hex Buffer The MC404B Hex Inverter/Buffer and MC4050B Noninverting Hex Buffer are constructed with MOS PChannel and NChannel enhancement mode devices in a single monolithic structure. These
MC74VHC14. Hex Schmitt Inverter
MC74HC4 Hex Schmitt Inverter The MC74HC4 is an advanced high speed CMOS Schmitt inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky
MC74VHC245. Octal Bus Buffer/Line Driver
MC74HC245 Octal Bus Buffer/Line Driver The MC74HC245 is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
MC14584B. Hex Schmitt Trigger
MC4584B Hex Schmitt Trigger The MC4584B Hex Schmitt Trigger is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. These devices find primary use where
MC74AC109, MC74ACT109. Dual JK Positive Edge Triggered Flip Flop
MC9, MC9 Dual JK Positive EdgeTriggered FlipFlop The MC9/9 coists of two highspeed completely independent traition clocked JK flipflops. The clocking operation is independent of rise and fall times of
SN74LS132MEL. Quad 2 Input Schmitt Trigger NAND Gate LOW POWER SCHOTTKY
Quad 2 Input Schmitt Trigger NAND Gate The SN74LS32 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly
MC74HC4094A. 8-Bit Shift and Store Register. High Performance Silicon Gate CMOS
8-Bit Shift and Store Register High Performance Silicon Gate CMOS The MC74HC4094A is a high speed CMOS 8 bit serial shift and storage register. This device consists of an 8 bit shift register and latch
High Performance Silicon Gate CMOS
High Performance Silicon Gae MOS The M7H7A is idenical in pinou o he LS7. The device inpus are compaible wih sandard MOS oupus; wih pull up resisors, hey are compaible wih LSTTL oupus. This device coiss
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MC74AC74, MC74ACT74. Dual D Type Positive Edge Triggered Flip Flop
Dual D Type Positive Edge Triggered Flip Flop The MC74AC74/74ACT74 is a dual D type flip flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is traferred
MC74AC259, MC74ACT Bit Addressable Latch
8 Bit Addressable Latch The MC74AC259/74ACT259 is a high speed 8 bit addressable latch designed for general purpose storage applicatio in digital systems. It is a multifunctional device capable of storing
NLSV2T Bit Dual-Supply Inverting Level Translator
2-Bit Dual-Supply Inverting Level Translator The NLSV2T240 is a 2 bit configurable dual supply voltage level translator. The input A n and output B n ports are designed to track two different power supply
MC74ACT Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
8 Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins The MC74ACT323 is an 8-bit universal shift/storage register with3-state outputs. Its function is similar to the MC74ACT299
NDS9952A Dual N & P-Channel Enhancement Mode Field Effect Transistor
NS99A ual N & P-Channel Enhancemen Mode Field Effec Transisor General escripion Feaures These dual N- and P-channel enhancemen mode power field effec ransisors are produced using ON Semiconducors proprieary,
74FST Bit, 4 Port Bus Exchange Switch
4 Bit, 4 Port Bus Exchange Switch The ON Semiconductor 74FST3400 is a 4 bit, 4 port bus exchange switch. The device is CMOS TTL compatible when operating between 4.0 and 5.5 Volts. The device exhibits
SN74LS151MEL. 8 Input Multiplexer LOW POWER SCHOTTKY
8 Input Multiplexer The TTL/MSI SN74LS5 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS5 can be used as
1.3 A, 20 V. R DS(ON) = 25 C unless otherwise noted. Symbol Parameter NDS331N Units V DSS. Drain-Source Voltage 20 V V GSS
NSN N-Channel Logic Level Enhancemen Mode Field Effec Transisor General escripion Feaures These N-Channel logic level enhancemen mode power field effec ransisors are produced using ON Semiconducor's proprieary,
MC74HC86A. Quad 2 Input Exclusive OR Gate. High Performance Silicon Gate CMOS
Quad 2 Input Exclusive OR Gate High Performance Silicon Gate CMOS The MC4HC86A is identical in pinout to the S86. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they
MC14070B, MC14077B CMOS SSI. Quad Exclusive OR and NOR Gates
C070B, C077B COS SSI Quad Exclusive OR and NOR Gates The C070B quad exclusive OR gate and the C077B quad exclusive NOR gate are constructed with OS Pchannel and Nchannel enhancement mode devices in a single
SN74LS125A, SN74LS126A. Quad 3 State Buffers LOW POWER SCHOTTKY. LS125A LS126A TRUTH TABLES ORDERING INFORMATION
Quad 3 State Buffers V CC E D O E D O 4 3 2 0 9 8 LOW POWER SCHOTTKY 2 3 4 5 6 E D O E D O LS25A GND V CC E D O E D O 4 3 2 0 9 8 4 PLASTIC N SUFFIX CASE 646 LS25A INPUTS 2 3 4 5 6 E D O E LS26A D O GND
NLSV22T244. Dual 2-Bit Dual-Supply Non-Inverting Level Translator
Dual 2-Bit Dual-Supply Non-Inverting Level Translator The NLSV22T244 is a dual 2 bit configurable dual supply bus buffer level translator. The input ports A and the output ports B are designed to track
MC74LCX74. Low-Voltage CMOS Dual D-Type Flip-Flop. With 5 V Tolerant Inputs
Low-oltage CMOS Dual D-Type Flip-Flop With 5 Tolerant Inputs The MC74LCX74 is a high performance, dual D type flip flop with asynchronous clear and set inputs and complementary (O, O) outputs. It operates
MC Bit Magnitude Comparator
Bit Magnitude Comparator The MC0 is a high speed expandable bit comparator for comparing the magnitude of two binary words. Two outputs are provided: and. A = B can be obtained by NORing the two outputs
MC14040B. 12-Bit Binary Counter
M4040B 2Bi Binary ouner The M4040B 2sage binary couner is coruced wih MOS Phannel and Nhannel enhancemen mode devices in a single monolihic srucure. This par is designed wih an inpu wave shaping circui
MC74LV594A. 8-Bit Shift Register with Output Register
8-Bit Shift Register with Output Register The MC74LV594A is an 8 bit shift register designed for 2 V to 6.0 V V CC operation. The device contain an 8 bit serial in, parallel out shift register that feeds
High Performance Silicon Gate CMOS
High Performance Silicon Gate CMOS The MC74HCT14A may be used as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs. The HCT14A is identical in pinout to the LS14. The HCT14A
Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS
TECHNICAL DATA IW0B Analog Muliplexer Demuliplexer HighPerformance SiliconGae CMOS The IW0B analog muliplexer/demuliplexer is digially conrolled analog swiches having low ON impedance and very low OFF
LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES ORDERING INFORMATION. SN74LS37xN AWLYYWW PDIP 20 N SUFFIX CASE 738
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is
Part Ordering code Marking Remarks 1N4148W-V 1N4148W-V-GS18 or 1N4148W-V-GS08 A2 Tape and Reel
Small Signal Fas Swiching Diode Feaures These diodes are also available in oher case syles including he DO- case wih he ype designaion N8, he MiniMELF case wih he ype designaion LL8, and he SOT- case wih
LOW POWER SCHOTTKY. ESD > 3500 Volts. GUARANTEED OPERATING RANGES ORDERING INFORMATION V CC 8 7 GND
ESD > 3500 Volts V CC 8 4 3 2 0 9 LOW POWER SCHOTTKY 2 3 4 5 6 7 GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage 4.75 5.0 5.25 V T A Operating Ambient Temperature
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163. Synchronous Presettable Binary Counter
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 Synchronous Presettable Binary Counter The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high speed synchronous modulo 16 binary counters. They are synchronously
SN74LS373, SN74LS374. Octal Transparent Latch with 3 State Outputs; Octal D Type Flip Flop with 3 State Output LOW POWER SCHOTTKY
Octal Transparent Latch with 3 State Outputs; Octal Type Flip Flop with 3 State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops
MC74VHC1GT125. Noninverting Buffer / CMOS Logic Level Shifter with LSTTL Compatible Inputs
C74CGT Noninvering Buffer / COS ogic evel Shifer wih STT Compaible Inpus The C74CGT is a single gae noninvering buffer fabricaed wih silicon gae COS echnology. I achieves high speed operaion similar o
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in
MC74HC390. Dual 4 Stage Binary Ripple Counter with 2 and 5 Sections. High Performance Silicon Gate CMOS
Dual 4Sage Binary Ripple ouner wih 2 and 5 Secions HighPerformance Siliconae OS The 54/74H30 is idenical in pinou o he LS30. The device inpus are compaible wih sandard OS oupus; wih pullup resisors, hey
MC14015B. Dual 4 Bit Static Shift Register
M0B Dual Bi Saic Shif egiser The M0B dual bi saic shif regiser is coruced wih MOS Phannel and Nhannel enhancemen mode devices in a single monolihic srucure. I coiss of wo idenical, independen sae serialinpu/paralleloupu
74ALVC Low Voltage 1.8/2.5/3.3 V 16 Bit Buffer. With 3.6 V Tolerant Inputs and Outputs (3 State, Non Inverting)
Low Voltage.8/2.5/3.3 V 6 Bit Buffer With 3.6 V Tolerant Inputs and Outputs (3 State, Non Inverting) The 74ALVC6244 is an advanced performance, non inverting 6 bit buffer. It is designed for very high
74HCT32. Quad 2 Input OR Gate with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
Quad 2 Input OR Gate with STT Compatible Inputs igh Performance Silicon Gate CMOS The 74CT32 is identical in pinout to the S32. The device has TT compatible inputs. Features Output Drive Capability: 0
SN74LS147, SN74LS Line to 4 Line and 8 Line to 3 Line Priority Encoders LOW POWER SCHOTTKY
0 Line to Line and 8 Line to 3 Line Priority Encoders The SN7LS7 and the SN7LS8 are Priority Encoders. They provide priority decoding of the inputs to eure that only the highest order data line is encoded.