MC74HC165A. 8 Bit Serial or Parallel Input/ Serial Output Shift Register. High Performance Silicon Gate CMOS
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1 MC74CA 8 Bi Serial or Parallel Inpu/ Serial Oupu Shif Regiser igh Performance Silicon Gae CMOS The MC74CA is idenical in pinou o he S. The device inpus are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible wih STT oupus. This device is an 8 bi shif regiser wih complemenary oupus from he las sage. Daa may be loaded ino he regiser eiher in parallel or in serial form. When he Serial Shif/Parallel oad inpu is low, he daa is loaded asynchronously in parallel. When he Serial Shif/Parallel oad inpu is high, he daa is loaded serially on he rising edge of eiher Clock or Clock Inhibi (see he Funcion Table). The 2 inpu NOR clock may be used eiher by combining wo independen clock sources or by designaing one of he clock inpus o ac as a clock inhibi. Feaures Oupu Drive Capabiliy: 0 STT oads Oupus Direcly Inerface o CMOS, NMOS, and TT Operaing olage Range: 2.0 o 6.0 ow Inpu Curren: A igh Noise Immuniy Characerisic of CMOS Devices In Compliance wih he Requiremens Defined by JEDEC Sandard No. 7A Chip Complexiy: 286 FETs or 7. Equivalen Gaes Pb Free Packages are Available* PDIP N SUFFI CASE 648 SOIC D SUFFI CASE 7B TSSOP DT SUFFI CASE 948F SOEIAJ F SUFFI CASE 966 MARKING DIAGRAMS MC74CAN AWYYWWG CAG AWYWW C A AYW 74CA AYWG A = Assembly ocaion, W = Wafer o Y, YY = Year W, WW = Work Week G = Pb Free Package = Pb Free Package (Noe: Microdo may be in eiher locaion) ORDERING INFORMATION See deailed ordering and shipping informaion in he package dimensions secion on page 2 of his daa shee. *For addiional informaion on our Pb Free sraegy and soldering deails, please download he ON Semiconducor Soldering and Mouning Techniques Reference Manual, SODERRM/D. Semiconducor Componens Indusries, C, 200 Publicaion Order Number: MC74CA/D
2 MC74CA SERIA SIFT/ PARAE OAD CC COCK 2 COCK INIBIT E 3 4 D F 4 3 C G 2 B 6 A Q 7 0 S A GND 8 9 Q Figure. Pin Assignmen PARAE DATA INPUTS SERIA DATA INPUT A 2 B 3 C D 4 E 3 F 4 G 6 S 0 A SERIA SIFT/ PARAE OAD COCK COCK INIBIT Q Q SERIA DATA OUTPUTS PIN = CC PIN 8 = GND Figure 2. ogic Diagram FUNCTION TABE Inpus Inernal Sages Oupu Serial Shif/ Parallel oad Clock Clock Inhibi S A A Q A Q B Q Operaion a h a b h Asynchronous Parallel oad No Change Serial Shif via Clock Serial Shif via Clock Inhibi Inhibied Clock No Change No Clock = don care = Daa shifed from he preceding sage ORDERING INFORMATION Device Package Shipping MC74CAN PDIP 00 Unis / Rail MC74CANG PDIP 00 Unis / Rail MC74CAD SOIC 48 Unis / Rail MC74CADG SOIC 48 Unis / Rail MC74CADR2 SOIC 200 Unis / Reel MC74CADR2G SOIC 200 Unis / Reel MC74CADTR2 TSSOP * 200 Unis / Reel MC74CADTR2G TSSOP * 200 Unis / Reel MC74CAF SOEIAJ 0 Unis / Rail MC74CAFG SOEIAJ 0 Unis / Rail MC74CAFE SOEIAJ 2000 Unis / Reel MC74CAFEG SOEIAJ 2000 Unis / Reel For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD80/D. *This package is inherenly Pb Free. 2
3 MC74CA MAIMUM RATINGS Symbol Parameer Î alue Uni CC DC Supply olage (Referenced o GND) Î 0. o in DC Inpu olage (Referenced o GND) Î 0. o CC + 0. ou DC Oupu olage (Referenced o GND) Î 0. o CC + 0. I in DC Inpu Curren, per Pin Î ± 20 ma I ou DC Oupu Curren, per Pin Î ± 2 ma I CC DC Supply Curren, CC and GND Pins Î ± 0 ma P D Power Dissipaion in Sill Air Plasic DIP Î 70 mw SOIC Package 00 TSSOP Package 40 T sg Sorage Temperaure 6 o + 0 C T ead Temperaure, mm from Case for 0 Seconds Î (Plasic DIP, SOIC or TSSOP Package) Î 260 C Maximum raings are hose values beyond which device damage can occur. Maximum raings applied o he device are individual sress limi values (no normal operaing condiions) and are no valid simulaneously. If hese limis are exceeded, device funcional operaion is no implied, damage may occur and reliabiliy may be affeced. Deraing Plasic DIP: 0 mw/ C from 6 o 2 C SOIC Package: 7 mw/ C from 6 o 2 C TSSOP Package: 6. mw/ C from 6 o 2 C For high frequency or heavy load consideraions, see Chaper 2 of he ON Semiconducor igh Speed CMOS Daa Book (D29/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameer Min Max Uni CC DC Supply olage (Referenced o GND) Î in, ou DC Inpu olage, Oupu olage (Referenced o GND) 0 CC T A Operaing Temperaure, All Package Types + 2 C r, f Inpu Rise and Fall Time CC = ns Î (Figure ) CC = Î CC = CC = 6.0 DC EECTRICA CARACTERISTICS (olages Referenced o GND) Î Symbol Parameer Î Tes Condiions Guaraneed imi CC Î o 2 C 8 C 2 C Î Uni I Minimum igh evel Inpu Î ou = 0. or CC olage I ou 20 A Î 4.Î Î I Maximum ow evel Inpu olage Î ou = 0. or CC I ou 20 A 3.0Î Î 4.Î O Minimum igh evel Oupu olage Î in = I or I I ou 20 A 4.Î Î in = I or I I ou 2.4 ma I ou 4.0 ma I ou.2 ma 6.0Î This device conains proecion circuiry o guard agains damage due o high saic volages or elecric fields. owever, precauions mus be aken o avoid applicaions of any volage higher han maximum raed volages o his high impedance circui. For proper operaion, in and ou should be consrained o he range GND ( in or ou ) CC. Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher GND or CC ). Unused oupus mus be lef open. 3
4 MC74CA DC EECTRICA CARACTERISTICS (olages Referenced o GND) Guaraneed imi CC Symbol Parameer Î Tes Condiions Î o 2 C 8 C 2 C Uni O Maximum ow evel Oupu Î in = I or I 2.0Î olage I ou 20 A Î in = I or I I ou 2.4 ma I ou 4.0 ma Î I ou.2 ma Î I in Maximum Inpu eakage Curren in = CC or GND 6.0Î ± 0. ±.0 ±.0 A I CC Maximum Quiescen SupplyÎ in = CC or GND Curren (per Package) I ou = 0 A 6.0Î Î A NOTE: Informaion on ypical parameric values can be found in Chaper 2 of he ON Semiconducor igh Speed CMOS Daa Book (D29/D). AC EECTRICA CARACTERISTICS (C = 0 pf, Inpu r = f = 6 ns) Symbol Parameer Guaraneed imi CC Î o 2 C 8 C 2 C Uni f max Maximum Clock Frequency (0% Duy Cycle) 2.0Î Mz (Figures and 8) Î 4.Î Î 6.0Î P, Maximum Propagaion Delay, Clock (or Clock Inhibi) o Q or Q 2.0Î ns P (Figures and 8) Î Î P, Maximum Propagaion Delay, Serial Shif/Parallel oad o Q P or Q ns (Figures 2 and 8) Î 4.Î Î P, Maximum Propagaion Delay, Inpu o Q P or Q ns (Figures 3 and 8) Î 4.Î Î T, Maximum Oupu Transiion Time, Any Oupu ns T (Figures and 8) 3.0Î Î 4.Î Î Maximum Inpu Capaciance pf C in NOTES:. For propagaion delays wih loads oher han 0 pf, see Chaper 2 of he ON Semiconducor igh Speed CMOS Daa Book (D29/D). 2. Informaion on ypical parameric values can be found in Chaper 2 of he ON Semiconducor igh Speed CMOS Daa Book (D29/D). 2 C, CC =.0 C PD Power Dissipaion Capaciance (Per Package)* 40 pf * Used o deermine he no load dynamic power consumpion: P D = C PD 2 CC f + I CC CC. For load consideraions, see Chaper 2 of he ON Semiconducor igh Speed CMOS Daa Book (D29/D). 4
5 MC74CA TIMING REQUIREMENTS (Inpu r = f = 6 ns) SymbolÎ Parameer Guaraneed imi CC Î o 2 C 8 C 2 C Uni su Minimum Seup Time, Parallel Daa Inpus o Serial Shif/Parallel oad ns (Figure 4) Î Î su Minimum Seup Time, Inpu SA o Clock (or Clock Inhibi) ns Î (Figure ) 3.0Î Î Î su Minimum Seup Time, Serial Shif/Parallel oad o Clock (or Clock Inhibi) ns Î (Figure 6) 3.0Î Î su Minimum Seup Time, Clock o Clock Inhibi ns (Figure 7) 3.0Î Î h Î Minimum old Time, Serial Shif/Parallel oad o Parallel Daa Inpus 2.0Î ns (Figure 4) 3.0Î Î h Î Minimum old Time, Clock (or Clock Inhibi) o Inpu SA 2.0Î ns (Figure ) 3.0Î Î h Î Minimum old Time, Clock (or Clock Inhibi) o Serial Shif/Parallel oad 2.0Î ns (Figure 6) 3.0 Î Î rec Î Minimum Recovery Time, Clock o Clock Inhibi 2.0Î ns (Figure 7) Î Î 3 9 w Î Minimum Pulse Widh, Clock (or Clock Inhibi) 2.0Î ns (Figure ) Î Î 3 9 w Minimum Pulse widh, Serial Shif/Parallel oad ns (Figure 2) Î Î r, f Maximum Inpu Rise and Fall Times ns Î (Figure ) 3.0Î Î NOTE: Informaion on ypical parameric values can be found in Chaper 2 of he ON Semiconducor igh Speed CMOS Daa Book (D29/D). 6.0
6 MC74CA PACKAGE DIMENSIONS PDIP N SUFFI CASE ISSUE T A 8 9 B NOTES:. DIMENSIONING AND TOERANCING PER ANSI Y4.M, CONTROING DIMENSION: INC. 3. DIMENSION TO CENTER OF EADS WEN FORMED PARAE. 4. DIMENSION B DOES NOT INCUDE MOD FAS.. ROUNDED CORNERS OPTIONA. G F S C K T SEATING PANE D P 0.2 (0.00) M T A M J M INCES MIIMETERS DIM MIN MA MIN MA A B C D F G 0.00 BSC 2.4 BSC 0.00 BSC.27 BSC J K M S SOIC D SUFFI CASE 7B 0 ISSUE J A 9 8 B P 8 P 0.2 (0.00) M B S NOTES:. DIMENSIONING AND TOERANCING PER ANSI Y4.M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAIMUM MOD PROTRUSION 0. (0.006) PER SIDE.. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.27 (0.00) TOTA IN ECESS OF TE D DIMENSION AT MAIMUM MATERIA CONDITION. T SEATING PANE G K C D P 0.2 (0.00) M T B S A S M R 4 J F MIIMETERS INCES DIM MIN MA MIN MA A B C D F G.27 BSC 0.00 BSC J K M P R
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N27WZ Dual 2-Input AND Gate The N27WZ is a high performance dual 2 input AND Gate operating from a.6 to. supply. Features Extremely igh Speed: t PD 2. ns (typical) at = Designed for.6 to. Operation Over
MC10H606, MC100H606. Registered Hex TTL to PECL Translator
Registered ex TT to PEC Translator Description The MC10/100606 is a 6 bit, registered, single supply TT to PEC translator. The device features differential PEC outputs as well as a choice between either
NL27WZ08. Dual 2-Input AND Gate. The NL27WZ08 is a high performance dual 2 input AND Gate operating from a 1.65 V to 5.5 V supply.
Dual 2-Input AND Gate The is a high performance dual 2 input AND Gate operating from a.65 to 5.5 supply. Features Extremely igh Speed: t PD 2.5 ns (typical) at = 5 Designed for.65 to 5.5 Operation Over
NL27WZ00. Dual 2-Input NAND Gate. The NL27WZ00 is a high performance dual 2 input NAND Gate operating from a 1.65 V to 5.5 V supply.
Dual 2-Input NAND Gate The N27WZ00 is a high performance dual 2 input NAND Gate operating from a.65 to 5.5 supply. Features Extremely igh Speed: t PD ns (typical) at = 5.0 Designed for.65 to 5.5 Operation
MC14060B. 14 Bit Binary Counter and Oscillator
4Bit Binary Counter and Oscillator The MC4060B is a 4stage binary ripple counter with an onchip oscillator buffer. The oscillator configuration allows design of either RC or crystal oscillator circuits.
D44VH10 (NPN), D45VH10 (PNP) Complementary Silicon Power Transistors 15 A COMPLEMENTARY SILICON POWER TRANSISTORS 80 V, 83 W
DH (NPN), D5H (PNP) Complemenary Silicon Power Transisors These complemenary silicon power ransisors are designed for highspeed swiching applicaions, such as swiching regulaors and high frequency inverers.
MC74HC04A. Hex Inverter. High Performance Silicon Gate CMOS
ex Inverter igh Performance Silicon Gate CMOS The MC74C04 is identical in pinout to the S04 and the MC4069. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are
NL17SZ08. Single 2-Input AND Gate
N7SZ08 Single 2-Input AND Gate The N7SZ08 is a single 2 input AND Gate in two tiny footprint packages. The device performs much as CX multi gate products in speed and drive. They should be used wherever
MC74VHC257. Quad 2-Channel Multiplexer with 3-State Outputs
MC74HC257 Quad 2-Channel Muliplexer wih 3-ae Oupus The MC74HC257 is an advanced high speed CMO quad 2 channel muliplexer fabricaed wih silicon gae CMO echnology. I achieves high speed operaion similar
NL37WZ07. Triple Buffer with Open Drain Outputs
Triple Buffer with Open Drain Outputs The N7WZ7 is a high performance triple buffer with open drain outputs operating from a.6 to. supply. The internal circuit is composed of multiple stages, including
NL17SHT08. 2-Input AND Gate / CMOS Logic Level Shifter
N7ST08 -Input AND Gate / CMOS ogic evel Shifter The N7ST08 is an advanced high speed CMOS input AND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
MC14027B. Dual J K Flip Flop
M4027B Dual Flip Flop The M4027B dual flip flop has independen,, lock (), Se (S) and Rese (R) inpus for each flip flop. These devices may be used in conrol, regiser, or oggle funcio. Feaures Diode Proecion
MC14042B. MARKING DIAGRAMS. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) ORDERING INFORMATION PDIP 16 P SUFFIX CASE 648
The MC14042B Quad Traparen Lach is coruced wih MOS P channel and N channel enhancemen mode devices in a single monolihic srucure. Each lach has a separae daa inpu, bu all four laches share a common clock.
MC74HC32A. Quad 2-Input OR Gate. High Performance Silicon Gate CMOS
MC74C32 Quad 2-Input OR Gate igh Performance Silicon Gate CMOS The MC74C32 is identical in pinout to the S32. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are
MC74HC08A. Quad 2-Input AND Gate High Performance Silicon Gate CMOS
MC74C08 Quad 2-Input ND Gate igh Performance Silicon Gate CMOS The MC74C08 is identical in pinout to the S08. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are
NL17SZ125. Non-Inverting 3-State Buffer. The NL17SZ125 is a high performance non inverting buffer operating from a 1.65 V to 5.5 V supply.
Non-Inverting 3-State Buffer The N17SZ125 is a high performance non inverting buffer operating from a 1.65 to 5.5 supply. Features Extremely High Speed: t PD 2.6 ns (typical) at CC = 5.0 Designed for 1.65
8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SHIFT RESISTER High-Performance Silicon-Gate CMOS
TECNICAL DATA 8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SIFT RESISTER igh-performance Silicon-ate CMOS The may be used as a level converter for interfacing TTL or NMOS outputs to high-speed CMOS inputs. The is
MC74HC244A Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs;
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION
The SN74S240 and SN74S244 are Octal Buffers and ine Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density.
MC74AC74, MC74ACT74. Dual D Type Positive Edge Triggered Flip Flop
Dual D Type Positive Edge Triggered Flip Flop The MC74/T74 is a dual D type flip flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is traferred to the
MC74HC132A. Quad 2 Input NAND Gate with Schmitt Trigger Inputs. High Performance Silicon Gate CMOS
Quad 2 Input NAND Gate with Schmitt Trigger Inputs High Performance Silicon Gate CMOS The is identical in pinout to the LS32. The device inputs are compatible with standard CMOS outputs; with pull up resistors,
MC74HC138A. 1-of-8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
MC74HC38A -of-8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The MC74HC38A is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
PI5A3157. SOTINY TM Low Voltage SPDT Analog Switch 2:1 Mux/Demux Bus Switch. Features. Descriptio n. Applications. Connection Diagram Pin Description
PI53157 OINY M Low Volage PD nalog wich 2:1 Mux/Demux Bus wich Feaures CMO echnology for Bus and nalog pplicaions Low ON Resisance: 8-ohms a 3.0V Wide Range: 1.65V o 5.5V Rail-o-Rail ignal Range Conrol
NL27WZ00. Dual 2 Input NAND Gate L1 D
Dual 2 Input NAND Gate The N27WZ00 is a high performance dual 2 input NAND Gate operating from a to 5.5 supply. Extremely igh Speed: t PD 2.4 ns (typical) at CC = 5 Designed for to 5.5 CC Operation Over
MC14020B. 14 Bit Binary Counter
M4020B 4Bi Binary ouner The M4020B 4sage binary couner is coruced wih MOS Phannel and Nhannel enhancemen mode devices in a single monolihic srucure. This par is designed wih an inpu wave shaping circui
74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
High Performance Silicon Gate CMOS
igh Performance Silicon Gate MOS The M7400A is identical in pinout to the S00. The device inputs are compatible with Standard MOS outputs; with pullup resistors, they are compatible with STT outputs. Output
MC74HC00A. Quad 2 Input NAND Gate. High Performance Silicon Gate CMOS
C74C00 Quad 2 Input NND Gate igh Performance Silicon Gate COS The C74C00 is identical in pinout to the S00. The device inputs are compatible with Standard COS outputs; with pullup resistors, they are compatible
NL27WZ14. Dual Schmitt Trigger Inverter
N7WZ Dual Schmitt Trigger Inverter The N7WZ is a high performance dual inverter with Schmitt Trigger inputs operating from a.5 to supply. Pin configuration and function are the same as the N7WZ0, but the
MC74HC04A. Hex Inverter. High Performance Silicon Gate CMOS
Hex Inverter High Performance Silicon Gate COS The is identical in pinout to the S04 and the C069. The device inputs are compatible with Standard COS outputs; with pullup resistors, they are compatible
74HC of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The 74HC38 is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are
MC74HC139A. Dual 1 of 4 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
MC74HC39A Dual of 4 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The MC74HC39A is identical in pinout to the LS39. The device inputs are compatible with standard CMOS outputs; with pull up
MC74HCT138A. 1 of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC74HCT38A is identical in pinout to the LS38. The HCT38A may be used as a level converter for interfacing
High Performance Silicon Gate CMOS
High Performance Silicon Gae MOS The M7H7A is idenical in pinou o he LS7. The device inpus are compaible wih sandard MOS oupus; wih pull up resisors, hey are compaible wih LSTTL oupus. This device coiss
NDS332P P-Channel Logic Level Enhancement Mode Field Effect Transistor
June 997 NS33P P-Channel Logic Level Enhancemen Mode Field Effec Transisor General escripion Feaures These P-Channel logic level enhancemen mode power field effec ransisors are produced using Fairchild's
NL27WZ14. Dual Schmitt-Trigger Inverter
N7WZ Dual Schmitt-Trigger Inverter The N7WZ is a high performance dual inverter with Schmitt Trigger inputs operating from a.5 to supply. Pin configuration and function are the same as the N7WZ0, but the
Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
TECHNICAL DATA IN74ACT74 Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT74 is identical in pinout to the LS/ALS74, HC/HCT74. The IN74ACT74 may be used as a level converter
MC74VHC1G08. Single 2-Input AND Gate
Single 2-Input AND Gate The is an advanced high speed CMOS 2 input AND gate fabricated with silicon gate CMOS technology. The internal circuit is composed of multiple stages, including a buffer output
NL27WZU04. Dual Unbuffered Inverter
Dual Unbuffered Inverter The N27WZU04 is a high performance dual unbuffered inverter operating from a.5 to 5.5 V supply. These devices are well suited for use as oscillators, pulse shapers, and in many
NL17SH02. Single 2-Input NOR Gate
N7S0 Single -Input NOR Gate The N7S0 MiniGate is an advanced high speed CMOS input NOR gate in ultra small footprint. The N7S0 input structures provide protection when voltages up to 7.0 are applied, regardless
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic