MC74VHC257. Quad 2-Channel Multiplexer with 3-State Outputs
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1 MC74HC257 Quad 2-Channel Muliplexer wih 3-ae Oupus The MC74HC257 is an advanced high speed CMO quad 2 channel muliplexer fabricaed wih silicon gae CMO echnology. I achieves high speed operaion similar o equivalen Bipolar choky TTL while mainaining CMO low power dissipaion. I consiss of four 2 inpu digial muliplexers wih common selec () and enable (OE) inpus. When (OE) is held High, selecion of daa is inhibied and all he oupus go Low. The selec decoding deermines wheher he A or B inpus ge roued o he corresponding Y oupus. The inpus olerae volages up o 7, allowing he inerface of 5 sysems o 3 sysems. High peed: PD = 4. ns (Typ) a CC = 5.0 Low Power Dissipaion: I CC = 4.0 A (Max) a T A = 25 C High Noise Immuniy: NIH = NIL = 28% CC Power Down Proecion Provided on Inpus Balanced Propagaion Delays Designed for o 5.5 Operaing Range Low Noise: OLP = 0.8 (Max) Pin and Funcion Compaible wih Oher andard Logic Families Lachup Performance Exceeds 300 ma ED Performance: HBM > 2000 ; Machine Model > 200 Chip Complexiy: FETs = 00; Equivalen Gaes = 25 These Devices are Pb Free and are RoH Complian O 6 D UFFIX CAE 75B TOP 6 DT UFFIX CAE 948F MARKING DIAGRAM 6 9 HC257G AWLYWW HC 257 ALYW A = Assembly Locaion L, WL = Wafer Lo Y, YY = Year W, WW = Work Week G or = Pb Free Package 8 A CC OE ORDERING INFORMATION Device Package hipping MC74HC257DG O 6 48 Unis/Rail B0 3 4 A3 MC74HC257DR2G O Unis/Reel Y0 A B3 Y3 MC74HC257DTG TOP 6 96 Unis/Rail MC74HC257DTR2G TOP Unis/Reel B 6 A2 Y 7 0 B2 GND 8 9 Y2 Figure. Pin Assignmen emiconducor Componens Indusries, LLC, 204 epember, 204 Rev. 6 Publicaion Order Number: MC74HC257/D
2 MC74HC257 OE I 0a I a I 0b I b I 0c I c I 0d I d Z a Z b Z c Z d Figure 2. Expanded Logic Diagram OE 5 EN G A0 B0 A B A2 B2 A3 B MUX Y0 Y Y2 Y3 Figure 3. IEC Logic ymbol FUNCTION TABLE Inpus Oupus OE Y0 Y3 H L X L Z A0 A3 L H B0 B3 A0 A3, B0 B3 = he levels of he respecive Daa Word Inpus. This device conains proecion circuiry o guard agains damage due o high saic volages or elecric fields. However, precauions mus be aken o avoid applicaions of any volage higher han maximum raed volages o his high impedance circui. For proper operaion, in and ou should be consrained o he range GND ( in or ou ) CC. Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher GND or CC ). Unused oupus mus be lef open. 2
3 MC74HC257 MAXIMUM RATING ymbol Parameer alue Uni CC Posiive DC upply olage 0.5 o +7.0 IN Digial Inpu olage 0.5 o +7.0 OUT DC Oupu olage 0.5 o CC +0.5 I IK Inpu Diode Curren 20 ma I OK Oupu Diode Curren 20 ma I OUT DC Oupu Curren, per Pin 25 ma I CC DC upply Curren, CC and GND Pins 75 ma P D Power Dissipaion in ill Air OIC Package TOP mw T TG orage Temperaure Range 65 o +50 C ED ED Wihsand olage Human Body Model (Noe ) Machine Model (Noe 2) Charged Device Model (Noe 3) >2000 >200 >2000 I LATCHUP Lachup Performance Above CC and Below GND a 25 C (Noe 4) 300 ma JA Thermal Resisance, Juncion o Ambien OIC Package TOP resses exceeding hose lised in he Maximum Raings able may damage he device. If any of hese limis are exceeded, device funcionaliy should no be assumed, damage may occur and reliabiliy may be affeced. Tesed o EIA/JED22 A4 A 2 Tesed o EIA/JED22 A5 A 3 Tesed o JED22 C0 A 4 Tesed o EIA/JED C/W RECOMMENDED OPERATING CONDITION ymbol Characerisics Min Max Uni CC DC upply olage 5.5 IN DC Inpu olage OUT DC Oupu olage 0 CC T A Operaing Temperaure Range, all Package Types C r, f Inpu Rise or Fall Time CC = CC = ns/ Funcional operaion above he sresses lised in he Recommended Operaing Ranges is no implied. Exended exposure o sresses beyond he Recommended Operaing Ranges limis may affec device reliabiliy. DEICE JUNCTION TEMPERATURE ERU TIME TO % BOND FAILURE Juncion Temperaure C Time, Hours Time, Years 80,032, , , , , , ,900.0 NORMALIZED FAILURE RATE FAILURE RATE OF PLATIC = CERAMIC UNTIL INTERMETALLIC OCCUR TJ = 30 C TJ = 20 C TJ = 0 C TJ = 00 C TJ = 90 C TJ = 80 C TIME, YEAR Figure 4. Failure Rae vs. Time Juncion Temperaure 3
4 MC74HC257 DC CHARACTERITIC (olages Referenced o GND) CC T A = 25 C T A 85 C 55 C T A 25 C ymbol Parameer Condiion () Min Typ Max Min Max Min Max Uni IH Minimum High Level Inpu olage IL OH Maximum Low Level Inpu olage Maximum High Level Oupu olage IN = IH or IL I OH = 50 A o 5.5 o 5.5 CCX CCX 0.3 CCX CCX 0.5 CCX 0.3 CCX CCX 0.3 IN = IH or IL I OH = 4 ma I OH = 8 ma OL Maximum Low Level Oupu olage IN = IH or IL I OL = 50 A IN = IH or IL I OH = 4 ma I OH = 8 ma I IN Inpu Leakage Curren IN = 5.5 or GND 0 o 5.5 I OZ I CC Maximum 3 ae Leakage Curren Maximum Quiescen upply Curren (per package) IN = IH or IL OUT = CC or GND ± ±.0 ±.0 A 5.5 ±0.25 ±2.5 ±2.5 A IN = CC or GND A Î AC ELECTRICAL CHARACTERITIC (Inpu r = f = ns) T Î A = 25 C T Î A = 85 C 55 C T A 25 C ymbol Parameer Tes Condiions Min Typ Max Min Max Min Max Î Uni PLH, Maximum Propagaion PHL Î Delay Î CC = 3.3 ± 0.3 C L = 5 pf C L = 50 pf Î Î.0.0Î Î.0.0 ns.0 A or B o Y Î CC = 5.0 ± 0.5 C L = 5 pf C L = 50 pf Î Î Î PLH, Maximum Propagaion PHL Î CC = 3.3 ± 0.3 C L = 5 pf Delay 7.0 Î.0 Î.0Î Î.0 ns C L = 50 pf o Y Î CC = 5.0 ± 0.5 C L Î = 5 pf C L = 50 pf Î Î Î Î Î PZL, Î Maximum Oupu Enable Î CC = 3.3 ± 0.3 C L = 5 pf 6.7 Î 0.5 Î.0Î 2.5 Î ns PZH Time R Î L = k C L = 50 pf OE o Y Î Î Î CC = 5.0 ± 0.5 C L = 5 pf R L = k C L = 50 pf Î Î 8.0.0Î 0.0 Î PLZ, Î Maximum Oupu Disable Î CC = 3.3 ± 0.3 C L = 50 pf Î 5.0Î.0Î 6.0 Î ns PHZ Time R Î L = k OE o Y CC = 5.0 ± 0.5 C L = 50 pf R L = k 5.7 Î Î Î Î Î C IN Î Maximum Inpu Î Capaciance Î Î Î Î 4 Î 0 Î Î 0 Î Î Î 0 pf 25 C, CC = 5.0 C PD Power Dissipaion Capaciance (Noe 5) 20 pf 5. C PD is defined as he value of he inernal equivalen capaciance which is calculaed from he operaing curren consumpion wihou load. Average operaing curren can be obained by he equaion: I CC(OPR) = C PD CC f in + I CC. C PD is used o deermine he no load dynamic power consumpion; P D = C PD 2 CC f in + I CC CC. 4
5 MC74HC257 NOIE CHARACTERITIC (Inpu r = f = ns, C L = 50 pf, CC = 5.0 ) T A = 25 C ymbol Characerisic Typ Max Uni OLP Quie Oupu Maximum Dynamic OL OL Quie Oupu Minimum Dynamic OL IHD Minimum High Level Dynamic Inpu olage 3.5 ILD Maximum Low Level Dynamic Inpu olage.5 CC OE 50% CC GND A, B or 50% PLH PHL GND Y PZL 50% CC PLZ HIGH IMPEDANCE OL Y 50% CC Y PZH 50% CC PHZ OH HIGH IMPEDANCE Figure 5. wiching Waveform Figure 6. wiching Waveform DEICE UNDER TET OUTPUT TET POINT C L * DEICE UNDER TET TET POINT kω OUTPUT C L * CONNECT TO CC WHEN TETING PLZ AND PZL. CONNECT TO GND WHEN TETING PHZ AND PZH. *Includes all probe and jig capaciance Figure 7. Tes Circui *Includes all probe and jig capaciance Figure 8. Tes Circui INPUT Figure 9. Inpu Equivalen Circui 5
6 MC74HC257 PACKAGE DIMENION OIC 6 CAE 75B 05 IUE K A B P 8 PL 0.25 (0.00) M B NOTE:. DIMENIONING AND TOLERANCING PER ANI YM, CONTROLLING DIMENION: MILLIMETER. 3. DIMENION A AND B DO NOT INCLUDE MOLD PROTRUION. 4. MAXIMUM MOLD PROTRUION 5 (0.006) PER IDE. 5. DIMENION D DOE NOT INCLUDE DAMBAR PROTRUION. ALLOWABLE DAMBAR PROTRUION HALL BE 27 (0.005) TOTAL IN EXCE OF THE D DIMENION AT MAXIMUM MATERIAL CONDITION. T EATING PLANE G D 6 PL K C M R X 45 J F MILLIMETER INCHE DIM MIN MAX MIN MAX A B C D F G.27 BC BC J K M P R (0.00) M T B A OLDERING FOOTPRINT 8X X.2 6 6X PITCH 8 9 DIMENION: MILLIMETER 6
7 MC74HC257 PACKAGE DIMENION 5 (0.006) T 5 (0.006) T 0 (0.004) T EATING PLANE L U PIN IDENT. U D 2X L/2 C 6X K REF 0 (0.004) M T U A G B U H TOP 6 CAE 948F IUE B J N N J F DETAIL E DETAIL E K K ÇÇÇ ÉÉÉ ECTION N N 0.25 (0.00) M OLDERING FOOTPRINT 7.06 W NOTE:. DIMENIONING AND TOLERANCING PER ANI YM, CONTROLLING DIMENION: MILLIMETER. 3. DIMENION A DOE NOT INCLUDE MOLD FLAH. PROTRUION OR GATE BURR. MOLD FLAH OR GATE BURR HALL NOT EXCEED 5 (0.006) PER IDE. 4. DIMENION B DOE NOT INCLUDE INTERLEAD FLAH OR PROTRUION. INTERLEAD FLAH OR PROTRUION HALL NOT EXCEED 0.25 (0.00) PER IDE. 5. DIMENION K DOE NOT INCLUDE DAMBAR PROTRUION. ALLOWABLE DAMBAR PROTRUION HALL BE 0.08 (0.003) TOTAL IN EXCE OF THE K DIMENION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBER ARE HOWN FOR REFERENCE ONLY. 7. DIMENION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETER INCHE DIM MIN MAX MIN MAX A B C D F G 0.65 BC BC H J J K K L 6.40 BC BC M PITCH 6X X.26 DIMENION: MILLIMETER ON emiconducor and he are regisered rademarks of emiconducor Componens Indusries, LLC (CILLC) or is subsidiaries in he Unied aes and/or oher counries. CILLC owns he righs o a number of paens, rademarks, copyrighs, rade secres, and oher inellecual propery. A lising of CILLC s produc/paen coverage may be accessed a Marking.pdf. CILLC reserves he righ o make changes wihou furher noice o any producs herein. CILLC makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does CILLC assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Typical parameers which may be provided in CILLC daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. CILLC does no convey any license under is paen righs nor he righs of ohers. CILLC producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he CILLC produc could creae a siuaion where personal injury or deah may occur. hould Buyer purchase or use CILLC producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold CILLC and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha CILLC was negligen regarding he design or manufacure of he par. CILLC is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON emiconducor P.O. Box 563, Denver, Colorado 8027 UA Phone: or Toll Free UA/Canada Fax: or Toll Free UA/Canada orderli@onsemi.com N. American Technical uppor: Toll Free UA/Canada Europe, Middle Eas and Africa Technical uppor: Phone: Japan Cusomer Focus Cener Phone: ON emiconducor Websie: Order Lieraure: hp:// For addiional informaion, please conac your local ales Represenaive MC74HC257/D
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M74H273A Ocal D Flip Flop wih ommon lock and Rese High Performance Silicon Gae MOS The M74H273A is idenical in pinou o he LS273. The device inpus are compaible wih sandard MOS oupus; wih pullup resisors,
MC74HC393A. Dual 4-Stage Binary Ripple Counter. High Performance Silicon Gate CMOS
Dual 4-Sage Binary Ripple ouner High Performance Silicon Gae MOS The M74H393A is idenical in pinou o he LS393. The device inpus are compaible wih sandard MOS oupus; wih pullup resisors, hey are compaible
High Performance Silicon Gate CMOS
High Performance Silicon Gae MOS The M74H574A is idenical in pinou o he LS574. The device inpus are compaible wih sandard MOS oupus; wih pull up resisors, hey are compaible wih LSTTL oupus. aa meeing he
74ALVC Low Voltage 1.8/2.5/3.3 V 16 Bit Buffer. With 3.6 V Tolerant Inputs and Outputs (3 State, Non Inverting)
Low Voltage.8/2.5/3.3 V 6 Bit Buffer With 3.6 V Tolerant Inputs and Outputs (3 State, Non Inverting) The 74ALVC6244 is an advanced performance, non inverting 6 bit buffer. It is designed for very high
MC74LV594A. 8-Bit Shift Register with Output Register
8-Bit Shift Register with Output Register The MC74LV594A is an 8 bit shift register designed for 2 V to 6.0 V V CC operation. The device contain an 8 bit serial in, parallel out shift register that feeds
MC74AC132, MC74ACT132. Quad 2 Input NAND Schmitt Trigger
MC74AC32, MC74ACT32 Quad 2 Input NAND Schmitt Trigger The MC74AC/74ACT32 contains four 2 input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter free
MC74HC573A. Octal 3-State Noninverting Transparent Latch. High Performance Silicon Gate CMOS
Ocal 3-Sae Noninvering Traparen Lach High Performance Silicon Gae COS The C74HC573 is idenical in pinou o he LS573. The devices are compaible wih sandard COS oupus; wih pullup resisors, hey are compaible
Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS
TECHNICAL DATA IW0B Analog Muliplexer Demuliplexer HighPerformance SiliconGae CMOS The IW0B analog muliplexer/demuliplexer is digially conrolled analog swiches having low ON impedance and very low OFF
MC74AC109, MC74ACT109. Dual JK Positive Edge Triggered Flip Flop
MC9, MC9 Dual JK Positive EdgeTriggered FlipFlop The MC9/9 coists of two highspeed completely independent traition clocked JK flipflops. The clocking operation is independent of rise and fall times of
MARKING DIAGRAMS ORDERING INFORMATION Figure 1. Pin Assignment VHCT139A AWLYYWW SOIC 16 D SUFFIX CASE 751B VHCT139A AWLYWW
The MC74HCT139A is an advanced high speed CMOS 2 to 4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL devices
74FST Bit, 4 Port Bus Exchange Switch
4 Bit, 4 Port Bus Exchange Switch The ON Semiconductor 74FST3400 is a 4 bit, 4 port bus exchange switch. The device is CMOS TTL compatible when operating between 4.0 and 5.5 Volts. The device exhibits
PIN ASSIGNMENT LOGI DIAGRAM LOK a RESET a a 2 a LOK b RESET b b LOK, 3 BINARY OUNTER 3, 4, 0 5, 9 6, a 4 a b 3 b RESET
Dual 4 Sage Binary Ripple ouner High Performance Silicon Gae MOS The M74H393A is idenical in pinou o he LS393. The device inpus are compaible wih sandard MOS oupus; wih pullup resisors, hey are compaible
High Performance Silicon Gate CMOS
High Performance Silicon Gae MOS The M7H7A is idenical in pinou o he LS7. The device inpus are compaible wih sandard MOS oupus; wih pull up resisors, hey are compaible wih LSTTL oupus. This device coiss
MC14027B. Dual J K Flip Flop
M4027B Dual Flip Flop The M4027B dual flip flop has independen,, lock (), Se (S) and Rese (R) inpus for each flip flop. These devices may be used in conrol, regiser, or oggle funcio. Feaures Diode Proecion
74VHC08 Quad 2-Input AND Gate
74VHC08 Quad 2-Input AND Gate Features High Speed: t PD = 4.3ns (Typ.) at T A = 25 C High noise immunity: V NIH = V NIL = 28% V CC (Min.) Power down protection is provided on all inputs Low power dissipation:
SN74LS145MEL. 1 of 10 Decoder/Driver Open Collector LOW POWER SCHOTTKY
of 0 Decoder/Driver Open Collector The SN74LS45, -of-0 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 0-digit incandescent displays. All outputs remain off for
AMIS LIN Transceiver
AMIS-000 Transceiver General Descripion The single wire ransceiver AMIS 000 is a monolihic inegraed circui in a SOIC 8 package. I works as an inerface beween he proocol conroller and he physical bus. The
NLSV22T244. Dual 2-Bit Dual-Supply Non-Inverting Level Translator
Dual 2-Bit Dual-Supply Non-Inverting Level Translator The NLSV22T244 is a dual 2 bit configurable dual supply bus buffer level translator. The input ports A and the output ports B are designed to track
SN74LS132MEL. Quad 2 Input Schmitt Trigger NAND Gate LOW POWER SCHOTTKY
Quad 2 Input Schmitt Trigger NAND Gate The SN74LS32 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly
74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
MC74HC139A. Dual 1 of 4 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
MC74HC39A Dual of 4 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The MC74HC39A is identical in pinout to the LS39. The device inputs are compatible with standard CMOS outputs; with pull up
MC14099B. 8 Bit Addressable Latches
MC0B Bi ddressable Laches The MC0B is an bi addressable lach. Daa is enered in serial form when he appropriae lach is addressed (via address pi 0,, ) and wrie disable is in he low sae. For he MC0B he inpu
MC74ACT Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
8 Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins The MC74ACT323 is an 8-bit universal shift/storage register with3-state outputs. Its function is similar to the MC74ACT299
PI74STX1G126. SOTiny Gate STX Buffer with 3-State Output. Features. Descriptio n. Block Diagram. Pin Configuration
PI74STXG6 4567890456789045678904567890456789045678904567890456789045678904567890456789045678904567890 4567890456789045678904567890456789045678904567890456789045678904567890456789045678904567890 SOTiny
MC74LCX74. Low-Voltage CMOS Dual D-Type Flip-Flop. With 5 V Tolerant Inputs
Low-oltage CMOS Dual D-Type Flip-Flop With 5 Tolerant Inputs The MC74LCX74 is a high performance, dual D type flip flop with asynchronous clear and set inputs and complementary (O, O) outputs. It operates
PI5A3157. SOTINY TM Low Voltage SPDT Analog Switch 2:1 Mux/Demux Bus Switch. Features. Descriptio n. Applications. Connection Diagram Pin Description
PI53157 OINY M Low Volage PD nalog wich 2:1 Mux/Demux Bus wich Feaures CMO echnology for Bus and nalog pplicaions Low ON Resisance: 8-ohms a 3.0V Wide Range: 1.65V o 5.5V Rail-o-Rail ignal Range Conrol
SN74LS157MEL. Quad 2 Input Multiplexer LOW POWER SCHOTTKY
Quad 2 Input Multiplexer The LSTTL/ MSI is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs
MC14020B. 14 Bit Binary Counter
M4020B 4Bi Binary ouner The M4020B 4sage binary couner is coruced wih MOS Phannel and Nhannel enhancemen mode devices in a single monolihic srucure. This par is designed wih an inpu wave shaping circui
MC74HCT138A. 1 of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC74HCT38A is identical in pinout to the LS38. The HCT38A may be used as a level converter for interfacing
MC74HC244A. Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver. High Performance Silicon Gate CMOS
Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs;
SN74LS125A, SN74LS126A. Quad 3 State Buffers LOW POWER SCHOTTKY. LS125A LS126A TRUTH TABLES ORDERING INFORMATION
Quad 3 State Buffers V CC E D O E D O 4 3 2 0 9 8 LOW POWER SCHOTTKY 2 3 4 5 6 E D O E D O LS25A GND V CC E D O E D O 4 3 2 0 9 8 4 PLASTIC N SUFFIX CASE 646 LS25A INPUTS 2 3 4 5 6 E D O E LS26A D O GND
74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs Features 5V tolerant inputs 2.3V 3.6V V CC specifications provided 5.5ns t PD max. (V CC = 3.3V), 10µA I CC max. Power down high impedance
MC74HC244A Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs;
MC74HC138A. 1-of-8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
MC74HC38A -of-8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The MC74HC38A is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
MC74HC4094A. 8-Bit Shift and Store Register. High Performance Silicon Gate CMOS
8-Bit Shift and Store Register High Performance Silicon Gate CMOS The MC74HC4094A is a high speed CMOS 8 bit serial shift and storage register. This device consists of an 8 bit shift register and latch
74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 4HC4 is identical in pinout to the LS4. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they
MC74VHC1GT50 Noninverting Buffer / CMOS Logic Level Shifter
MC74CGT0 Noninverting Buffer / CMOS Logic Level Shifter TTL Compatible Inputs The MC74CGT0 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation
MC Bit Magnitude Comparator
Bit Magnitude Comparator The MC0 is a high speed expandable bit comparator for comparing the magnitude of two binary words. Two outputs are provided: and. A = B can be obtained by NORing the two outputs
74FST Bit Bus Switch
8 Bit Bus witch The ON emiconductor 74FT3245 is an 8 bit, high performance switch. The device is CMO TT compatible when operating between 4 and 5.5 Volts. The device exhibits extremely low R ON and adds
LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES ORDERING INFORMATION. SN74LS37xN AWLYYWW PDIP 20 N SUFFIX CASE 738
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is
Figure 1. Pinout: 16 Lead Packages Conductors (Top View) ORDERING INFORMATION Figure 2. Logic Symbol PIN ASSIGNMENT
The MC74AC138/74ACT138 is a high speed 1 of 8 decoder/demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel
NE522 High Speed Dual Differential Comparator/Sense Amp
HighSpeed DualDifferential Comparator/Sense Amp Features 5 ns Maximum Guaranteed Propagation Delay 0 A Maximum Input Bias Current TTL-Compatible Strobes and Outputs Large Common-Mode Input oltage Range
MC14584B. Hex Schmitt Trigger
MC4584B Hex Schmitt Trigger The MC4584B Hex Schmitt Trigger is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. These devices find primary use where
Type Marking Pin Configuration Package SMBT3904/MMBT3904 SOT23 SMBT3904S 2=E 1=B 3=C 1=E1 2=B1 3=C2
SMBT94...MMBT94 NPN Silicon Swiching Transisors High D curren gain:. ma o ma Low collecoremier sauraion volage For SMBT94S: Two (galvanic) inernal isolaed ransisors wih good maching in one package omplemenary
MC74AC74, MC74ACT74. Dual D Type Positive Edge Triggered Flip Flop
Dual D Type Positive Edge Triggered Flip Flop The MC74AC74/74ACT74 is a dual D type flip flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is traferred
NL17SHT08. 2-Input AND Gate / CMOS Logic Level Shifter
N7ST08 -Input AND Gate / CMOS ogic evel Shifter The N7ST08 is an advanced high speed CMOS input AND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
SN74LS151MEL. 8 Input Multiplexer LOW POWER SCHOTTKY
8 Input Multiplexer The TTL/MSI SN74LS5 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS5 can be used as
AND9120/D. An Introduction to LDO Early Warning Function APPLICATION NOTE
An nroducion o LDO Early Warning Funcion Absrac n oday s world of high speed, high power processors, new demands have been placed on he power source regulaor. One example is he need o inform he processor
MC74LVX32. Quad 2-Input OR Gate. With 5 V Tolerant Inputs
MC4X32 Quad 2-Input OR Gate With 5 Tolerant Inputs The MC4X32 is an advanced high speed CMOS 2 input OR gate. The inputs tolerate voltages up to.0, allowing the interface of 5.0 systems to 3.0 systems.
NCN5150. Wired M-BUS Slave Transceiver
Wired M-BUS Slave Transceiver Descripion The is a single-chip inegraed slave ransceiver for use in wo-wire Meer Bus (M-BUS) slave devices and repeaers. The ransceiver provides all of he funcions needed