MC74HC273A. Octal D Flip Flop with Common Clock and Reset. High Performance Silicon Gate CMOS

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1 M74H273A Ocal D Flip Flop wih ommon lock and Rese High Performance Silicon Gae MOS The M74H273A is idenical in pinou o he LS273. The device inpus are compaible wih sandard MOS oupus; wih pullup resisors, hey are compaible wih LSTTL oupus. This device consiss of eigh D flip flops wih common lock and Rese inpus. Each flip flop is loaded wih a low o high ransiion of he lock inpu. Rese is asynchronous and acive low. Feaures Oupu Drive apabiliy: 0 LSTTL Loads Oupus Direcly Inerface o MOS, NMOS and TTL Operaing Volage Range: 2.0 o 6.0 V Low Inpu urren:.0 A High Noise Immuniy haracerisic of MOS Devices In ompliance wih he Requiremens Defined by JEDE Sandard No. 7A hip omplexiy: 264 FETs or 66 Equivalen Gaes Pb Free Packages are Available* PDIP N SUFFIX ASE 738 SOI DW SUFFIX ASE 75D MARKING DIAGRAMS M74H273AN AWLYYWWG 74H273A AWLYYWWG TSSOP DT SUFFIX ASE 948E H 273A ALYW SOEIAJ F SUFFIX ASE H273A AWLYWWG A = Assembly Locaion WL, L = Wafer Lo YY, Y = Year WW, W = Work Week G = Pb Free Package = Pb Free Package (Noe: Microdo may be in eiher locaion) ORDERING INFORMATION See deailed ordering and shipping informaion in he package dimensions secion on page 2 of his daa shee. *For addiional informaion on our Pb Free sraegy and soldering deails, please download he ON Semiconducor Soldering and Mouning Techniques Reference Manual, SOLDERRM/D. Semiconducor omponens Indusries, LL, 05 July, 05 Rev. 0 Publicaion Order Number: M74H273A/D

2 M74H273A PIN ASSIGNMENT DATA INPUTS LOK RESET D0 3 D 4 D2 7 D3 8 D4 3 D5 4 D6 7 D7 8 LOGI DIAGRAM Q0 Q Q2 Q3 Q4 Q5 Q6 Q7 PIN = V PIN 0 = NONINVERTING OUTPUTS Design rieria Value Unis Inernal Gae oun* 66 ea Inernal Gae Propagaion Delay.5 ns Inernal Gae Power Dissipaion 5.0 W Speed Power Produc.0075 pj *Equivalen o a wo inpu NAND gae. RESET Q0 D0 D Q 5 Q2 D2 D3 Q V Q7 D7 D6 Q6 Q5 D5 D4 Q4 LOK FUNTION TABLE Inpus Oupu Rese lock D Q L X X L H H H H L L H L X No hange H X No hange ORDERING INFORMATION Device Package Shipping M74H273AN PDIP 8 Unis / Rail M74H273ANG SOI 8 Unis / Rail (Pb Free) M74H273ADW SOI WIDE 38 Unis / Rail M74H273ADWG SOI WIDE 38 Unis / Rail (Pb Free) M74H273ADWR2 SOI WIDE 000 Tape & Reel M74H273ADWR2G SOI WIDE 000 Tape & Reel (Pb Free) M74H273ADT TSSOP * 75 Unis / Rail M74H273ADTG TSSOP * 75 Unis / Rail M74H273ADTR2 TSSOP * 2500 Tape & Reel M74H273ADTR2G TSSOP * 2500 Tape & Reel M74H273AF SOEIAJ 40 Unis / Rail M74H273AFG SOEIAJ (Pb Free) 40 Unis / Rail M74H273AFEL SOEIAJ 00 Tape & Reel M74H273AFELG SOEIAJ (Pb Free) 00 Tape & Reel For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD80/D. *This package is inherenly Pb Free. 2

3 M74H273A MAXIMUM RATINGS Symbol Parameer Î Value Uni V D Supply Volage (Referenced o ) Î 0.5 o V V in D Inpu Volage (Referenced o ) Î 0.5 o V V V ou D Oupu Volage (Referenced o ) Î 0.5 o V V I in D Inpu urren, per Pin Î ± ma I ou D Oupu urren, per Pin Î ± 25 ma I D Supply urren, V and Pins Î ± 50 ma P D Power Dissipaion in Sill Air, Plasic DIP Î 750 mw SOI Package 500 TSSOP Package 450 T sg Sorage Temperaure 65 o + 50 T L Lead Temperaure, mm from ase for 0 Seconds Î Plasic DIP, SOI or TSSOP Package Î 260 Maximum raings are hose values beyond which device damage can occur. Maximum raings applied o he device are individual sress limi values (no normal operaing condiions) and are no valid simulaneously. If hese limis are exceeded, device funcional operaion is no implied, damage may occur and reliabiliy may be affeced. Deraing Plasic DIP: 0 mw/ from 65 o 25 SOI Package: 7 mw/ from 65 o 25 TSSOP Package: 6. mw/ from 65 o 25 For high frequency or heavy load consideraions, see haper 2 of he ON Semiconducor High Speed MOS Daa Book (DL29/D). REOMMENDED OPERATING ONDITIONS Symbol Parameer Min Max Uni V D Supply Volage (Referenced o ) V V in, V ou D Inpu Volage, Oupu Volage (Referenced o ) 0 V V T A Operaing Temperaure, All Package Types r, f Inpu Rise and Fall Time V = 2.0 V ns (Figure ) V = 4.5 V Î V = 6.0 V This device conains proecion circuiry o guard agains damage due o high saic volages or elecric fields. However, precauions mus be aken o avoid applicaions of any volage higher han maximum raed volages o his high impedance circui. For proper operaion, V in and V ou should be consrained o he range (V in or V ou ) V. Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher or V ). Unused oupus mus be lef open. D ELETRIAL HARATERISTIS (Volages Referenced o ) Î Guaraneed Limi Î Symbol Parameer Î Tes ondiions V 55 o V Uni V IH Minimum High Level Inpu Volage Î V ou = V 0. V V I Î ou A V IL Maximum Low Level Inpu Volage Î Î V ou = 0. V V I ou Î A V OH Minimum High Level Oupu V in = V IH Î Î Volage Î I ou A V Î V Î in = V IH I ou I ou 6.0 ma Î I ou 7.8 ma V OL Maximum Low Level Oupu V in = V IL V Volage I ou Î A Î V in = V IL I ou 2.4 ma I Î ou I ou 7.8 ma

4 M74H273A D ELETRIAL HARATERISTIS (Volages Referenced o ) Î Guaraneed Limi V 55 o Symbol Parameer Tes ondiions V Uni I in Maximum Inpu Leakage urren V in = V or 6.0 Î ± 0. ±.0 ±.0 A I OZ Maximum Three Sae Leakage Î Oupu in High Impedance Sae Î urren Î V in = V IL or V IH 6.0 ± 0.5 ± 5.0 Î ± 0 A V ou = V or I Maximum Quiescen Supply Î V in = V or Î urren (per Package) Î I ou = 0 A Î 60 A NOTE: Informaion on ypical parameric values can be found in haper 2 of he ON Semiconducor High Speed MOS Daa Book (DL29/D). A ELETRIAL HARATERISTIS ( L = 50 pf, Inpu r = f = 6.0 ns) Guaraneed Limi V 55 o Symbol Parameer V Uni Î f max Maximum lock Frequency ( Duy ycle) MHz (Figures and 4) Î PLH Maximum Propagaion Delay, lock o Q ns PHL (Figures and 4) Î PHL Maximum Propagaion Delay, Rese o Q ns (Figures 2 and 4) Î TLH Maximum Oupu Transiion Time, Any Oupu ns THL (Figures and 4) Î Maximum Inpu apaciance pf in NOTE: For propagaion delays wih loads oher han 50 pf, and informaion on ypical parameric values, see haper 2 of he ON Semiconducor High Speed MOS Daa Book (DL29/D). 25, V = 5.0 V PD Power Dissipaion apaciance (Per Enabled Oupu)* 48 pf * Used o deermine he no load dynamic power consumpion: P D = PD V 2 f + I V. For load consideraions, see haper 2 of he ON Semiconducor High Speed MOS Daa Book (DL29/D). 4

5 M74H273A Î TIMING REQUIREMENTS ( L = 50 pf, Inpu r = f = 6.0 ns) Guaraneed Limi V Î 55 o 25 Î SymbolÎ Parameer Figure Vols Min Max Min Max Min Max Uni su Î Minimum Seup Time, Daa o lock ns Î h Î Minimum Hold Time, lock o Daa ns rec Î Minimum Recovery Time, Rese Inacive o ns lock w Î Minimum Pulse Widh, lock ns Î w Minimum Pulse Widh, Rese ns Î r, f Maximum Inpu Rise and Fall Times ns

6 M74H273A SWITHING WAVEFORMS r f V w LOK 90% 0% w RESET PHL V Q 90% 0% PLH /fmax TLH PHL THL Q LOK rec V Figure. Figure 2. VALID DATA su h V LOK V D0 3 D R Q 2 Q0 Figure 3. D 4 D R Q 5 Q D2 7 D R Q 6 Q2 DEVIE UNDER TEST TEST POINT OUTPUT L * DATA INPUTS D3 8 D R Q 9 D4 3 D R Q 2 D5 4 D R Q 5 Q3 Q4 Q5 NONINVERTING OUTPUTS *Includes all probe and jig capaciance Figure 4. Tes ircui D6 7 D R Q 6 D7 8 D R Q 9 Q6 Q7 Figure 5. Expanded Logic Diagram 6

7 M74H273A PAKAGE DIMENSIONS PDIP N SUFFIX PLASTI DIP PAKAGE ASE ISSUE E A 0 B NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, ONTROLLING DIMENSION: INH. 3. DIMENSION L TO ENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INLUDE MOLD FLASH. T SEATING PLANE G E F N K D PL 0.25 (0.00) M T A M L M J PL 0.25 (0.00) M T B M INHES MILLIMETERS DIM MIN MAX MIN MAX A B D E BS.27 BS F G 0.00 BS 2.54 BS J K L BS 7.62 BS M N SOI DW SUFFIX ASE 75D 05 ISSUE G H 0X 0.25 M B M D E A h X 45 NOTES:. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANES PER ASME Y4.5M, DIMENSIONS D AND E DO NOT INLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 PER SIDE. 5. DIMENSION B DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.3 TOTAL IN EXESS OF B DIMENSION AT MAXIMUM MATERIAL ONDITION. X B 0.25 M T A S 8X e 0 B B S A A T SEATING PLANE L MILLIMETERS DIM MIN MAX A A B D E e.27 BS H h L

8 M74H273A PAKAGE DIMENSIONS TSSOP DT SUFFIX ASE 948E 02 ISSUE B 0.5 (0.006) T L U 2X L/2 0.5 (0.006) T U S PIN IDENT S 0.00 (0.004) T SEATING PLANE X K REF 0.0 (0.004) M T U S V S 0 A V D G H B U J J N N K K ÍÍÍÍ ÍÍÍÍ SETION N N F DETAIL E 0.25 (0.00) DETAIL E M W NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE K DIMENSION AT MAXIMUM MATERIAL ONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G 0.65 BS BS H J J K K L 6.40 BS BS M

9 M74H273A PAKAGE DIMENSIONS SOEIAJ F SUFFIX ASE ISSUE O e E H E 0 Z D A L E Q M L DETAIL P VIEW P c NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXEED 0.5 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL ONDITION. DAMBAR ANNOT BE LOATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPAE BETWEEN PROTRUSIONS AND ADJAENT LEAD TO BE 0.46 ( 0.08). b 0.3 (0.005) M A 0.0 (0.004) MILLIMETERS INHES DIM MIN MAX MIN MAX A A b c D E e.27 BS BS H E L L E M Q Z

10 M74H273A ON Semiconducor and are regisered rademarks of Semiconducor omponens Indusries, LL (SILL). SILL reserves he righ o make changes wihou furher noice o any producs herein. SILL makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SILL assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Typical parameers which may be provided in SILL daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SILL does no convey any license under is paen righs nor he righs of ohers. SILL producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he SILL produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SILL producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SILL and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SILL was negligen regarding he design or manufacure of he par. SILL is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion ener for ON Semiconducor P.O. Box 632, Phoenix, Arizona USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderli@onsemi.com N. American Technical Suppor: Toll Free USA/anada Japan: ON Semiconducor, Japan usomer Focus ener 2 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconducor Websie: Order Lieraure: hp:// For addiional informaion, please conac your local Sales Represenaive. M74H273A/D

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