MC74HC390. Dual 4 Stage Binary Ripple Counter with 2 and 5 Sections. High Performance Silicon Gate CMOS
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1 Dual 4Sage Binary Ripple ouner wih 2 and 5 Secions HighPerformance Siliconae OS The 54/74H30 is idenical in pinou o he LS30. The device inpus are compaible wih sandard OS oupus; wih pullup resisors, hey are compaible wih LSTTL oupus. This device consiss of wo independen 4bi couners, each composed of a dividebywo and a dividebyfive secion. The dividebywo and dividebyfive couners have separae clock inpus, and can be cascaded o implemen various combinaions of 2 and/or 5 up o a 100 couner. lipflops inernal o he couners are riggered by higholow ransiions of he clock inpu. A separae, asynchronous rese is provided for each 4bi couner. Sae changes of he Q oupus do no occur simulaneously because of inernal ripple delays. Therefore, decoded oupu signals are subjec o decoding spikes and should no be used as clocks or srobes excep when gaed wih he lock of he H30. Oupu Drive apabiliy: 10 LSTTL Loads Oupus Direcly Inerface o OS, NOS, and TTL Operaing olage Range: 2 o 6 Low Inpu urren: 1 μa High Noise Immuniy haracerisic of OS Devices In ompliance wih he Requiremens Defined by EDE Sandard No 7A hip omplexiy: 244 ETs or 61 Equivalen aes LO A LOI DIARA 1, 15 2 OUNTER 3, N SUIX PLASTI PAAE ASE D SUIX SOI PAAE ASE 751B05 ORDERIN INORATION 54HXXX 74HXXXN 74HXXXD LO A a a SUIX ERAI PAAE ASE eramic Plasic SOI PIN ASSINENT a LO B a a Q a a ND LO A b b b LO B b b Q b b LO B 4, 12 2, 14 5 OUNTER PIN = PIN 8 = ND 5, 11 6, 10 Q 7, UNTION TABLE lock A B Rese Acion X X H Rese 2 and 5 X L Incremen 2 X L Incremen 5 Semiconducor omponens Indusries, LL, 2006 une, 2006 Rev. 7 1 Publicaion Order Number: 74H30/D
2 AXIU RATINS* SymbolÎÎ Parameer Î alue Uni ÎÎ D Supply olage (Referenced o ND) Î 0.5 o in ÎÎ D Inpu olage (Referenced o ND) Î 1.5 o ou D Oupu olage (Referenced o ND) 0.5 o ÎÎ I in D Inpu urren, per Pin ± 20 ma I ou D Oupu urren, per Pin ± 25 ma I D Supply urren, and ND Pins ± 50 ma P D Power Dissipaion in Sill Air,Plasic or eramic DIP 750 ÎÎ SOI Package Î 500 mw T sg ÎÎ Sorage Temperaure Î 65 o T L ÎÎ Lead Temperaure, 1 mm from ase for 10 Seconds Î (Plasic or SOI DIP) Î 260 (eramic DIP) *aximum Raings are hose values beyond which damage o he device may occur. uncional operaion should be resriced o he Recommended Operaing ondiions. Deraing Plasic DIP: 10 mw/ from 65 o 125 eramic DIP: 10 mw/ from 100 o 125 SOI Package: 7 mw/ from 65 o 125 or high frequency or heavy load consideraions, see haper 2 of he oorola HighSpeed OS Daa Book (DL12/D). REOENDED OPERATIN ONDITIONS ÎÎ Symbol Parameer in ÎÎ ax Uni D Supply olage (Referenced o ND) 2.0 ÎÎ 6.0 in, ou ÎÎ ÎÎ D Inpu olage, Oupu olage (Referenced o ND) 0 T A Operaing Temperaure, All Package Types 55 ÎÎ r, f Inpu Rise and all Time ÎÎ = 2.0 ÎÎ (igure 1) = 4.5 ÎÎ 0 0 ÎÎ ns = 6.0 D ELETRIAL HARATERISTIS (olages Referenced o ND) uaraneed Limi 55 oî Symbol Parameer Tes ondiions Uni ÎÎ IH inimum HighLevel Inpu ÎÎ olage Î ou = 0.1 or I ou 20 μa IL ÎÎ aximum LowLevel Inpu Î ou = 0.1 or olage I ÎÎ ou 20 μa OH ÎÎ inimum HighLevel Oupu Î in = IH or IL olage I Î ou 20 μa ÎÎ Î in = IH or IL I ou 4.0 ma Î I ou 5.2 ma OL ÎÎ aximum LowLevel Oupu Î in = IH or IL olage I Î ou 20 μa Î in = IH or IL I ou 4.0 maîî Î I ou 5.2 ma I in ÎÎ aximum Inpu Leakage urren Î in = or ND 6.0 ± 0.1 ± 1.0 ± 1.0 μa I ÎÎ aximum Quiescen Supply Î in = or ND ÎÎ μa urren (per Package) I ou = 0 μa This device conains proecion circuiry o guard agains damage due o high saic volages or elecric fields. However, precauions mus be aken o avoid applicaions of any volage higher han maximum raed volages o his highimpedance circui. or proper operaion, in and ou should be consrained o he range ND ( in or ou ). Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher ND or ). Unused oupus mus be lef open. NOTE: Informaion on ypical parameric values can be found in haper 2 of he oorola HighSpeed OS Daa Book (DL12/D). 2
3 A ELETRIAL HARATERISTIS ( L = 50 p, Inpu f = f = 6 ns) uaraneed Limi Symbol Parameer 55 oî Uni ÎÎ f Î max aximum lock requency ( Duy ycle) Hz ÎÎ (igures 1 and 3) Î PLH, Î aximum Propagaion Delay, lock A o QA ns Î PHL (igures 1 and 3) ÎÎ Î PLH ÎÎ, aximum Propagaion Delay, lock A o Q Î PHL Î (QA conneced o lock B) ns (igures 1 and 3) ÎÎ Î PLH, aximum Propagaion Delay, lock B o QB ns PHL Î (igures 1 and 3) Î PLH, Î aximum Propagaion Delay, lock B o Q ns Î PHL (igures 1 and 3) Î PLH, Î aximum Propagaion Delay, lock B o QD ÎÎ Î PHL Î (igures 1 and 3) ns ÎÎ Î PHL aximum Propagaion Delay, Rese o any Q ns Î (igures 2 and 3) Î TLH, Î aximum Oupu Transiion Time, Any Oupu ns Î THL (igures 1 and 3) Î aximum Inpu apaciance p in NOTES: 1. or propagaion delays wih loads oher han 50 p, see haper 2 of he oorola HighSpeed OS Daa Book (DL12/D). 2. Informaion on ypical parameric values can be found in haper 2 of he oorola HighSpeed OS Daa Book (DL12/D). PD Power Dissipaion apaciance (Per ouner)* 25, = 5.0 * Used o deermine he noload dynamic power consumpion: P D = PD 2 f + I. or load consideraions, see haper 2 of he oorola HighSpeed OS Daa Book (DL12/D). 35 p TIIN REQUIREENTS (Inpu r = f = 6 ns) uaraneed Limi 55 o ÎÎ Symbol Parameer Uni ÎÎ Î rec inimum Recovery Time, Rese Inacive o lock A or lock B ns Î (igure 2) Î w Î inimum Pulse Widh, lock A, lock B ns (igure 1) Î w Î inimum Pulse Widh, Rese ÎÎ Î (igure 2) ns ÎÎ Î f, f aximum Inpu Rise and all Times ns Î (igure 1) NOTE: Informaion on ypical parameric values can be found in haper 2 of he oorola HighSpeed OS Daa Book (DL12/D). 3
4 PIN DESRIPTIONS INPUTS lock A (Pins 1, 15) and lock B (Pins 4, 15) lock A is he clock inpu o he 2 couner; lock B is he clock inpu o he 5 couner. The inernal flipflops are oggled by higholow ransiions of he clock inpu. ONTROL INPUTS Rese (Pins 2, 14) Asynchronous rese. A high a he Rese inpu prevens couning, reses he inernal flipflops, and forces hrough low. OUTPUTS (Pins 3, 13) Oupu of he 2 couner., Q, (Pins 5, 6, 7,, 10, 11) Oupus of he 5 couner. is he mos significan bi. is he leas significan bi when he couner is conneced for BD oupu as in igure 4. is he leas significan bi when he couner is operaing in he biquinary mode as in igure 5. SWITHIN WAEORS LO 10% f 0% 10% w 1/f max r ND PHL w ND Q PLH PHL Q 10% 0% TLH THL LO rec ND igure 1. igure 2. TEST IRUIT TEST POINT DEIE UNDER TEST OUTPUT L * *Includes all probe and jig capaciance igure 3. 4
5 EXPANDED LOI DIARA LO A 1, 15 Q D Q R 3, 13 LO B 4, 12 Q D Q R 5, 11 Q D Q R 6, 10 Q D Q R 7, 2, 14 TIIN DIARA ( onneced o lock B) LO A Q 5
6 APPLIATIONS INORATION Each half of he 54/74H30 has independen 2 and 5 secions (excep for he Rese funcion). The 2 and 5 couners can be conneced o give BD or biquinary (25) coun sequences. If Oupu is conneced o he lock B inpu (igure 4), a decade divider wih BD oupu is obained. The funcion able for he BD coun sequence is given in Table 1. To obain a biquinary coun sequence, he inpu signals conneced o he lock B inpu, and oupu is conneced o he lock A inpu (igure 5). provides a duy cycle oupu. The biquinary coun sequence funcion able is given in Table 2. oun 1. BD oun Sequence* Oupu Q 0 L L L L 1 L L L H 2 L L H L 3 L L H H 4 L H L L 5 L H L H 6 L H H L 7 L H H H 8 H L L L H L L H * conneced o lock B inpu. 6
7 oun 2. BiQuinary oun Sequence** Oupu Q 0 L L L L 1 L L L H 2 L L H L 3 L L H H 4 L H L L 8 H L L L H L L H 10 H L H L 11 H L H H 12 H H L L ** conneced o lock A inpu. ONNETION DIARAS LO A 1, 15 3, 13 1, LO A OUNTER OUNTER 3, 13 LO B 4, 12 5 OUNTER 5, 11 6, 10 7, Q LO B 4, 12 5 OUNTER 5, 11 6, 10 7, Q 2, 14 2, 14 igure 4. BD oun igure 5. Bi-Quinary oun 7
8 OUTLINE DIENSIONS A 1 8 B SUIX ERAI PAAE ASE ISSUE L NOTES: 1. DIENSIONIN AND TOLERANIN PER ANSI Y14.5, ONTROLLIN DIENSION: INH. 3. DIENSION L TO ENTER O LEAD WHEN ORED PARALLEL. 4. DI AY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE ERAI BODY. T SEATIN PLANE E N D PL 0.25 (0.010) T A S PL 0.25 (0.010) T B S DI A B D E L N INHES IN AX BS BS BS ILLIETERS IN AX BS BS BS A 1 8 H S B T SEATIN PLANE D PL 0.25 (0.010) T A N SUIX PLASTI PAAE ASE ISSUE R L NOTES: 1. DIENSIONIN AND TOLERANIN PER ANSI Y14.5, ONTROLLIN DIENSION: INH. 3. DIENSION L TO ENTER O LEADS WHEN ORED PARALLEL. 4. DIENSION B DOES NOT INLUDE OLD LASH. 5. ROUNDED ORNERS OPTIONAL. DI A B D H L S INHES IN AX BS BS ILLIETERS IN AX BS 1.27 BS T SEATIN PLANE 1 8 A D PL B 0.25 (0.010) T B S A S D SUIX PLASTI SOI PAAE ASE 751B05 ISSUE P 8 PL 0.25 (0.010) B R X 45 NOTES: 1. DIENSIONIN AND TOLERANIN PER ANSI Y14.5, ONTROLLIN DIENSION: ILLIETER. 3. DIENSIONS A AND B DO NOT INLUDE OLD PROTRUSION. 4. AXIU OLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIENSION D DOES NOT INLUDE DABAR PROTRUSION. ALLOWABLE DABAR PROTRUSION SHALL BE (0.005) TOTAL IN EXESS O THE D DIENSION AT AXIU ATERIAL ONDITION. DI A B D P R ILLIETERS IN AX INHES IN AX BS BS
9 ON Semiconducor and are regisered rademarks of Semiconducor omponens Indusries, LL (SILL). SILL reserves he righ o make changes wihou furher noice o any producs herein. SILL makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SILL assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Typical parameers which may be provided in SILL daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SILL does no convey any license under is paen righs nor he righs of ohers. SILL producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he SILL produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SILL producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SILL and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SILL was negligen regarding he design or manufacure of he par. SILL is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLIATION ORDERIN INORATION LITERATURE ULILLENT: Lieraure Disribuion ener for ON Semiconducor P.O. Box 53, Denver, olorado USA Phone: or Toll ree USA/anada ax: or Toll ree USA/anada orderli@onsemi.com N. American Technical Suppor: Toll ree USA/anada Europe, iddle Eas and Africa Technical Suppor: Phone: apan usomer ocus ener Phone: ON Semiconducor Websie: Order Lieraure: hp:// or addiional informaion, please conac your local Sales Represenaive 74H30/D
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Small Signal Fas Swiching Diode Feaures These diodes are also available in oher case syles including he DO- case wih he ype designaion N8, he MiniMELF case wih he ype designaion LL8, and he SOT- case wih
MC14017B. Decade Counter
M407B ecade ouner The M407B is a five sage Johon decade couner wih buil in code converer. High speed operaion and spike free oupus are obained by use of a Johon decade couner design. The en decoded oupus
MC14040B. 12-Bit Binary Counter
M4040B 2Bi Binary ouner The M4040B 2sage binary couner is coruced wih MOS Phannel and Nhannel enhancemen mode devices in a single monolihic srucure. This par is designed wih an inpu wave shaping circui
MC14099B. 8 Bit Addressable Latches
MC0B Bi ddressable Laches The MC0B is an bi addressable lach. Daa is enered in serial form when he appropriae lach is addressed (via address pi 0,, ) and wrie disable is in he low sae. For he MC0B he inpu
AMIS LIN Transceiver
AMIS-000 Transceiver General Descripion The single wire ransceiver AMIS 000 is a monolihic inegraed circui in a SOIC 8 package. I works as an inerface beween he proocol conroller and he physical bus. The
SN74LS125A, SN74LS126A. Quad 3 State Buffers LOW POWER SCHOTTKY. LS125A LS126A TRUTH TABLES ORDERING INFORMATION
Quad 3 State Buffers V CC E D O E D O 4 3 2 0 9 8 LOW POWER SCHOTTKY 2 3 4 5 6 E D O E D O LS25A GND V CC E D O E D O 4 3 2 0 9 8 4 PLASTIC N SUFFIX CASE 646 LS25A INPUTS 2 3 4 5 6 E D O E LS26A D O GND
AND9120/D. An Introduction to LDO Early Warning Function APPLICATION NOTE
An nroducion o LDO Early Warning Funcion Absrac n oday s world of high speed, high power processors, new demands have been placed on he power source regulaor. One example is he need o inform he processor
PI74STX1G126. SOTiny Gate STX Buffer with 3-State Output. Features. Descriptio n. Block Diagram. Pin Configuration
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MC74VHC1GT125. Noninverting Buffer / CMOS Logic Level Shifter with LSTTL Compatible Inputs
C74CGT Noninvering Buffer / COS ogic evel Shifer wih STT Compaible Inpus The C74CGT is a single gae noninvering buffer fabricaed wih silicon gae COS echnology. I achieves high speed operaion similar o
Type Marking Pin Configuration Package SMBT3904/MMBT3904 SOT23 SMBT3904S 2=E 1=B 3=C 1=E1 2=B1 3=C2
SMBT94...MMBT94 NPN Silicon Swiching Transisors High D curren gain:. ma o ma Low collecoremier sauraion volage For SMBT94S: Two (galvanic) inernal isolaed ransisors wih good maching in one package omplemenary
MC10H Bit Arithmetic Logic Unit/ Function Generator
C0H8 4Bit Arithmetic Logic Unit/ unction Generator The C0H8 is a highspeed arithmetic logic unit capable of performing 6 logic operatio and 6 arithmetic operatio on two fourbit words. ull internal carry
ML ML Digital to Analog Converters with Serial Interface
OS LSI L L Digital to Analog onverters with Serial Interface Legacy Device: otorola/reescale, The L and L are low cost 6 bit D/A converters with serial interface ports to provide communication with OS
High Speed Optocoupler, 1 MBd, Phtotdiode with Transistor Output
Vishay Semiconducors High Speed Opocoupler, FEATURES Isolaion es volages: 3 V RMS TTL compaible High bi raes:. Mbi/s i798 DESCRIPTION NC A C NC The N3 and N3 are opocouplers wih a GaAIAs infrared emiing
HV513 8-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs, POL, Hi-Z, and Short Circuit Detect
H513 8-Channel Serial o Parallel Converer wih High olage Push-Pull s, POL, Hi-Z, and Shor Circui Deec Feaures HCMOS echnology Operaing oupu volage of 250 Low power level shifing from 5 o 250 Shif regiser
Dual 4-Input AND Gate
TENIAL DATA Dual 4-Input AND ate The is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the Dual 4-input AND function. Outputs Directly Interface
High Speed Optocoupler, 1 MBd, Photodiode with Transistor Output. i179081
High Speed Opocoupler, MBd, Phoodiode wih Transisor Oupu Feaures Isolaion Tes Volage: V RMS TTL Compaible High Bi Raes:. Mbi/s High Common-Mode Inerference Immuniy Bandwidh. MHz Open-Collecor Oupu Exernal
High Speed Optocoupler, 1 MBd, Photodiode with Transistor Output. i179081
High Speed Opocoupler, MBd, Phoodiode wih Transisor Oupu Feaures Isolaion Tes Volage: V RMS TTL Compaible High Bi Raes:. Mbi/s High Common-Mode Inerference Immuniy Bandwidh. MHz Open-Collecor Oupu Exernal
SN74LS145MEL. 1 of 10 Decoder/Driver Open Collector LOW POWER SCHOTTKY
of 0 Decoder/Driver Open Collector The SN74LS45, -of-0 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 0-digit incandescent displays. All outputs remain off for
Triple 3-Input NOR Gate
TENIAL DATA IN4T2A Triple 3-Input NOR ate The IN4T2A is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the Triple 3-input NOR function. Outputs
NCN5150. Wired M-BUS Slave Transceiver
Wired M-BUS Slave Transceiver Descripion The is a single-chip inegraed slave ransceiver for use in wo-wire Meer Bus (M-BUS) slave devices and repeaers. The ransceiver provides all of he funcions needed
SN74LS157MEL. Quad 2 Input Multiplexer LOW POWER SCHOTTKY
Quad 2 Input Multiplexer The LSTTL/ MSI is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs
SFH636. Pb Pb-free. Optocoupler, Phototransistor Output, 1 Mbd, 10 kv/ms CMR, Split CollectorTransistor Output VISHAY. Vishay Semiconductors
Opocoupler, Phooransisor Oupu, Mbd, kv/ms CMR, Spli CollecorTransisor Oupu Feaures High Speed Opocoupler wihou Base Connecion Isolaion Tes Volage: 3 V RMS GaAlAs Emier Inegraed Deecor wih Phoo diode and
SFH636. Optocoupler, Phototransistor Output, 1 Mbd, 10 kv/ms CMR, Split CollectorTransistor Output VISHAY. Vishay Semiconductors.
Opocoupler, Phooransisor Oupu, Mbd, kv/ms CMR, Spli CollecorTransisor Oupu Feaures High Speed Opocoupler wihou Base Connecion Isolaion Tes Volage: 3 V RMS GaAlAs Emier Inegraed Deecor wih Phoo diode and
74HC of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The 74HC38 is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are
SN74LS132MEL. Quad 2 Input Schmitt Trigger NAND Gate LOW POWER SCHOTTKY
Quad 2 Input Schmitt Trigger NAND Gate The SN74LS32 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly
High Performance Silicon Gate CMOS
SEIONDUTOR TENI DT igh Performance Silicon ate OS The 5/7T00 may be used as a level converter for interfacing TT or NOS outputs to high speed OS inputs. The T00 is identical in pinout to the S00. Output
High Speed Optocoupler, 1 MBd, Transistor Output. i179081
High Speed Opocoupler, MBd, Transisor Oupu Feaures Isolaion Tes Volage: V RMS TTL Compaible High Bi Raes:. Mbi/s High Common-mode Inerference Immuniy Bandwidh. MHz Open-collecor Oupu Exernal Base Wiring
MC14070B, MC14077B CMOS SSI. Quad Exclusive OR and NOR Gates
C070B, C077B COS SSI Quad Exclusive OR and NOR Gates The C070B quad exclusive OR gate and the C077B quad exclusive NOR gate are constructed with OS Pchannel and Nchannel enhancement mode devices in a single
SFH6345. High Speed Optocoupler, 1 Mbd, 15 kv/ms CMR, Transistor Output Features VISHAY. Vishay Semiconductors. Agency Approvals.
High Speed Opocoupler, Mbd, kv/ms CMR, Transisor Oupu Feaures Direc Replacemen for HCPL43 High Speed Opocoupler wihou Base Connecion Isolaion Tes Volage: 3 V RMS GaAlAs Emier Inegraed Deecor wih Phoo diode
MC Bit Magnitude Comparator
Bit Magnitude Comparator The MC0 is a high speed expandable bit comparator for comparing the magnitude of two binary words. Two outputs are provided: and. A = B can be obtained by NORing the two outputs
MC74AC109, MC74ACT109. Dual JK Positive Edge Triggered Flip Flop
MC9, MC9 Dual JK Positive EdgeTriggered FlipFlop The MC9/9 coists of two highspeed completely independent traition clocked JK flipflops. The clocking operation is independent of rise and fall times of
SFH6345. Pb Pb-free. High Speed Optocoupler, 1 Mbd, 15 kv/ms CMR, Transistor Output. Vishay Semiconductors
High Speed Opocoupler, Mbd, kv/ms CMR, Transisor Oupu Feaures Direc Replacemen for HCPL43 High Speed Opocoupler wihou Base Connecion Isolaion Tes Volage: 3 V RMS GaAlAs Emier Inegraed Deecor wih Phoo diode
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in
onlinecomponents.com OPTOLOGIC OPTICAL INTERRUPTER SWITCH QVE00112 PACKAGE DIMENSIONS FEATURES 6/10/04
PACKAGE DIMENSIONS.714 (18.15).123 (3.125).189 (4.82).14 (.356).327 (8.31) Ø 3.3.1 (2.54).173 (4.4) OPTICAL C L 13.78 (35) ±.275 (7).316 (8.25) GRN WHT.464 (11.8).143 (3.625).118 (3.) GRY.173 (4.4).246.276
74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
SOTiny Gate STX. Input. Descriptio n. Features. Block Diagram. Pin Configuration. Recommended Operating Conditions (1) Pin Description.
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SN74LS147, SN74LS Line to 4 Line and 8 Line to 3 Line Priority Encoders LOW POWER SCHOTTKY
0 Line to Line and 8 Line to 3 Line Priority Encoders The SN7LS7 and the SN7LS8 are Priority Encoders. They provide priority decoding of the inputs to eure that only the highest order data line is encoded.
Dual 4-Input AND Gate
TENIAL DATA IN42A Dual 4-Input AND ate The IN42A is high-speed Si-gate MOS device and is pin compatible with pullup resistors with low power Schottky TTL (LSTTL). The device provide the Dual 4-input AND
NCN5150. Wired M-BUS Slave Transceiver
Wired M-BUS Slave Transceiver Descripion The is a single-chip inegraed slave ransceiver for use in wo-wire Meer Bus (M-BUS) slave devices and repeaers. The ransceiver provides all of he funcions needed
74HC244 Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with
High Performance Silicon Gate CMOS
EIONDUTOR TEHNIA DATA HighPerformance iliconate O The 54/74H3A is identical in pinout to the 3. The device inputs are compatible with standard O outputs; with pullup resistors, they are compatible with
SN74LS175MEL. Quad D Flip Flop LOW POWER SCHOTTKY
uad Flip Flop The LSTTL/MSI SN74LS75 is a high speed uad Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the inputs is stored
MC74HC4020A. 14-Stage Binary Ripple Counter. High Performance Silicon Gate CMOS
M74H20A 4-Stage Binary Ripple ounter High Performance Silicon Gate MOS The M7420A is identical in pinout to the standard MOS M20B. The device inputs are compatible with standard MOS outputs; with pullup
74HCT245. Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs. High-Performance Silicon-Gate CMOS
Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS The 74HCT245 is identical in pinout to LS245. The device has TTL-Compatible Inputs. The HCT245
High Performance Silicon Gate CMOS
SEONDUTOR TEHNAL HighPerformance Siliconate OS The H is identical in pinout to the LS. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with LSTTL outputs.
NLSV2T Bit Dual-Supply Inverting Level Translator
2-Bit Dual-Supply Inverting Level Translator The NLSV2T240 is a 2 bit configurable dual supply voltage level translator. The input A n and output B n ports are designed to track two different power supply
MC74AC132, MC74ACT132. Quad 2 Input NAND Schmitt Trigger
MC74AC32, MC74ACT32 Quad 2 Input NAND Schmitt Trigger The MC74AC/74ACT32 contains four 2 input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter free
MC14020B. 14-Bit Binary Counter
M4020B 4-Bit Binary ounter The M4020B 4stage binary counter is cotructed with MOS Phannel and Nhannel enhancement mode devices in a single monolithic structure. This part is designed with an input wave
MC74AC138, MC74ACT of 8 Decoder/Demultiplexer
1 of 8 Decoder/Demultiplexer The MC74AC138/74ACT138 is a high speed 1 of 8 decoder/demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple
NE522 High Speed Dual Differential Comparator/Sense Amp
HighSpeed DualDifferential Comparator/Sense Amp Features 5 ns Maximum Guaranteed Propagation Delay 0 A Maximum Input Bias Current TTL-Compatible Strobes and Outputs Large Common-Mode Input oltage Range
SN74LS151MEL. 8 Input Multiplexer LOW POWER SCHOTTKY
8 Input Multiplexer The TTL/MSI SN74LS5 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS5 can be used as
LOW POWER SCHOTTKY. ESD > 3500 Volts. GUARANTEED OPERATING RANGES ORDERING INFORMATION V CC 8 7 GND
ESD > 3500 Volts V CC 8 4 3 2 0 9 LOW POWER SCHOTTKY 2 3 4 5 6 7 GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage 4.75 5.0 5.25 V T A Operating Ambient Temperature
MC74HCT138A. 1 of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC74HCT38A is identical in pinout to the LS38. The HCT38A may be used as a level converter for interfacing