Semiconductor Devices and Models

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1 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan - 郭泰豪, nalog I Design, 07 Semiconducor Devices and Models Resisor apacior Diode Bipolar Transisor MOSFET SPIE Model ppendix

2 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan - 郭泰豪, nalog I Design, 07 Resisors Maerial Diffusion layers: e.g. n+, p+, well onducors : e.g. polysilicon, meal meal SiO SiO n + p-subsrae Resisance calculaion R=ρ/=ρ/W= R /W R =ρ/ is shee resisance Resisiviy W ross-secion area, Resisiviy=ρ R Shee resisance W Shee resisance = R R口 R W

3 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -3 郭泰豪, nalog I Design, 07 Resisors (on.) Graphical calculaions from shee resisance W R W W W W ½ 7.5R W W W W/.5 R R (volage coefficien) and T (emperaure coefficien) of R (or ) nonlineariy THD

4 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -4 郭泰豪, nalog I Design, 07 apaciors Meal-or polysilicon-over-diffusion is volage dependen meal SiO SiO n + meal l Meal-Insulaor-meal High lineariy meal n meal n- p - Iner-meal and inra-meal Iner: differen layer Inra: same layer meal n ia meal n- ia

5 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -5 郭泰豪, nalog I Design, 07 Resiser raio-maching consideraions Resisor onac Meal R w R w 3 R3 w R4 w

6 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -6 郭泰豪, nalog I Design, 07 apacior raio-maching consideraions X 3 4 X 7 7 X X X X

7 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -7 郭泰豪, nalog I Design, 07 Diode ccepor ions Donor ions I O Holes Elecrons I S p-ype -Xp 0 Xn n-ype x T O Depleion Region I I S (exp T ) kt where T q I S sauraion curren K Xp [ K Xn [ ( q ) S 0 0 R D / ] ( q ) N N (N N S 0 0 R / ] N D N (N N K S relaive permiivi y of silicon 0 buli in poenial reverse bias volage R D D ) )

8 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07-8 Juncion apaciance For abrup juncion: For graded juncion / D D R 0 0 S ] N N N N ) ( [qk Q Q 0 R j0 / D D R 0 0 S R j ] N N N N ) ( qk [ d dq ] ] N N N N qk [ [ / D D 0 0 S j0 m D D R 0 0 S ] ) N (N N N ) ( [qk Q Q m 0 R j0 m R 0 m D D 0 S R j ) ( ) ( ] N N N N m)[qk ( d dq ] ] N N N N m)[qk ( [ m 0 m D D 0 S j0 m depend on he doping profile m /3 for a linearly graded juncion

9 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -9 郭泰豪, nalog I Design, 07 Diode Model D Model For < r (off) For > r (on) R f di ( d ) D I e S T / T I T D I S I D r O I D + - R f r Small Signal Model For forward-biased diode rd I T D Diffusion capaciance: Juncion capaciance: d r T d j j0 r d d j Normally, d >> j ( d 00 j ) j0 : apaciance a 0- bias T : Diode ransi ime

10 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -0 郭泰豪, nalog I Design, 07 Bipolar Process erical and laeral ransisor in a bipolar process collecor base base collecor emier emier n n + n + n + p p p p n + + n n + n + n p + n p erical PNP or NPN high β aeral PNP or NPN low β verical npn ransisor laeral pnp ransisor

11 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan - 郭泰豪, nalog I Design, 07 BJT Model: Ebers-Moll model (D Model) α R I R α F I F NPN PNP I E E EB I F - - I R B I B I B B BE I E B I B B BE I E I B B E I E E I E I I E I S -I α e S R e BB BB T T - I α -I S S R e e B B T T

12 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan - 郭泰豪, nalog I Design, 07 Small Signal BJT Model Emier luminum conacs ollecor P n + n + P n P + Base Isolaion island p subsrae

13 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -3 郭泰豪, nalog I Design, 07 Small Signal BJT Model (on.) Sub r μ BS B r b + B R r n BE v be g m v be r o S - R E Sub E

14 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -4 郭泰豪, nalog I Design, 07 MOS Transisors MOS srucure NMOS GTE ONDUTOR INSUTOR symbol DRIN GTE SOURE n n P - DOPED SEMIONDUTOR SUBSTRTE DRIN SUBSTRTE SOURE PMOS ONDUTOR symbol DRIN GTE INSUTOR GTE p n - DOPED p SOURE DRIN SUBSTRTE SOURE SEMIONDUTOR SUBSTRTE

15 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -5 郭泰豪, nalog I Design, 07 MOS Transisors (on.) -Enhancemen NMOS Source Gae Drain s gs D P Source Gae Drain Meal Polysilicon Oxide n-diffusion p-diffusion -Depleion NMOS P Implan p-subsrae n-depleion subsrae -Enhancemen PMOS Source Gae Drain -Depleion PMOS Source Gae Drain n n Implan

16 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -6 郭泰豪, nalog I Design, 07 MOS Transisor Symbol (on.) nmos enhancemen nmos depleion pmos enhancemen

17 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -7 郭泰豪, nalog I Design, 07 Example : nmos MOS Transisor Operaion gs >, ds = 0 (linear region) GND (0 ) gs v d gae ( inversion layer) 0 hannel ( inversion layer) gs >, ds = gs - GND (0 ) gs 0

18 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -8 郭泰豪, nalog I Design, 07 MOS Transisor Operaion (on.) Example : nmos gs >, ds > gs - (sauraion region) GND (0 ) 0 Pinch off, Xd I- characerisic of nmos INER REGION gs - = ds STURTION REGION gs4 I ds gs3 gs gs ds

19 arge Signal Behavior of MOSFETs Threshold volage arge-signal I- I 0 0 qε W SiO f where γ GS N SB qε - SiO f f N kw SB and - GS OX f k ε 0 ε If depleion-layer widh X d is considered eff = -X d I kw GS hannel lengh modulaion I kw d GS d e I eff r o eff I I eff Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -9 郭泰豪, nalog I Design, 07 I eff dx d eff d dx d d I kw GS

20 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -0 郭泰豪, nalog I Design, 07 Small Signal Model of MOSFETs in Sauraion Equivalen circui model G + gd D v gs g m v gs g mb v bs r ds - gs - S v bs + sb gb db B

21 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan - 郭泰豪, nalog I Design, 07 Small Signal Model of MOSFETs in Sauraion (on.) gm I ' W W k GS k I GS I W gmb k GS g o f SB f m BS BS BS BS f BS r o I - I eff dx ( d d ) - λi I sb db gs f sb0 SB 0 db0 Q gm π T GS gs 0 3 W W K OX ( GS W 3 - ) 3 f GS Derivaion of gs Toal charge sored in he channel Q T gs W 3 Q W T GS 0 [ 3 GS GS W - (y) W - ]dy I D μ GS Q T - - d

22 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan - 郭泰豪, nalog I Design, 07 Example Small Signal Model Derive he complee small-signal model for an NMOS ransisor wih I =00μ, SB =0.5, =0.6. Device parameers are f = 0.65, W=.5 μm, =45 nm, γ= 0.45 /, μ n = 80μ/, λ =. -, =. nm, Ψ 0 = 0.69, sb0 = db0 =.5 ff. Overlap capaciance from gae o source and gae o drain is.5 ff. ssume gb =5fF. g m = μ n W I D = =.76m g mb n W I f D SB r o I D.. k

23 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -3 郭泰豪, nalog I Design, 07 Example Small Signal Model (on.) Wih SB =0.5,we find The volage from drain o body is.5 sb sb / / SB DB SB ff ff Hence,.5 db db / / DB.. ff.85ff The ide capaciance per uni area is.. F r SiO cm 8.7 ff 9. m The inrinsic porion of he gae source capaciance is gs fF.5fF m

24 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -4 郭泰豪, nalog I Design, 07 Example Small Signal Model (on.) The addiion of overlap capaciance gives gs =.4 ff Gae-drain capaciance is overlap capaciance gd =.5 ff The complee small-signal equivalen circui is shown below G v gs + - ff ff. 76 v gs 44 v bs.k D S v bs - + ff 5fF.85fF The f T of he device can be calculaed wih gb = 5fF giving f T gs g m gd gb B Hz 3.GHz

25 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -5 郭泰豪, nalog I Design, 07 Subhreshold onducion in MOSFETs I GS W n n k exp x - exp where k depends on process I x n.5 ( ) parameers = 5 W = 0 μ m = 0μm GS ( )

26 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -6 郭泰豪, nalog I Design, 07 Subhreshold onducion in MOSFET (con.) Ploed on linear scales as characerisic. I versus GS,showing he square-law I ( / ) = 5 W = 0 μm = 0μm GS ( ) Exrapolaed = 0.7

27 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -7 郭泰豪, nalog I Design, 07 Subhreshold onducion in MOSFET (con.) Ploed on log-linear scales showing he exponenial characerisic in he subhreshold region. I ( ) Square-law region = 5 W = 0 μ m = 0μm 0-0 Subhreshold exponenial region GS ( )

28 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -8 郭泰豪, nalog I Design, 07 Mobiliy Degradaion arge laeral elecric fields accelerae carriers up o a maximum velociy arger verical elecric fields effecive channel deph collisions These effecs can be modeled by an effecive carrier mobiliy I n,eff D where θ [ ( n and W n eff ) ] m / m eff ( [ ( eff m are device parameers ) ] m / m ) I D n W eff, This effec can also expressed as α-law model from curve-fiing Source Gae Drain I D () Wihou mobiliy degradaion Wih mobiliy degradaion n + aeral Elecric Field p-subsrae n + ()

29 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -9 郭泰豪, nalog I Design, 07 Subsrae urren Flow in MOSFETs I DB k ( - sa )I exp - ( k - sa ) k k where and are process-dependen parameers and sa is he value of where he drain characerisics ener he sauraion region g db I DB DB k - I DB sa

30 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -30 郭泰豪, nalog I Design, 07 Example (/) alculae rdb /g db for and 4, and compare wih he device. r o ssume I = 00μ, λ = , (sa) = 0.3, K = 5 -, and K = 30. For =, we have I g DB db exp and hus r db g db G

31 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -3 郭泰豪, nalog I Design, 07 Example (/) This resul is negligibly large compared wih ro. k λid.4 However, for IDB exp The subsrae leakage curren is now abou 0.5% of he drain curren. We find gdb and hus r db g db Ω 833 This parasiic resisor is now comparable o and can have a dominan effec on high-oupu-impedance MOS curren mirrors. kω r o

32 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -3 郭泰豪, nalog I Design, 07 Summary of MOSFET Parameers arge-signal Operaion Quaniy Drain curren (sauraion region) I μ Formula W ( - ds gs ) Drain curren (riode region) I ds μ W [( gs - ) ds - ds ] Threshold volage 0 γ[ φ f - sb - φ f ] Threshold volage parameer γ qn Oxide capaciance ε 3.45 ff m for 00 ο

33 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -33 郭泰豪, nalog I Design, 07 Summary of MOSFET Parameers arge-signal Operaion Quaniy Formula Top-gae ransconducance g m μ W ( GS - ) I W Transconducance-o-curren raio g I m GS - Body-effec ransconducance g mb φ f γ SB g m χg m hannel-lengh modulaion parameer λ eff dx d d Oupu resisance r o λi I eff dx d d

34 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -34 郭泰豪, nalog I Design, 07 Summary of MOSFET Parameers Quaniy Formula Effecive channel lengh eff drwn - d - X d Maximum gain g m r o λ GS - - GS Source-body depleion capaciance sb sb0 ψ SB Drain-body depleion capaciance db db0 ψ DB Gae-source capaciance Transiion frequency f 3 gs W T π gs gm gd gb

35 SPIE MOSFET Model Parameers of Typical NMOS Process (MOSIS) Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -35 郭泰豪, nalog I Design, 07 Parameer (evel model) Enhancemen Depleion Unis TO KP μ/ GMM PHI MBD 3.E-.00E-6 GSO.60E-4.60E-4 widh GDO.60E-4.60E-4 widh GBO.70E-4.70E-4 widh RSH J.E-4.E-4 MJ JSW 5.0E-4 5.0E-4 pf/μ perimeer MJSW TOX ff/ ff/ ff/ Ω/ pf/μ

36 SPIE MOSFET Model Parameers of Typical NMOS Process (MOSIS) (on.) (evel model) Enhancemen Depleion Unis /cm NSUB.09E5.0E6 NSS 0 0 /cm NFS.90E 4.3E /cm TPG XJ D UO URIT.0E E6 cm UEXP.00E-3.00E-3 MX.0E5 6.75E5 m/s NEFF.00E-.00E- DET.6.80 The SPIE parameers: Empirical parameers Fiing measured device characerisics o he mahemaical equaions Using a numerical opimizaion algorihm This approach gives good fi o he model bu causes a deviaion from he ypical parameers. Parameer relaionships may no be self-consisen wih some of he fundamenal relaionships. *Please refer o he chapers abou SPIE model in he HSPIE documen suggesed in assignmen Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan -36 郭泰豪, nalog I Design, 07 3 /(v s) /cm

37 ppendix Resisance Esimaion apaciance Esimaion Inducance Esimaion PP- -37 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

38 Shee Resisance R=ρ/=ρ/W= R /W R =ρ/ Resisance Esimaion : resisivi y W : hicknes s :conducor lengh W : conducor R widh :shee resisance ohm/square, / urren PP- -38 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

39 Resisance Esimaion (con.) Typical shee resisance for conducors Maerial Min. Typical Max. Inermaal (meal-meal) Top-meal(meal3) Polysilicon Silicide 3 6 Diffusion(n +, p + ) Silicided diffusion 4 0 N-well K K 5K PP-3-39 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

40 Resisance Esimaion of Nonrecangular Shapes Direc esimaion W urren urren R = /W W Table-assised esimaion W RTIO = W 4 R = + 4W W W W D W W W W W W RTIO = W B W W W RTIO = W W W R = + W W R = /W W W RTIO = W W W W E W W RTIO = W W Shape Raio Resisance 5 5 B 5 5 B.5 B.55 B D. D.5.3 D.3 D 3.6 E.5.45 E.8 E 3.3 E 4.65 PP-4-40 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

41 onac and ia Resisance Proporional o he area of he conac e.g. feaure size =>Rconac 0.5Ω ~ a few ens of Ωs Muliple conacs o obain low-resisance inerlayer connecions PP-5-4 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

42 MOS-apacior haracerisics - plo accumulaion depleion inversion.0 low frequency high frequency min Three regions in he plo (i)ccumulaion region (ii)depleion region (iii)inversion region 0 gs ccumulaion region ε ε o :gae area o o SiO : permiivi y of free space : gae capacianc e ε SiO : dielecric ε SiO ε o ε o consan of SiO ( 3.9) :gae capacianc e per uni area PP Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07 o gae gae g < p-subsrae +

43 Depleion region εsiεo dep d d : depleion layer deph ε Si gb : dielecric o Where o o dep beween gae and surface Inversion region gb min dep For MOS-apacior haracerisics (con.) consan of Si( ) dep :gae capacianc e per uni is low frequency o o o capacianc e area :saic (i.e. low frequency, 00Hz) dep dep O 00 ~ 00, min min :dynamic o varies (i.e. high depends on he deph of he depleoin region, i.e. depends on subsrae doping for subsrae doping densiy va ries from 0 / densiy. frequency) from 0.0 ~ PP-7-43 o dep Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07 cm -3 o 50-5 o dep cm -3 gae gae + gae depleion layer p-subsrae gae p-subsrae h > g > 0 g > h channel depleion layer d d

44 MOS Device apaciance ross secion of MOS device GTE gs gb gd SOURE HNNE DRIN DEPETION YER sb db Equivalen circui SUBSTRTE d gd db g GTE DRIN SOURE SUBSTRT be gs s sb gb PP-8-44 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

45 MOS Device apaciance (con.) pprimaion of gae capaciance Self-aligned process is assumed (i.e. overlap caps. are negligible) Parameer off Non-sauraed Sauraed gb gs gd g = gb + gs + gd (finie for shor channel devices) 0.9 (shor channel) PP-9-45 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

46 gs,gd and Example : W=49. m, =4.5 m (long channel) gs and gd *large g & small gd (in sauraion region) g gd large 0 ( gd is due o channel side fringing fields beween gae and drain.) gs, gd W gs gs ds (vols) gs gd PP-0-46 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

47 gs,gd and (con.) Example : =0.75 m (shor channel) gs and gd small *small g & small gd (in sauraion region) gd gs gs 0. ( gd is due o channel side fringing fields beween gae and drain.) g gs, gd W gs ds (vols) gd PP- -47 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

48 = ε SiO e.g., gae capaciance per uni area ε Uni ransisor I is he same widh as a meal-diffusion conac o ; where o ε SiO and ε 0-3 o pf/μf 4 ff/μf W 4 Minimum-size ransisor 5 W 4 PP Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

49 Diffusion apaciance rea and periphery d=ja*(ab)+jp*(a+b) ja: juncion capaciance per μm jp: periphery capaciance per μm a: widh of diffusion region b: lengh of diffusion region Typical value (μm n-well process) ja: *0-4 pf/μm (n+ diffusion) 5*0-4 pf/μm (p+ diffusion) jp: 4*0-4 pf/μm (n+ diffusion) 4*0-4 pf/μm (p+ diffusion) olage dependen j j j0 j b m j b jp j0 a m ja Diffusion rea b is juncion abrup poly volage isbuil -in juncion is zero bias capaciance graded juncion juncion poenial ~ ~ 0.6 PP-3-49 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

50 SPIE example. SPIE Modeling of MOS apaciances M NFET W 4U U S 5P D 5P PS.5U PD.5U...MODE NFET NMOS TOX 00E - 8 GBO 00P GSO 600P GDO 600P J 00U JSW 400P MJ 0.5 MJSW 0.3 PB o node4 - drain TOX 00 node3 - gae node5 - source node0 - subsrae channel widh 4m channel lengh m source area S 5m drain area D 5m - beyond he channel. 000 F/M gbo gso occours due o he polysilicon exesion and represen he gae - o - source/drain source periphery PS.5m capaciance due o overlap in he physical drain periphery PD.5m - srucure of he ransisor F/M gdo PP-4-50 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

51 SPIE Modeling of MOS apaciances (con.) apaciance gae capaciance g(inrinsic) g(exrinsic) g(oal) W j rea j where W gs0 W gd0 gb PF g(inrinsic) OX g(exrinsic) source and drain capaciance rea j S or D, he PF J J PB J he juncion poenial PB he buil -in volage PF J MJ 4 0.0PF MJSW he grading coefficien of he PF 0.04PF 0 4 periphery JSW he zero -bias capaciance per juncion MJ he grading coefficien of he juncion boom ~ vols juncion area of he souce or drain.5 is assumed.5 is assumed area PF JSW he zero -bias capaciance per juncion periphery sidewall Periphery PS or PD, he periphery of he source or drain j(drain) j(source) PP-5-5 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07 J PB MJSW

52 Single wire capaciance Rouing apaciance Parallel-plae effec and fringing effec Fringing field W T Insulaor(Oxide) H Subsrae ccurae capaciance evaluaion : use compuer Hand calculaion : use simple model (less han 0% error) Half cylinders w Parallel plae h ε w h w h 0.5 PP Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07 h 0.5

53 Rouing apaciance (con.) Muliple conducor capaciances Three-layer example c 3 c c layer3 layer layer apaciance calculaion is very complex refer o exbook Typical dielecric and conducor hicknesses Thin ide o 00 Meal o 6000 Field ide o 6000 M M ide o 6000 Polysilicon o 3000 Meal o 000 M poly ide o 6000 Passivaion o 0000 PP-7-53 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

54 Disribued R Effecs Transmission line l Subsrae conducor layer isolaion layer Delay ime from one end o he oher end rc l r : resisance c : capacianc e per uni l :lengh of per uni he wire lengh lengh PP-8-54 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

55 Disribued R Effecs (con.) Disadvanages of long wire: ong delay Reducion in sensiiviy o noise PP-9-55 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

56 Disribued R Effecs (con.) Mehod o improve disadvanages menioned previously g delay rcl If g, more buffers In acual design, if possible, rcl rc τ g l g l rc rcl g 4 rcl If g, delay ime 4 rc g is l reduced should be used PP-0-56 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

57 Disribued R Effecs (con.) Transmission line effec is paricularly severe in poly wire because of he relaively high resisance of his layer. Gae poly layer is he wors one because of is high capaciance o subsrae. Sraegies Use meal line : small r Use wider meal for signal disribuion line (e.g. clock disribuion line) : small r, a iny bi large PP- -57 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

58 Inducance On-chip inducance are normally small. Bond-wire inducance is larger. Inducance of bonding wires and he pins on packages : he magneic permeabiliy of h : he heigh d: he 4h ln H/cm d (ypically.57 0 diameer above of he he H/cm) ground wire Inducance of on-chip wires ln 8h w w : conducor h : he heigh w 4h widh above he -8 H/cm subsrae he plane wire PP- -58 Prof. Tai-Haur Kuo, EE, NKU, Tainan iy, Taiwan 郭泰豪, nalog I Design, 07

Chapter 6 MOSFET in the On-state

Chapter 6 MOSFET in the On-state Chaper 6 MOSFET in he On-sae The MOSFET (MOS Field-Effec Transisor) is he building block of Gb memory chips, GHz microprocessors, analog, and RF circuis. Mach he following MOSFET characerisics wih heir