Technology Scaling. 9nm. Advanced Digital IC-Design. Content. What happens when technology is scaled? Progress: Described by Gordon Moore

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1 Advanced Digial IC-Design Conen 0.μm Wha happens when echnology is scaled? Technology caling 9nm ource Gae Drain ource Gae Drain ubsrae ubsrae IC Design pace Progress: Described by Gordon Moore peed Tradiional design space Area New echnologies give a new design space Complexiy Flexibiliy New Design pace Power Moore s law, formulaed 965 The complexiy for minimum componen coss has increased a a rae of roughly a facor of wo per year no reason o believe i will no remain nearly consan for a leas 0 years ource: Elecronics, Volume 38, Number 8, 9 April 965

2 Moore s aw: Processors Example: 30 nm Transisor Reformulaed by Moore 975 The # of ransisors will be doubled every 8 h monh ource Gae Drain n + n + ource: Inel p - subsra Inel 0 nm Transisor ITR Inernaional Technology Roadmap for emiconducors Esimae of fuure echnologies in a 5 year perspecive New esimae every second year hp://public.irs.ne/

3 ITR ysem Drivers Where are we in abou 0 years? MPU (Micro Processor Uni) oc (ysem-on-chip) - Muli echnology (digial, analog, and mixed) - High Performance (high speed) -ow Power AM/ (Analog & Mixed ignal) DRAM (Dynamic RAM) Virus 00 Proein Molecule DNA Molecule 0 [nm] Technology Oxide hickness Meal Oxid Halvledare (semiconducor) 9nm Channel lengh decrease by 7 Oxide hickness decrease by 5 Thickness of a few aoms Technology predicions from four scenarios Aom nm ource: ITR 00 Updae (High performance logic echnology) Gae Oxide in an 50 nm echnology Polysilicon Gae Gae Oxide ilicon crysal Abou 0 molecular layers of io Manufacuring: A lihographic process Phoographic glass plae (mask) Each layer is projeced o he silicon die Dimensions close o ligh wavelenghs Ou of reach for he Opics!!! 3

4 Manufacuring: A lihographic process ine widhs smaller han he wavelengh of ligh Opical Primiy Correcion (OPC) Predisorion of he mask layou is needed when scaling down he echnology No OPC OPC Correcions Wih OPC Original ayou Needed for 0. micron and less Manufacuring: A lihographic process Power Consumpion Paining a cm line wih a 3 cm brush Two major ypes Dynamic power consumpion -Two ypes aic power consumpion aic power consumpion - Tradiionally wo major ypes - Four in submicron echnologies Couresy : IBM 4

5 Wha Happens wih he Power Consumpion? Curren pikes (hor Circui) V Charge Previous focus: Dynamic charging/discharging g g g of he load Curren peak when boh N- and PMO are open Power consumpion: P = C V f V -V T Discharge 80-90% from he load and 0-0% from oher sources N open P open V T I peak Dynamic Power Consumpion Why do he aic Power Increase? 90% capaciive swiching and [V] 5 0% shor circui i power ower hreshold volage V T o increase he gae overdrive Tha is, o keep a reasonable propagaion delay hor circui power will decrease in submicron echnologies when V ges closer o V T (Close o Zero when V =V T ) 4 3 Disance beween V and V T will decrease V V T Technology [μm] Vola age (V) ource: ITR 0.93V Gae Overdrive (V V T ) 0.75V V V T 0 5

6 caling & aic Power Consumpion Dynamic vs. aic Power V -V T rade-off New Technologies require reduced V Require lower V T - (or slow devices) High eakage ource: K. Roy V V T I off [V] [V] [um] [pa] Norma alized power aic power is a large conribuor o he power oday Esimaed o be abou equal in oday s echnologies Dynamic power 65 nm aic power Year ource: ITR Mainly subhreshold curren in 65 nm Mos Imporan eakage Currens aic Power in an NMO Device Reverse-biased, drain and source o subsrae juncion band-o-band-unneling (BTBT) Gae ide unneling ubhreshold curren ubhreshold dominaes he power oday Gae leakage will be he major source ua eakage Gae eakage Gae ide unneling na ubhreshold 6 orders of magniude! ub Threshold pa Juncion BTBT Juncion BTBT Juncion BTBT 90 nm 50 nm 5 nm ource K. Roy, IEEE Micro, March April 006 ource K. Roy, IEEE Micro, March April 006 6

7 aic Power in an NMO Device eakage Currens Gae ide unneling eakage increase wih emperaure ubhreshold dominaes a high emperaures 5 na eakage (A/um ) 0 na 5 na Gae eakage Toal Temperaure ubhreshold Juncion BTBT ource K. Roy, IEEE Micro, March April Noe: inear scale ub Threshold Juncion BTBT Juncion BTBT Major source in fuure echnologies (5 nm) Gae ide unneling Major source in fuure echnologies (50 nm and below) ubhreshold curren Major source oday (90 and 65 nm) and below a high operaing emperaures ource K. Roy, IEEE Micro, March April 006 Juncion BTBT Why do he aic Power Increase? Why do he aic Power Increase? hrinking feaure sizes, ource Gae Drain Exponenial increase of he saic power! hrinking hin ide Thin ide ower volage o avoid break-hrough ow V T 0m ln(i D) Increased propagaion delay p : p CV = kv ( - V) T High I off High V T ow I off 00u u 0n 00p p V T I = I e off V G (V) VG VT m vt 7

8 Gae Oxide Tunneling Normalized Gae Oxide Tunneling Gae o bulk curren 90 nm echnology Experimenal echnology High elecrical field over he hin ide ( ) will cause unneling hrough he gae Will be a major obsacle in submicron echnologies Gae ide unneling ub Threshold Juncion BTBT Juncion BTBT C = I gae-leak = C =.6 I gae-leak < 0.0 Oher aic Power Consumpion aic Power and caling Gae-Induced Drain eakage (GID) No very serious for he supply volages suggesed by ITR Drain-Induced Barrier owering (DIB) Resul in an increase of he subhreshold curren Gae Juncion BTBT will increase ubhreshold curren will increase Gae ide unneling will increase DIB and GIB give minor conribuions Gae ide unneling ource DIB GID Drain ub Threshold Juncion BTBT Juncion BTBT 8

9 Threshold Variaions Device Variabiliy a big Problem Threshold volage variaions in 90 nm eakage change exponenially wih he hreshold The problem increases wih denser echnologies Hospos caling & of Errors Rae (ER) Advanced ools o reduce he hospo emperaure Before Afer Cosmic Rays a ground level is abou 5 imes lower han in ouer space Noise margin decreases wih lower V Mainly a memory problem (boh RAM and DRAM) Normalized of Error Rae Exponenial growh wih decreasing V Cosmic ray = high-energy paricle from ouer space 9

10 ome Quoaions Full (ideal) Transisor caling Cosmic rays are almos impossible o sop. They'll go hrough 5 fee of concree wihou any rouble and cause a bi o flip (ange IBM) Original device V D caled device (New Technology) / V D / In 0.3-micron echnology we're seeing some memory echnology wih error raes of 0,000 or 00,000 FITs per megabi. This brings he frequency of error in a single device down o weeks or monhs (Eric-Jones Moys) ource Gae Drain I D ource Gae / Drain I D / A sysem wih GBye of RAM can expec an error every wo weeks; a hypoheical erabye sysem would experience a sof error every few minues (Tezzaron emiconducor) Channel lengh () Channel widh (W) Thin ide hickness ( ) Drain curren (I D ) Volage (V D, V T, V, ec.) Doping (N A ) Channel lengh (/) Channel widh (W/) Thin ide hickness ( /) Drain curren (I D /) Volage (V D /, V T /, V /, ec.) Doping (N A ) FIT/Mbi = Failures In Time: Errors per billion hours of use Increased accepor concenraion for consan elecrical field caling Facors: Area & Capaciance caling Facor: Delay Area ε W Capaciance W C = W V Area W caling facor = C Capaciance W W ε C = caling facor = / Q = C Δ V = C ( V V ) = CV OH O Q = I = k ( V V ) = k ( V V ) n G T ph n T ph W ε = Maerial consan ph CV = k ( V V ) n T 0

11 caling Facor: Delay ( p ) caling Facor: Power Consumpion W = μ = Gain facor k C μ = Elecron mobiliy CV p P = C V f ε = Maerial consan = Delay p p CV C W V V kv ( V) ( V V) W T μc ( ) T V V μ T C W C W ε = = W caled delay p V μ( V VT ) calning facor = W P = C V f ε W V p Delay (facor /) ource: J. Rabaey, Digial Inegraed Circuis ource: J. Rabaey, Digial Inegraed Circuis caling Facor: Power Consumpion caling Facor: Power Consumpion P = CV f ε W V p Power consumpion caling facor = caled power W ε V p caling facor = Area caling facor = Power consumpion caling facor = Area uni

12 Ideal caling: imiaion Velociy auraion Volage scale less han oher parameers eads o higher h E-field in he channel eads o sauraion of he elecron velociy e - e - e- e - e - High E-field Elecron velociy canno have an unlimied increase k W I = n ( V V ) D G T Non-sauraed k n W ID = ( VG VT) α Velociy α < auraed The drain curren is reduced due o he velociy sauraion Velociy auraion (0.5um echnology) Velociy auraion α k n W I ( ) D = VG V α T ow V : Velociy auraion can be negleced High V : α decreases auraion appear earlier in denser echnologies I D V G =5V V G =4V V G =3V V G =V V G =V inear Dependence I d hor ong Device Device I d V G (auraed Region) V G V D [V] V D [V] ource: M. R. an, IEEE Trans. on VI ysems, Apr 0.

13 Delay Power V Non-sauraed gae delay ( V VT ) caling facor = V V Fixed volage gae delay caling facor = ( V V ) auraed gae delay T T ( V V ) α caling facor < (or ) W ε V Non-sauraed power consumpion caling facor = ph Fixed- volage power consumpion W ε V ph caling facor = W ε V auraed power consumpion ph caling facor < (or ) The curren do no increase as expeced a high volages The curren do no increase as expeced a high volages Transisor caling Dynamic Power Consumpion Parameer Full caling Fixed auraed Volage caling Dimensions (W,, and ) / / / V and V T0 / Volage do no scale: leads o increased power consumpion P = CV f Parly limied by velociy sauraion Delay / / / Capaciance / / / I D / Power consumpion / Power per area uni 3 We will compare o ITR laer Dependen on echnology ype Technologies for high performance: Increased consumpion Technologies for low power: ow volage, less increase in power consumpion 3

14 Power in new echnologies? Meal ayers Year Techology (nm) Meal ayers Dynamic power have been dominaing aic power will increase drasicaly How abou inerconnecions? Meal ayers - No a D problem!!! Transisors Tungsen Conacs Delay vs Technology Delay [ps] Gae Delay Inerconnec Delay Technology [um] ource: IA Roadmap 4

15 Capaciive load will increase Inerconnecions on a ilicon Die Conacs Connecion Probabiliy 0.08 Fringing Capaciors Plae capaciors was dominaing Fringing capaciors will dominae in new echnologies Wire engh/chip Diagonal engh.0 ocal Wires Global Wires Global Wires do no scale wih he echnology Comparison of Nework-on-Chip and Busses Copper Wires 40 % reducion in resisance % performance improvemen in a Power PC Transisor 5

16 Delay vs. Technology Trends for Maximum Power Inerconnec dominaes he load - Fringing capaciances added - 3 dimensions - onger global wires oluions? - Copper wires - Maerials wih low dielecric consan - Inerconnec opimizaion mehodology Physical design mus be considered in all design phases Toal power per funcion P [W] Today, Idag, 50W ource: ITR 00 Updae 06, 90W 58W 3W High performance: Doubling over 5 years ow power: Doubling over 5 years andby: Consan over 5 years Wha abou Moore s aw? Moore s lag: Toal power? The number of ransisors is doubled every 8h monh (965) Gordon Moore P (kw) W oday 5 kw he year 00 5 kw per chip!!! Year År 6

17 Manufacuring Coss Manufacuring Coss - Masks Iniial cos have he larges increase maller sizes leads o an explosion of he coss for a mask-se Mask se cos [M$] M$ Feaure size ource: eaic ource: eaic Cos ($000) nm ource: Jan Rabaey Year 65 nm 90 nm 30 nm 80 nm 50 nm 008 More Expensive in he beginning Exponenial cos increase Manufacuring coss in new Technologies Cos per Funcion (CPF) More Expensive for lower volumes bu cheaper when he volumes goes up CPF reducion beween 9-35% per year Technology / Die ($) Cos 30 nm 80 nm Relaive cos per funcion Technology Technology 3 Technology cross-overover Years Volume (Dies) ource: Rakesh Kumar 7

18 Coss New Fab Wha is volume? 3000 Capial Cos (M$).5 Billion $ " Typical "business case" for an AIC (30 nm): Price of "off-he-shelf" IC - 50$ per Chip 000 8" Manufacure cos - 0$ per Chip Developmen coss - 0M$ " 6" Technology 50$ 0$ Break-even even = Chips 0M$ Break-even is higher for 90 nm, 65nm ource: Peer Olanders, Ericsson Memories on Chip Increase from 50% o over 90% of he silicon area 00% 80% 60% 40% 0% 0% source: Japanese sysem-i indusry % Area Memory % Area Reused ogic % Area New ogic 8