UT Austin, ECE Department VLSI Design 5. CMOS Gate Characteristics

Transcription

1 La moule: CMOS Tranior heory Thi moule: DC epone Logic Level an Noie Margin Tranien epone Delay Eimaion Tranior ehavior 1) If he wih of a ranior increae, he curren will ) If he lengh of a ranior increae, he curren will ) If he upply volage of a chip increae, he maimum ranior curren will 4) If he wih of a ranior increae, i gae capaciance will 5) If he lengh of a ranior increae, i gae capaciance will 6) If he upply volage of a chip increae, he gae capaciance of each ranior will D. Z. Pan 1 D. Z. Pan DC epone DC epone: v. for a gae E: Inverer When = -> = When = -> = V In beween, epen on DD ranior ize an curren I V p in y KCL, mu ele uch ha = I p We coul olve equaion u graphical oluion give more inigh D. Z. Pan Tranior Operaion Curren epen on region of ranior behavior For wha an are nmos an pmos in Cuoff?? Sauraion? D. Z. Pan 4 nmos Operaion pmos Operaion Cuoff Saurae Cuoff Saurae V gn < V n V gn > V n V gn > V n V gp > V p V gp < V p V gp < V p < V n > V n V n < V gn V n < -V n > V n V n > V gn V n > -V n > + V p < + V p V p > V gp V p > -V p < + V p V p < V gp V p < -V p V gn = V n = I p V gp = - V p = - V p < I p D. Z. Pan 5 D. Z. Pan 6 1

2 I-V Characeriic Curren v., Make pmos wier han nmos uch ha β n = β p V gn5 5 V gn4 -V gp1 V gp -V p V gn V gn V gn1, I p V gp V n V gp4 -I p V gp5 D. Z. Pan 7 D. Z. Pan 8 For a given : Plo, I p v. mu be where curren are equal in = 5, I p, I p I p D. Z. Pan 9 D. Z. Pan 1 =. =.4 In, I p, I p D. Z. Pan 11 D. Z. Pan 1

3 =.6 =.8, I p, I p D. Z. Pan 1 D. Z. Pan 14 Loa Line Summary = 5 5, I p, I p D. Z. Pan 15 D. Z. Pan 16 DC Tranfer Curve Trancribe poin ono v. plo Operaing egion evii ranior operaing region 5 C D E V n / +V p egion nmos Cuoff Sauraion C Sauraion D E pmos Sauraion Sauraion Cuoff C D E V n / +V p D. Z. Pan 17 D. Z. Pan 18

4 ea aio If β p / β n 1, wiching poin will move from / Calle kewe gae Oher gae: collape ino equivalen inverer β p.1 β = n β p 1 β = n 1.5 D. Z. Pan 19 Noie Margin How much noie can a gae inpu ee before i oe no recognize he inpu? Logical High Oupu ange Logical Low Oupu ange Oupu Characeriic Inpu Characeriic V OH NM H V IH Ineerminae V egion IL NM L V OL GND Logical High Inpu ange Logical Low Inpu ange D. Z. Pan Logic Level To maimize noie margin, elec logic level a uniy gain poin of DC ranfer characeriic V OH Uniy Gain Poin Slope = -1 β p /β n > 1 Tranien epone DC analyi ell u if i conan Tranien analyi ell u () if () change equire olving ifferenial equaion Inpu i uually coniere o be a ep or ramp From o or vice vera V OL V n V IL V V IH DD - V p D. Z. Pan 1 D. Z. Pan Inverer Sep epone E: fin ep repone of inverer riving loa cap Vi n() = u ( ) VDD V Vou ( < ) = V in () DD Vo u ( ) I n () = () C I n loa β ( ) = ( VDD V) > VDD V ( ) β VDD V V ou () < VD D V () () C loa () Delay Definiion pr : riing propagaion elay Ma ime from inpu o riing oupu croing / pf : falling propagaion elay Ma ime from inpu o falling oupu croing / p : average propagaion elay p = ( pr + pf )/ r : rie ime From oupu croing. o.8 f : fall ime From oupu croing.8 o. D. Z. Pan D. Z. Pan 4 4

5 Delay Definiion cr : riing conaminaion elay Minimum ime from inpu o riing oupu croing / cf : falling conaminaion elay Minimum ime from inpu o falling oupu croing / c : average conaminaion elay p = ( cr + cf )/ Simulae Inverer Delay Solving ifferenial equaion by han oo har SPICE imulaor olve equaion numerically Ue more accurae I-V moel oo! u imulaion ake ime o wrie (V).5 pf = 66p pr = 8p.. p 4p 6p 8p 1n () D. Z. Pan 5 D. Z. Pan 6 Delay Eimaion We woul like o be able o eaily eimae elay No a accurae a imulaion u eaier o ak Wha if? The ep repone uually look like a 1 orer C repone wih a ecaying eponenial. Ue C elay moel o eimae elay C = oal capaciance on oupu noe Ue effecive reiance So ha p = C Characerize ranior by fining effecive Depen on average curren a gae wiche D. Z. Pan 7 C Delay Moel Ue equivalen circui for MOS ranior Ieal wich + capaciance an ON reiance Uni nmos ha reiance, capaciance C Uni pmos ha reiance, capaciance C Capaciance proporional o wih eiance inverely proporional o wih g k /k g /k g k g D. Z. Pan 8 Eample: -inpu NND Skech a -inpu NND wih ranior wih choen o achieve effecive rie an fall reiance equal o a uni inverer (). -inpu NND Cap nnoae he -inpu NND gae wih gae an iffuion capaciance. D. Z. Pan 9 D. Z. Pan 5

6 Elmore Delay ON ranior look like reior Pullup or pullown nework moele a C laer Elmore elay of C laer C p i o ource i noe i ( )... (... ) = C + + C C N N Eample: -inpu NND Eimae wor-cae riing an falling elay of -inpu NND riving h ienical 1 N C 1 C C C N D. Z. Pan 1 D. Z. Pan Eample: -inpu NND elay of a -inpu NND riving h ienical Eample: -inpu NND elay of a -inpu NND riving h ienical C C pr = D. Z. Pan D. Z. Pan 4 Eample: -inpu NND elay of a -inpu NND riving h ienical Eample: -inpu NND elay of a -inpu NND riving h ienical C C = ( 6+ 4 ) pr h C D. Z. Pan 5 D. Z. Pan 6 6

7 Eample: -inpu NND elay of a -inpu NND riving h ienical / / C C pf ( )( ) ( 6 4 ) ( ) ( 7 4h) C = C + + h C + = + Delay Componen Delay ha wo par Paraiic elay 6 or 7 C Inepenen of loa Effor elay 4h C Proporional o loa capaciance D. Z. Pan 7 D. Z. Pan 8 Conaminaion Delay e-cae (conaminaion) elay can be ubanially le han propagaion elay. E: If boh inpu fall imulaneouly C cr ( ) = + h C D. Z. Pan 9 Diffuion Capaciance ume conace iffuion on every / Goo layou minimize iffuion area E: NND layou hare one iffuion conac euce oupu capaciance by C Merge unconace iffuion migh help oo Share Conace Diffuion Merge Unconace Diffuion C C C C C Iolae Conace Diffuion 7C C C Noe. Thi picure from ebook aume ha unconace iffuion ha he ame uni capaciance C. cually, i can be le, e.g., C/. D. Z. Pan 4 7