System-On-Chip. Embedding A/D Converters in SoC Applications. Overview. Nyquist Rate Converters. ADC Fundamentals Operations

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1 Overview Embedding A/D Conversion in SoC applicaions Marin Anderson Dep. of Elecrical and Informaion Technology Lund Universiy, Sweden Fundamenal limiaions: Sampling and Quanizaion Pracical limiaions: Sampling noise and clock jier Mixed Signal Noise and Disorion CMOS Scaling Aspecs Nyquis Rae Converers ADC Fundamenals Operaions A/D Converer Coninous ime Conversion from analog o digial signals involves sampling and quanizaion boh producing errors and noise, nonlinear disorions or look-a-likes x () AAF Sampling Analog x LP () wih x[nt ] ani alias filer frequency s f Quanizer wih R bi resoluion x[k] R f s x() Sampling x [k] x q [k] Quanizaion D/A Converer x[k] R f s Digial o analog inerpreer x[nt ] Analog low pass filer x() From coninuous ime o discree ime Bandwidh limiaion Aliasing, aliasing, ALIASING Sampling ime uncerainy Sampling noise From infinie precision o finie precision Quanizaion error or noise? Equivalen noise power Coninous ime 3 4

2 Sampling example Bandwidh limiaion (ime domain) 00 Hz one 1000 Hz sampling Sampled signal 00 Hz one 1000 Hz sampling Sampled signal = 0.001s T s = 0.001s T s SPECTRUM OF ORIGINAL SIGNAL T samp SPECTRUM OF SAMPLED SIGNAL 100 Hz one 1000 Hz sampling T s Sampled signal!!!! The same sampled signal, wih differen original signals! Freq. Freq. = 0.001s T s When he signal i sampled, copies of he original specrum show up a every ineger muliple of he sampling frequency. This effec, where a high frequency signal appear as a low frequency one afer sampling is called ALIASING. T s 5 6 Bandwidh Limiaion (frequency domain) Sampling Quiz To avoid aliasing, he sampling frequency mus be a leas TWICE as high as he highes frequency componen of he original signal. A wha frequency / frequencies will a sinusoidal signal close o f s, ha is sampled wih he sampling rae f s, be afer sampling? 7 8

3 Noise Folding - Aliasing Ani-alias Filering f s / x() f ou f s / f s 3f s / f s 5f s / 3f s f in In almos all cases we need o apply an ani-aliasing filer before our sampling uni o avoid aliasing. Mos signals conain unwaned componens a frequencies above wha our chosen sampling frequency can handle. x[k] f in x () LP filer Sampling wih x LP () wih x[k ] cuoff s f / frequency s f The frequency f s / is called he Nyquis frequency f ou 9 10 Sampled hermal noise kt/c noise kt/c noise calculaion Noise creaed by he sampling swich and he signal source, is filered in he sampling circui. The Wiener-Kinchine heorem saes ha he PSD a he oupu is he PSD a he inpu imes he ransfer funcion squared. In order o make he sampling noise power equal o he quanizaion noise (3 db SNR degradaion) we need o selec C large enough. (V FS = 1 V) For high accuracy ADCs he sampling capacior will ge very large and require large currens for charging and discharging! ( f ) = S ( f ) Sv ns v n 1 1+ j ( π f τ ) Inegraing he PSD a he oupu from zero o infiniy, yields he oal noise power ha will fold ino he band from 0 o f s /. Sv ( f ) S n 1 σ n = Sv ( f ) df = ( πτ an ( πτ f )) = ny ( ) 4 0 πτ s 0 v () 0 n 4kTRs kt σ kt C = = ( ) / 4τ ( R C ) C s = 1 kt C R 1kT 1kT C = = VFS VFS R R = 8b => 3.3 ff R = 10b => 5 ff R = 1b => 834 ff R = 14b => 13 pf R = 16b => 14 pf R = 18b => 3.41 nf C I P R + 1 C 4 I 4 P

4 Sampling-ime jier Any clock signal is affeced by jier (noise on he zero crossings ) Large errors wih seep signal slopes Sampling error caused by jier For a sine wave x Asin ω in ( ) = ( in ) ( ), he jier-induced error x nt is x( nt ) = Aωδ in ( nt ) cos( ωinnt ) δ ( nt ) δ ji ( ) Assume ha is he sampling of a random variable obain: A ωin x ji = A ωin cos ωinnt δ nt = δ nt () ( ) ( ) ( ) The jier-limied SNR is herefore: S SNR = 10log = 0log in N ( ω δ ( nt ) ) ; we REMARK: If he SNR does no change wih signal ampliude SUSPECT CLOCK JITTER! Jier may be he limiing facor in daa conversion: if SNR=90dB and f in =100MHz, hen he clock jier mus be below 50fs Maximum jier vs. inpu frequency and SNR Clock Jier - Random and Sysemaic SNR Second order harmonics likely o appear already for quie modes signal-oclock crossalk! 15 16

5 Clock Jier Summary Ampliude quanizaion - quanizaion error No dependen on sampling rae SNR due o oher disorion is normally dependen on signal ampliude, he jier limied SNR is no. Sysemaic clock skew creaes disorion, random variaions in sampling insan generaes noise. Srong dependence on inpu frequency (be careful when using low IF conversion) Jier performance can ofen be improved by careful design M = N N = # of bis Y = X + ε in in max Q ( 1) n < X < n+ ε FS Q X FS = M X = X X min M = # of quanizaion levels The quanizaion error is a form of daa corrupion fundamenally unavoidable in daa conversion (unless N is infinie) Quanizaion error Ramp inpu Quanizaion error Sinusoidal inpu This is NOT a random signal! This is also no a random signal. Quanizaion errors are funcions of he inpu signal! 19 0

6 Quanizaion noise Quanizaion noise: properies The quanizaion error can be viewed as a form of noise source Frequen code ransiions decorrelae successive samples of he quanizaion error, spreading is specrum and making i resemble whie noise Necessary condiions for his very convenien assumpions are: All quanizaion levels are exercised wih equal probabiliy (rue if inpu signal is large) A large number of quanizaion levels are used (usually rue, excep for Σ converers) The quanizaion seps are uniform (usually rue) The quanizaion error is no correlaed wih he inpu (usually rue) The quanizaion error is confined beween - / and /, and has a whie specrum: 1 if - < εq < p ( εq ) = 0 oherwise The ime average power becomes: ε P p d d Q Q = εq ( εq) εq = εq = 1 1 Quanizaion noise and SNR Equivalen number of bis (ENOB) Wihin a dynamic range of X FS, he power of a maximum-ampliude sine wave is T n 1 X ( ) FS X FS Psin = sin ( ) d T ω = = ( ) and for a riangular wave is n X FS Prian = = 1 1 he maximum SNR becomes: Psin SNRsin = 10 log = ( 6.0 n ) db PQ Prian SNRrian = 10 log = ( 6.0 n) db P Q The effecive SNR is he real measure of he resoluion of a daa converer. Measured in bis, i is called he ENOB: SNReff 1.76 db ENOBsin = 6.0 If, for example, here is a sampling jier δ ji, he effecive SNR becomes SNR eff X 8 1 = 10log = FS 10log N ( ωδ in ji X FS ) ( ωδ in ji ) 3 4

7 Mixed Signal Noise and Disorion (1) Mixed signal Noise and Disorion () Jier Again!! Inpu o reference crossalk DC V DD Reference signal DC 10 % power supply variaion ~ 10 % iming edge variaion Analog inpu DC/LF/IF Inpu o clock crossalk ADC I/O crossalk RF Clock signal Power suuply induced jier Digial oupu DC/LF/IF/RF vin Dou = v R ref REMARK: The qualiy of all inpu signals are of grea imporance for he qualiy of he oupu Use separae power connecions for boh digial and analog clocks Carefully decouple sampling clock circuis! 5 6 Mixed Signal Noise and Disorion (3) - Crossalk MS Noise and Disorion (4) Oupu signal scrambling Clean analog supply for inverers driving swiches o avoid digial power supply noise coupling o sensiive analog nodes By scrambling he digial oupu, he inpu/oupu correlaion can be removed. D 0 D 1 XOR XOR Scrambled daa D XOR Sysemaic oupu signal D 3 XOR PRBS Pseudo random binary sequence wih long repeiion inerval 7 8

8 MS Noise and Disorion (5) Bondwire inducance Number (muliple pads for supplies and DCs) and orienaion of currens Puing VDD and GND on every second pad decreases he effecive inducance by as much as 30 % Floorplanning and pad frame planning MS Noise and Disorion (6) Careful Floorplanning Analog inpu Unsensiive analog Quie digial Digial oupus VDD GND VDD GND I in I ou I in I ou Analog supply and bias Sensiive analog Mixed analog and digial Noisy digial Increased number of bond wires = lower inducance = less ringing! Analog reference 9 30 Clock inpu Quie digial MS Noise and Disorion (7) Differenial signals Miigaing Mixed Signal Noise and Disorion - Summary Differenial signal Vin = Vin,p-Vin,n Common mode Vcm = (Vin,p+Vin,n)/ Differenial signals Muliple bondwires Careful floorplanning Symmeric layou of differenial signals In a well balanced design, disurbances are sensed as common mode variaions and herefore rejeced Decoupling, decoupling, decoupling

9 Speed Accuracy of ADCs CMOS Scaling Aspecs - Opporuniies R 1 level / T clk R Increased f T 0 15 INTEGRATING DELTA SIGMA CONVERTERS 1 word / (OSR T clk ) 1 bi / T clk 0 15 INTEGRATING DELTA SIGMA CONVERTERS Digial calibraion 10 SUCCESSIVE APPROXIMATION ALGORITHMIC 1 word / T clk 10 SUCCESSIVE APPROXIMATION ALGORITHMIC 5 FLASH, TWO-STEP FOLDING, INTERPOLATING PIPELINED TIME INTERLEAVING 5 FLASH, TWO-STEP FOLDING, INTERPOLATING PIPELINED TIME INTERLEAVING 1k 10k 100k 1M 10M 100M 1G f S 1k 10k 100k 1M 10M 100M 1G f S CMOS Scaling Aspecs - Challenges Summary and Conclusions Reduced supply volage -> Reduced signal swings Reduced inrinsic gain -> More complex feedback amplifiers Poor lineariy due o shor-channel effecs Complex swich implemenaions Sampling fundamenally limis he bandwidh of ADCs. Ampliude quanizaion limis he resoluion. The sampling circui accuracy is limied by kt/c hermal noise a low inpu frequencies and by clock jier a high frequencies. The sampling circui is very sensiive o mixed signal noise and disorion. Increased speed of deep submicron CMOS enables faser A/D conveers and digial error correcion mehods ha may improve accuracy and power consumpion where maching is he limi. Low supply volage is bad for analog design and leads o SNR reducion, reduced DC gain and lineariy problems, or increased power consumpion

10 Nex lecure Noise shaping ADCs How o achieve 80 db SNR from a 1 bi quanizer... How o increase he SNR exponenially by increasing he clock rae... 37