Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product

Transcription

1 010 3rd Inernaional Conference on VLSI Design Opimized Sage Raio of Tapered CMOS Inverers for Minimum Power and Mismach Jier Produc R. Dua*, T. K Bhaacharyya*, X. Gao and E. A. M. Klumperink *E & ECE Deparmen, IIT Kharagpur, Kharagpur, India IC Design Group, CTIT Research Insiue, Universiy of Twene, Enschede, The Neherlands, dua.ramen@gmail.com, kb@ece.iikgp.erne.in, x.gao@uwene.nl, e.a.m.klumperink@uwene.nl Absrac In his paper, an opimum sage raio (apering facor) for a apered CMOS inverer chain is derived o minimize he produc of power dissipaion and jier variance due o device mismach. Analysis shows ha his opimum sage raio (.4) is lower han ha of minimum delay (3.6) and minimum power-delay (6.35) produc. This analysis is verified by simulaion resuls using sandard 180nm as well as 90nm CMOS echnology. Knowledge of he opimum sage raio helps o design low power low mismach jier buffers for muli phase clock generaion circuis ha can drive large load capaciances. Index Terms apering facor, sage raio, CMOS inverer, mismach jier, muliphase clock, low power, figure of meri. 1. Inroducion Muliphase clocks are required in several applicaions such as ime inerleaved Analog o Digial Converers (ADCs) [1], polyphase mulipah radio circuis [] and image rejec wireless receivers [3]. In all of hese applicaions, phase error of he muliphase clocks severely degrades he performance by generaing spurious ones in ime inerleaved ADCs [4], reducing he harmonic rejecion in polyphase mulipah radios [5] and limiing he image rejecion and hus increasing bi error rae in he image rejec receivers [3]. The phase error originaes from he mismach among he phase-generaing blocks which are he delay elemen of a Delay Locked Loop (DLL) based muliphase clock generaor and laches or flip-flops in a shif regiser based muliphase clock generaor [6]. Given a good layou design and power supply, he delay variaions in hese blocks are primarily caused by he device mismach among differen blocks. We erm his iming variaion as mismach jier similar o [6]. For one phase clock, mismach jier is fixed afer fabricaion and hus only conribues o clock oupu skew. However, in case of muliple phases (for differenial clock also), he mismach jier causes phase error. The noise (hermal noise, flicker noise ec.) generaed iming error also causes phase error bu is value much lower han error generaed by mismach jier for MOS circuis. This is because he error curren (or volage) due o noise is much less han ha of device mismach [7]. I is also confirmed by simulaions in [6] and [8]. Alhough saic mismach jier can be reduced by digial calibraion echniques bu i adds considerable cos and complexiy which increases wih number of phases. Therefore, opimum circui design by jus componen sizing is ofen preferred. Anoher performance parameer is he power consumpion as we arge for a porable applicaion. The phase generaed form a muliphase clock generaor is ofen needed o drive a large amoun of capaciance. Depending on he fan-ou, i is required o be decided wheher o use exra buffer o drive he load. And if yes how many buffers should be used. In general, for he single ended and large swing clocks CMOS inverers and for low swing differenial clocks, MOS Curren Mode Logic (MCML) buffers are used. Mismach jier analysis along wih power o opimize he MCML buffers has been repored [6][9]. However, mismach jier analysis on CMOS inverer is no done much. To solve he number of buffer problem, radiionally a apered chain of inverer analysis has been adoped o find he opimum sage raio for minimum delay [10-11] and minimum power delay produc [1]. We follow similar procedure only wih a differen opimizaion arge. Mismach analysis on a apered buffer chain has been done by [13], however This projec is sponsored by Naional Semiconducor Corporaion /10 $ IEEE DOI /VLSI.Design Auhorized licensed use limied o: UNIVERSITEIT TWENTE. Downloaded on May 14,010 a 18:33: UTC from IEEE Xplore. Resricions apply.

2 opimum sage raio combining mismach jier and power consumpion is no repored ye. In his paper, we aim o derive he opimum sage raio for minimum power and mismach jier produc by a simple analysis for a chain of inverers driving a given load capaciance. The paper is organized as follows. Secion II inroduces a Figure of Meri (FoM) for power and mismach jier. Secion III and Secion IV esimaes he mismach jier of an inverer and a apered inverer chain respecively. In Secion V he power consumpion of he inverer chain is modeled. Secion VI derives he opimum sage raio from he FoM expression. Simulaion resuls are presened in Secion VII, while Secion VII concludes his paper.. Figure of Meri: Power and mismach jier The clock buffers need o size such ha i gives boh low power as well as low mismach jier. Via admiance level scaling [14], we know ha boh noise and mismach jier can always be reduced a he cos of increasing he power consumpion. In order o ake his radeoff ino accoun, jier variance is normalized o power, similar o [6]. Thus a FoM is defined o combine he mismach jier and power in he following way: FoM =. P p d (1) where P d is he power consumpion and p is he mismach jier variance. In simple word, a beer FoM circui will inroduce less mismach jier for a given power budge and vice-versa. 3. Mismach jier of an inverer The propagaion delay of an inverer wih a LOW o HIGH sep inpu can be esimaed as [15]: phl CV L. = K.( V V ) n Tn () where C L is he oal load capaciance, V is he supply volage, K n is he ransconducance parameer and V Tn is he hreshold volage of an nmos ransisor. The -power law model [16] wih < insead of he square-law model (=) is more appropriae for shor channel devices which experience significan mobiliy reducion due o high elecrical fields. In () i is assumed ha he average nmos curren is equal o he iniial curren during swiching. The acual curren will sar degrading when he inverer oupu goes below (V - V Tn ). This degradaion will no be severe if (V - V Tn ) is no much higher han he oggle poin V /. Since new echnologies use lower V and for simpliciy, we neglec his degradaion. Anoher assumpion used in () is ha he inpu is considered as an ideal sep. This assumpion simplifies he mah and can sill give reasonable accurae resuls as discussed in [15]. In a very similar manner we can find he inverer delay for a HIGH o LOW inpu ransiion as: plh CV L. = K.( V V ) p Tp (3) The nominal inverer delay is he average of () and (3) and represened as: 1 CV L. CV L. = Kn.( V VTn) Kp.( V VTp) (4) When an inverer is un-loaded, C L is equal o is inrinsic capaciance C in (mainly is drain-bulk capaciance). We call he delay of he un-loaded inverer he inrinsic delay p_in. I is independen of he fan-ou and sizing of he gae and is purely deermined by he echnology and layou. I can be represened similar o (4) jus by replacing C L wih C in as: 1 Cin. V Cin. V p_in = (5) Kn.( V VTn) Kp.( V VTp) In an inverer chain, an inverer is loaded by he nex inverer. If C ex is he exrinsic (load) capaciance, i.e. mainly he gae capaciance from he nex inverer sage, such ha C L =C in C ex, (4) can be wrien as: C C V V (6) C = p (7) γ C in ex = Kn.( V VTn) Kp.( V VTp) ex and _in[1 ] where C g is he gae capaciance of he driving inverer, and γ is he raio beween he drain and gae capaciance of any inverer in he chain wih a value beween 0 o 1 and close o 1 for mos sub-micron process [17,pp. 53]. The delay of any inverer can now be relaed o is fan-ou r using C ex =rc g, as: (1 r ) = p _in (8) γ Due o mismach in he parameers such as K n, K p, V Tn, V Tp and C L, here will be uncerainies in he amoun of inverer delay which we call he mismach g 153 Auhorized licensed use limied o: UNIVERSITEIT TWENTE. Downloaded on May 14,010 a 18:33: UTC from IEEE Xplore. Resricions apply.

3 jier. The mismach jier variance of an inverer can be found from (4) via parial derivaives as: C L K n VTn L n ( Tn) C K V V = 4 K p V Tp Kp ( V VTp) (9) where V,,, Tn V Tp C L K are he variances n K p of V Tn, V Tp, K n, K p, and C L variaions respecively. The nominal HIGH o LOW and LOW o HIGH delay are assumed o be equal here by choosing proper nmos and pmos widhs. In a very similar manner mismach jier of a unloaded inverer can be represened by parial derivaive of (5) as: p _in C in K n VTn _in in n ( Tn) p C K V V = 4 K p V Tp Kp ( V VTp) (10) The only difference beween he bracke-ed pars in (9) and (10) is he capaciance variaions. Compared wih variaions in V T and K, capaciance variaions are usually small, as observed in [6]. Wih his assumpion, (9) and (10) can be relaed using (8) as: r = 1 p _in γ 4. Mismach jier of a inverer chain (11) Le us now consider he circui shown in Fig. 1, where C in and C ou are he inpu and oupu capaciance fixed by a specific applicaion. For example C in will be he inpu capaciance of he firs inverer which is defined by he accepable load of he circui driving he firs inverer, and C ou by he load capaciance or he inpu capaciance of he block o be driven. Typically a chain of apered inverers is used when here is a large difference beween C in and C ou. The raio R = C ou / C in is he overall fan-ou for he chain of N inverers wih each inverer having a fan-ou of r. For a given R, our aim is o find he opimum value of r which gives he minimum FoM. Alhough he amoun of delay is equal for all he sages in an inverer chain, he mismach jier variance will differ because of he differen sizes. If we compare he 1 s and he nd sage, he inverer area as well as load capaciance are sized up by a facor of r for he nd sage. According o mismach heory [18][19], he mismach variance of he nd sage will be r imes smaller han ha of he 1 s sage also exploied during admiance level scaling [14]: _1 = (1) _ r Similarly, for N h inverer in he inverer chain, he mismach jier variance can be relaed o he firs sage as: _ N _1 N 1 = (13) The oal mismach jier variance of he inverer chain is he sum of he independen jier variance erms of each sage. Thus, _ =.. (14) oal _1 N From (11), (13) and (14) we ge he oal mismach jier: The firs sage inrinsic mismach jier is independen of r and hus can be considered as a consan here. r r = 1 _ oal p _in_1 N 1 N 1 ( r 1) γ r ( r 1) (15) 5. Power consumpion of he inverer chain as a funcion of fan-ou Figure 1: A chain of N inverers wih fixed inpu and oupu capaciance The main source of power consumpion of an inverer is he dynamic swiching power. Anoher source of power consumpion is he cross-bar circui power consumpion which may be a considerable componen if he oupu capaciance is low compared o he inpu capaciance [0]. In he presen scenario, 154 Auhorized licensed use limied o: UNIVERSITEIT TWENTE. Downloaded on May 14,010 a 18:33: UTC from IEEE Xplore. Resricions apply.

4 he oupu capaciance of each inverer is larger han is inpu capaciance. Therefore, he shor circui power consumpion can be ignored. Recognizing ha he load capaciance of any sage is scaled up by r (for a fan-ou of r) from he previous sage, he load capaciance of any sage can be represened by he inpu capaciance C in. The firs sage power consumpion is f in V C in r because is load is r.c in. The oal dynamic power of he inverer chain can be represened as, P = f V rc r C r C (16) N d in..(. in. in... in) Where, f in is he inpu clock frequency. Wih some manipulaion (16) can be rewrien as: N rr ( 1) Pd = fin. V. Cin ( r 1) 6. Opimum inverer sage raio for minimum FoM (17) The inverer chain mismach jier and power consumpion can be used o ge he FoM of he inverer chain. From (1), (15) and (17) and replacing r N by R we ge, r ( R 1) r =... 1 γ (18) FoM f p0_1 inv Cin R ( r 1) Afer differeniaing (18) wih respec o r and using he condiion for minima we ge an equaion of r. Afer some simplificaion, he equaion can be wrien as, r r γ = 0 If we ignore he negaive soluion of r we ge, r = 1 1 γ (19) Therefore, r= forγ =0 and r=.414 for γ =1 As γ is generally close o 1 [17], he opimum value of he sage raio is close o.4. This is smaller han he opimum sage raio for minimum delay. Table 1 shows he sage raios for minimum delay [11], minimum power delay produc [1] and he minimum FoM which is power and mismach jier produc for differen γ values. Though γ is close o 1, a wider range from 0-3 is chosen as in [1], o show is effec on he opimum sage raio. I is clear ha he opimum sage raio for minimum power and mismach jier produc is significanly less han ha of minimum power-delay produc. Sizing base on he power-mismach jier produc approach akes more power bu i have much beer FoM. From (18) we can say ha compared o he power-delay produc approach, i is less han imes. Tha means i inroduces less mismach jier and hus relaxed he phase errors specificaions for oher blocks. In oher word his approach reduces he mismach jier for a given power budge. TABLE 1: Opimum sage raio for minimum delay, power*delay and power*mismach jier γ Minimum Delay Minimum Power*delay Minimum power * mismach jier (FoM) Simulaion resuls In order o verify he analyical resuls, simulaions have been carried ou in UMC 90nm echnology on a long apered inverer chain for differen sage raios, while keeping he inpu and oupu capaciance fixed. We have chosen overall fan-ou, R=50. The choice is made such a way so ha we ge he required sage raios mainaining ineger number of sages. To ge more resoluion in he sage raio, R can be increased o he square of his value. The sage raio was chosen equal o,.,.5, 3, 4 and 6.3 o realize an overall fan-ou of 50 wih a number of sages equal o 8, 7, 6, 5, 4 and 3 respecively. The firs inverer has Wn=1μm and Wp=.5μm, and C ou is se by an inverer of size Wn=50μm and Wp=65μm and he lengh of all he ransisors are equal o he minimum lengh allowed for ha echnology. The pmos o nmos raio is.5 because ha gives equal rise and fall delay. In Fig. he delay of he inverer chain is ploed as a funcion of he sage raio. Minimum delay is found for a sage raio of 4, which is he closes compared o he value given in [11,17] as 3.6. Mismach jier is evaluaed by Mone Carlo simulaions using 100 ieraions. Hisogram plos were used o find he sigma value of he mismach jier. Fig. 3 shows he resuling mismach jier, power dissipaion and FoM for differen sage raios. The lowes (bes) FoM is found for a sage raio of.5, which is close o he heoreically derived value. To allow for easy relaive comparison o he minimum value, all he values in he plos are normalized o heir corresponding value a.5 sage raio. When sage raio is larger han.5, he power dissipaion decreases bu he mismach jier increases. 155 Auhorized licensed use limied o: UNIVERSITEIT TWENTE. Downloaded on May 14,010 a 18:33: UTC from IEEE Xplore. Resricions apply.

5 To verify ha mismach jier dominaes over noise jier as found in [7], we simulaed he variance of noise jier using specre pnoise analysis. This variance was found o be abou 5-6 imes smaller han due o mismach in 90nm and 0-30 imes smaller in case of 180nm CMOS echnology. This validaes our assumpion ha he mismach jier dominaes he phase error. o 4 which is ofen used as a humb rule [1]. I also gives o.5 imes improvemen compared o he power delay produc approach. Figure 4: FoM versus inverer sage raio in 180nm CMOS Figure : Delay versus inverer sage raio in 90nm CMOS 8. Conclusion We derived an opimum sage raio for a apered inverer chain o minimize he produc of power and mismach jier variance wih a simple inverer delay model. We assumed ha ransisor mismach dominaes jier which is rue for 90nm echnology and above. The heoreical opimum is r = 1 1 γ, where γ is he raio beween he drain and gae capaciance of he inverer. Simulaion resuls show an opimum r.5 for boh 90nm and 180nm CMOS echnology, which fis o expecaions (γ 1). This resul will help in sizing inverers and digial gaes in phase error sensiive applicaions such as muliphase clock buffers. 9. References Figure 3: FoM versus inverer sage raio in 90nm CMOS The same simulaions have been carried ou in 180nm CMOS echnology, where he inverer widhs are he same as in 90nm, only he lengh changed o he minimum value of 180nm. The (normalized) power, mismach jier and FoM for differen sage raios are ploed in Fig. 4. Here again he minimum FoM is obained when sage raio is close o.5 which is similar o he resul for 90nm echnology. The FoM improves abou 30% and 50% for 90nm and 180nm echnology respecively a sage raio of.5 compared [1] W. C. Black and D. A. Hodges, Time-inerleaved converer arrays, IEEE J. Solid-Sae Circuis, vol. 15, no. 6, pp , Dec [] R. Shresha, E. Mensink, E.A.M. Klumperink, G.J.M. Wienk and B. Naua A polyphase mulipah echnique for sofware-defined radio ransmiers, IEEE J. Solid- Sae Circuis, vol. 41, no. 1, Dec [3] B. Razavi, Design consideraions for direc-conversion receivers, IEEE Trans. Circuis Sys. II, Analog Digi. Signal Process., vol. 44, no. 6, pp , Jun [4] David G. Nairn, Time-inerleaved analog-o-digial converers, IEEE Cusom Inergraed Circuis Conference, pp , Auhorized licensed use limied o: UNIVERSITEIT TWENTE. Downloaded on May 14,010 a 18:33: UTC from IEEE Xplore. Resricions apply.

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