Theoretical and Practical Limits of Dynamic Voltage Scaling

Transcription

1 Theoreical and Pracical Limis of Dynamic Volage Scaling Bo Zhai, David Blaauw, Dennis Sylveser, *Kriszian Flauner {bzhai, blaauw, Universiy of Michigan, Ann Arbor, MI * kriszian.flauner@arm.com, ARM Ld., Cambridge, UK Absrac Dynamic volage scaling (DVS) is a popular approach for energy reducion of inegraed circuis. Curren processors ha use DVS ypically have an operaing volage range from full o half of he maximum. However, i is possible o consruc designs ha operae over a much larger volage range: from full o subhreshold volages. This possibiliy raises he quesion of wheher a larger volage range improves he energy efficiency of DVS. Firs, from a heoreical poin of view, we show ha for subhreshold supply volages leakage energy becomes dominan, making jus in ime compleion energy inefficien. We derive an analyical model for he minimum energy opimal volage and sudy is rends wih echnology scaling. Second, we use he proposed model o sudy he workload aciviy of an acual processor and analyze he energy efficiency as a funcion of he lower limi of volage scaling. Based on his sudy, we show ha exending he volage range below / will improve he energy efficiency for mos processor designs, while exending his range o subhreshold operaion is beneficial only for very specific applicaions. Finally, we show ha operaion deep in he subhreshold volage range is never energy-efficien. Caegories and Subjec Descripors B.8. [Performance and Reliabiliy]: Performance analysis General Terms performance, design, reliabiliy Keywords dynamic volage scaling, minimum energy poin Inroducion Due o echnology scaling, microprocessor performance has increased remendously albei a he cos of higher power consumpion. efficien operaion has herefore become a very pressing issue, paricularly in mobile applicaions which are baery operaed. Dynamic volage scaling (DVS) was proposed as aecive approach o reduce energy use and is now uilized in a number of low-power processor designs [][][3]. Mos applicaions do no always require he peak performance from he processor. Hence, in a sysem wih a fixed performance level, cerain asks complee ahead of heir deadline and he processor eners a low-leakage sleep mode [4] for he remainder of he ime. This operaion is illusraed in Figure (a). Freq f normal normal ask ask ask ask (a) (b) Figure. Illusraion of opimal ask scheduling Freq f f Permission o make digial or hard copies of all or par of his work for personal or classroom use is graned wihou fee provided ha copies are no made or disribued for profi or commercial advanage and ha copies bear his noice and he full ciaion on he firs page. To copy oherwise, or republish, o pos on servers or o redisribue o liss, requires prior specific permission and/or a fee. DAC 4, June 7-, 4, San Diego, California, USA Copyrigh 4 ACM /4/6...$5.. In DVS sysems however, he performance level is reduced during periods of low uilizaion such ha he processor finishes each ask jus in ime, sreching each ask o is deadline, as shown in Figure (b). As he processor frequency is reduced, he supply volage can be reduced. As shown by he equaions below, he reducion in frequency[5] combined wih a quadraic reducion from he supply volage resuls in an approximaely cubic reducion of power consumpion. However, wih reduced frequency he ime o complee a ask increases, leading o an overall quadraic reducion in he energy o complee a ask. C s Delay = --- = f I dsa ( V h ).3 Power fv dd DVS is herefore aecive mehod o reduce he energy consumpion of a processor, especially under wide variaions in workload ha are increasingly common in mobile applicaions. Hence, exensive work has been performed on how o deermine volage schedules ha maximize he energy savings obained from DVS [4][8]. In mos curren DVS processor designs, he volage range is limied from full o approximaely half a mos. In Table, he available range of operaing volages and associaed performance levels are shown for four commercial designs. The lower limi of Table. Commercial processor designs and range of volage scaling IBM PowerPC 45LP [3] TransMea Crusoe TM58 [] Inel XScale 8 [] Volage Range.V-.8V.8V-.3V.95V-.55V Frequency Range 53M-333M 3M-G 333M-733M volage scaling is ypically dicaed by volage and noise-sensiive circuis, such as pass-gaes, PLLs, and sense amps and resuls from applying DVS o a processor as is wihou special redesign o accommodae operaion over a wide range of volage levels. However, i is well known ha CMOS circuis can operae over a very large range of volage levels down o less hen wo hundred mv. In such subhreshold operaing regimes, he supply volage lies below he hreshold volage and he circui operaes using leakage currens. Work has been repored on designs ha operae a subhreshold volages [6][7] and i was repored ha he ideal minimum allowable supply volage of a funcional CMOS erer is 36mV [9]. A number of commercial producs have also used subhreshold operaion for exremely low power applicaions []. Wih some addiional desigor, i is possible o significanly exend he operaing volage range of processors. One issue ha needs o be addressed is he deerminaion of a lower limi of he volage range for opimal energy efficiency. The opimal volage limi depends on wo facors: he power/delay rade-offs a low operaing volages and he workload characerisics of he specific processor. In his paper we address boh of hese issues. Firs, we show ha he quadraic relaionship beween energy and deviaes as is scaled down ino he subhreshold region of MOSFETs. In subhreshold operaion he on-curren akes he form of subhreshold curren, which is exponenial wih, causing he delay o increase exponenially wih volage scaling. Since leakage. The.3-power[5] scaling of curren is only valid for high supply volages when carrier velociy sauraes. Subhreshold scaling of he supply volage wih performance for low volage operaion will be exensively discussed in Secion 3.

2 energy is linear wih he circui delay, he fracion of leakage energy increases wih supply volage reducion in he subhreshold regime. Alhough dynamic energy reduces quadraically, a very low volages, where dynamic and leakage energy become comparable, he oal energy can increase wih volage scaling due o he increased circui delay. In his paper, we derive an analyical model for he volage ha minimizes energy and we show ha i lies well above he previously repored[9] minimal operaing volage of 36mV. We verify our model using SPICE and also sudy is rends as a funcion of differen design and process parameers. As one of he resuls, our work shows ha operaion a volages well below hreshold is never energy-efficien. A second issue ha deermines he lower limi of volage scaling is he workload characerisics of he processor. Clearly i is no necessary o exend he volage range below ha which is needed based on he expeced workload of he processor. Moreover, he energy/volage relaionship flaens ou as he operaing volage approaches he heoreical lower limi of volage scaling. Therefore, if he applicaions use low performance levels only infrequenly, he gain in energy savings from exending he operaing volage range is limied. To analyze his rade-off, we sudy a number of workload races obained from a processor running a wide range of applicaions. Using our energy model, we esigae he rade-off beween he energy efficiency of he processor and he lower limi of volage scaling. Our resuls show ha mos applicaions benefi significanly from an operaing volage range ha is greaer han wha is available in mos curren DVS processors, bu rue subhreshold operaion is no required. On he oher hand, applicaions ha spend exensive ime in near idle mode will benefi significanly from a volage scaling abiliy from full o subhreshold volages. The remainder of his paper is organized as follows. Secion provides an overview of he volage limi for funcionally correc CMOS logic. Secion 3 presens our analysis of he minimum volage scaling limi for opimal energy efficiency and discusses exensions of our model o larger circuis. Secion 4 presen our analysis of workload daa and he pracical rade-off beween he minimum scaling volage and energy efficiency. Finally, Secion 5 conains our conclusions. Circui Behavior a Ulra Low Volages Before we derive he energy opimal operaing volage in Secion 3, in his secion we firs briefly review he minimum operaing volage ha is required for funcional correcness of CMOS logic. The minimum operaing volage was firs derived by Swanson and Meindl in [9] and is given as follows:, limi kt C fs q C d = ln C ox + C d C ox (EQ ) C d V T ln C ox where C fs is he fas surface sae capaciance per uni area, C ox is he gae-oxide capaciance per uni area, and C d is he channel depleion region capaciance per uni area. For bulk CMOS echnology, we know ha subhreshold swing can be expressed as follows: C d S s = ln V T (EQ ) C ox From his, we can rewrie EQ as follows: S s, limi = V T ln ln V T (EQ 3) S s 5mV ln mV a 3K For.8um echnology S s is ypically in he range of 9mV/decade, and herefore, limi = 48mV. (EQ 4) Hence, i is heoreically possible o operae circuis deep ino he subhreshold regime given ha ypical hreshold volages are much larger han 48mV. In fac, SPICE simulaion confirms ha i is possible o consruc an erer chain ha works properly a 48mV, alhough a his poin he inernal signal swing is reduced o less han 3mV. In Figure, we also show ha i is possible o operae a wide range of sandard library gaes a similar operaing volages and ha heir delay racks relaively well o ha of he erer. I is, however, clear ha here are pracical reasons why operaing circuis a he minimum volage is no desirable, such as suscepibiliy o noise and process variaions[5]. More imporanly, we show in he nex secion ha from an energy efficiency poin of view, he minimum operaing volage for funcionally correc operaion does no provide he bes resuls. 3 Minimum Analysis We firs illusrae he energy dependence on supply volage using a simple erer chain consising of 5 erers. A single ransiion is used as a simulus and energy is measured over he ime period necessary o propagae he ransiion hrough he chain. The energy- relaion is ploed in Figure 3. I is seen ha he dynamic energy componen E acive reduces quadraically while he leakage energy, E leak, increases wih volage scaling. The reason for he increase in leakage energy in he subhreshold operaing regime is ha as he volage is scaled below he hreshold volage, he on-curren (and hence he circui delay) increases exponenially wih volage scaling while he offcurren is reduced less srongly. Hence, he leakage energy E leak will rise and supersede he dynamic energy E acive a 8mV. This effec creaes a minimum energy poin in he erer circui ha lies a mv, as shown in Figure 3. In he previous example, if he erer chain is pipelined logic beween wo regisers, we are implicily assuming ha here is always one inpu ransiion per clock cycle. Bu he swiching aciviy varies in differen circuis, so we include he inpu aciviy facor α, which is he average number of imes he node makes a power consuming ransiion in one clock period. We now derive an analyical expression for he energy of an erer chain as a funcion of he supply volage. Suppose we have an n-sage erer chain wih aciviy facor of α. The sandard expression for subhreshold curren is given by[]: V gs V h V off V ds W mv T V T (EQ 5) I sub = µ eff C ox ( m )V L T e e eff where, S s 9 m = = (EQ 6) ln V = T ln 6.5 In EQ6 we again assume S s is 9mV/decade which is a ypical value. We now express he oal energy E per clock cycle as he sum of dynamic, leakage energy : Delay normalized Delay scalabiliy of differen gaes in a sandard library aoi nand nand3 nor nor3 oai xor xnor Figure. Delay of ypical library gaes over a wide volage range, normalized o erer delay. Noe ha we assume ha shor circui power is negligible and can be ignored. This assumpion is known o hold for well-designed circuis in normal (super-hreshold) operaion [3]. Using SPICE simulaions we have found ha his assumpion holds in subhreshold operaion as well.

3 differen energy componens (log scale) differen energy componens (linear scale).5 x 4 E oal.5 erer sep delay and acual delay analysis 4 E acive E leak 6 8 E oal E acive E leak Figure 3. energy as a funcion of supply volage. E E acive + E leak = α n E swich, + P leak d (EQ 7) = α n -- C s V dd + ( n I leak ) ( n p ) where a - aciviy facor n - number of sages E swich, - swiching energy of a single erer P leak - oal leakage power of he enire erer chain d - delay of he enire erer chain C s - oal swiched capaciance of a single erer I leak - leakage curren of a single erer p - delay of a single erer Firs, we focus on finding an accurae esimae of p. Le p,sep denoe he ideal erer delay wih a sep inpu and p,acual denoe he acual erer delay wih an inpu rising ime of r. We can compue p,sep based on a simple charge-based expression: -- C (EQ 8) s p, sep = I on where I on is he average on-curren of a erer. Furhermore, for normal operaing volages, he sep delay can be exended o he acual delay as follows [8], r phl, acual = phl, sep (EQ 9) I is shown in [3] ha if r > phl,acual (which is saisfied when an erer drives anoher one of he same size, as in our modelling), phl, acual =.84 r (EQ ) Subsiuing EQ ino EQ9 gives, phl, acual =.445 phl, sep (EQ ) Similar resuls hold for plh [3]. We hen can esimae he average p,acual as: p, acual =.445 p, sep (EQ ) = η p, sep However, we need o es if his linear model is valid for subhreshold operaion. To jusify he linear modelling of p,acual wih p,sep a such a wide supply volage range, we plo he calculaed η as a funcion of, based on SPICE simulaion in Figure 4. From Figure 4, i is clear ha he coefficien η increases as he supply volage is reduced o he subhreshold regime. Oher facors affecing he accuracy are ha EQ5 does no perfecly model I sub in subhreshold operaion and ha volage swing degrades a ulra low supply volages. Taking hese facors ino accoun, we se for his echnology aecive η=. for subhreshold operaion.. We find ha over he enire subhreshold region(<<v h ), I sub deviaes from he simple exponenial equaion(eq5) by a mos % if we rea mobiliy µ as consan..5.5 η= p,acual / p,sep Figure 4. The raio η in EQ wih (SPICE) As he supply volage reduces he oal energy consumpion reaches a minimum a some supply volage (referred o as ) since he delay of he circui increases and he circui now leaks over a larger amoun of ime. Subsiuing he equaion for circui delay EQ ino EQ7, we obain he following expression for oal energy: ηc s E = -- α n C s + n I leak n I on (EQ 3) I leak = --nc s α + η n I on Noe ha I on here is subhreshold on curren because we are focusing on subhreshold region where occurs. By subsiuing EQ5 ino EQ3, we now arrive a our final expression for he oal energy as a funcion of supply volage for subhreshold operaion: mv T E = --nc (EQ 4) s α + η n e Based on his simple expression of oal energy, we can find he opimal minimum energy volage by seing E / =. Le u=η n/α and = /mv T, we obain: e = u (EQ 5) -- u We rewrie he above equaion as: e u = (EQ 6) By doing his, we can easily find ha only if u e 3 ( =3) can E have a minimum, which means he lowes is 3mV T. This corresponds o n 4 if η=., α=.. Since EQ5 is a non-linear equaion, i is impossible o solve i analyically. Hence, we use curve-fiing o arrive a he following closed-form expression:.8 x α=.8 α= α=.5 α=. wih differen α (n=) Figure 5. - for an erer chain(n=)

4 5 x 4 simple model SPICE simulaion. x Figure 6. Inverer chain - (analyical model vs. SPICE) =.587 lnu.355 (EQ 7) Subsiuing he original variables gives he following final expression for he energy opimal volage: =.587 ln η n ᾱ mv T n =8 eff =7 =6 =5 n =4 eff =3 n = eff = (EQ 8) Noe ha in he presened model, he only parameers ha are echnology-dependen are η and m. Hence, when we swich from one echnology o anoher, i is only required o deermine hese wo parameers which can be easily accomplished. Ineresingly, he oal energy in EQ4 and he opimal energy volage do no depend on he hreshold volage V h, as verified using SPICE. This independence is caused by he fac ha in subhreshold operaion boh leakage and delay have similar dependencies on V h, and hence he effec of V h on he oal energy cancels ou. Also, we find ha he minimum energy volage is srongly dependen on he number of sages in he erer chain. This is due o he fac ha in a longer erer chain more gaes are leaking relaive o he dynamic energy componen, causing o occur a a higher volage. Finally, we poin ou ha is srongly relaed o he aciviy facor α. In a circui wih a lower α, occurs a a larger volage han in a circui wih higher α, because a lower α gives he circui more ime o leak and effecively increases he sage number, as shown in Figure 5. We herefore inroduce he noaion of effecive sage number as = used in he following analysis. 4 Model Verificaion and Exension o Circui Blocks o be In order o verify he accuracy of he proposed model, we compared he resuls from EQ4 wih SPICE simulaions for erer chains of differen lenghs. In Figure 6, we compare he energy- relaionship prediced by he proposed analyical model in he subhreshold region wih SPICE simulaion resuls for an indusrial.8um process. The plo shows a range of effecive erer chain lenghs ( ). As shown in Figure 6, he analyical model maches SPICE well, excep a volages less han mv. In his region, he n -- α n =8 eff =7 n =6 eff n =5 eff n =4 eff =3 n = eff n = eff Figure 8. NAND chain - (SPICE) model ends o underesimae he rise in energy consumpion due o he dramaic increase of η from Figure 4, resuling in a delay ha is greaer han expeced. However, his is no a severe problem since he imporan region of modeling is around, where he proposed model shows good accuracy. In Figure 7, we compare he prediced minimum energy volage based on our model wih ha measured by SPICE simulaion. In he plo, he resuls using he fied closed-form expression of EQ8 are shown, as well as he numerical soluion of he non-linear equaion in EQ5. As can be seen, boh mach SPICE wih a high degree of accuracy for a wide range of effecive erer chain lenghs. We now consider he energy opimal volage for more complex gaes, such as NAND and NOR, as well as larger circui blocks. Figure 8 shows resuls of SPICE simulaions for a NAND. As can be seen, he minimum volage shifs righ compared wih he erer chain which means ha he energy opimal volage occurs a a higher volage. This is caused by he fac ha for a chain of NAND gaes, he number of leaking pmos ransisors is doubled in every oher gae and nmos ransisors are wice he size. The capaciance increase does no affec he because he delay and he swiching energy are proporional o he loading C s. Now we inroduce n eff, as he equivalen sage number of a erer chain ha gives he same as a NAND chain wih,nand. The n eff, proves a lile smaller han wice,nand due o he sack affec in he nmos ransisors and a slighly larger driving abiliy of he pulldown nmos. We herefore compue n eff, value for he NAND chain: n I eff, leak, nand I on, , nand = I leak, (EQ 9) =.74 Using his n eff,, we obain an accurae mach beween he modeled and SPICE simulaion as shown in Figure 9. Oher complex gaes can be modeled in a similar way by conribuing o each an I on, nand.4..3 of model numerical compuaion of closed form expression of SPICE simulaion of model numerical compuaion of closed form expression of SPICE simulaion Figure 7. Minimal energy wih erer effecive sage number Figure 9. Minimal energy wih NAND effecive sage number

5 x proposed model SPICE simulaion Lasing(%) Performance disribuion for differen applicaions and idle sae emacs fs konqueror nescape plaympeg idle Figure. - for 6X6 muliplier circui appropriae n eff, value. This approach can be exended o larger circui blocks as well. In Figure, we show he oal energy as a funcion of supply volage obained using SPICE for 6 x 6 muliplier when aciviy facor α=.5. We esimae he oal power consumpion for large circui blocks such as his by exending he expression in EQ4 as follows: E oal = E acive + E leak (EQ ) E ac = α S HD C w W oal (EQ ) where S HD is he swiching facor o model he hamming disance of he inpus[], W oal is he oal widh of all he ransisors in he circui, C w is he capaciance of a uni widh ransisor. We compue he oal leakage energy as follows: E leak = I leak, oal d (EQ ) = ( γ leak W oal I leak ) ( n deph p, FO4 ) where γ leak is he leaking facor used o model he leakage sack effec and inpu paern dependency, I leak is he leak curren of a uni widh ransisor, n deph is he logic deph in erms of fanou-of-four (FO4) erer delay p,fo4, which is expressed as follows: -- ( 4W C w ) p, FO4 = (EQ 3) W I on where I on is he on-curren a uni widh erer. Noe ha S swich may change wih supply volage as gliches are sensiive o circui delay alhough for simpliciy we rea S HD as a consan. Subsiuing EQ and EQ ino EQ, we can derive he following expression for oal energy of a circui block as a funcion of supply volage in a manner similar o EQ4: mv T E oal = C w W oal αshd + γ leak n deph e (EQ 4) For he es circui in Figure, he following parameers for he model were found using SPICE simulaion: S HD.55, γ leak.5, n deph 65. The oal energy prediced by EQ4 wih above parameers is shown in Figure for he 6x6 muliplier block ogeher wih SPICE simulaion resuls. I is imporan o noe ha for a generic circui block is defined n deph as, block Therefore when he aciviy facor α and α S HD swiching facor S HD are very low, based on circui srucure or he inpu daa sream, he,block is acually much larger han he real logic deph n deph. In a real processor, he aciviy facor varies across he chip because no all he circui blocks are working inensively a Performance(%) Figure. Performance disribuion of differen applicaions all imes. Therefore, in order o gain energy efficiency, designers mus ake ino accoun he α difference before esimaing he average. In oher words, for he purposes of opimizing DVS, low aciviy and large logic dephs are inerchangeable as hey boh lead more quickly o leakage dominaed designs. 5 Opimaliy for Differen Work Loads. As discussed earlier, he energy opimal volage depends on boh circui and echnology characerisics. A he same ime, he bes choice for he minimum allowed volage for a processor depends on is workload disribuion. If he workload of a processor is such ha low performance levels are never or rarely required, he minimum operaing volage for energy-efficien operaing will be larger han he minimum volage compued in Secion 3. Hence, we sudied a number of differen applicaions running on Linux using an ARM96 and Transmea Crusoe TM56 processors wih dynamic volage scaling and recorded races of he minimum necessary performance levels for each applicaion. The applicaions comprise boh mulimedia and ineracive applicaions: emacs is a race of user aciviy using he edior performing ligh ex ediing asks konqueror and nescape are races of web browsing sessions using he wo browsers fs conains a record of filesysem-inensive operaions mpeg is a race using MPEG video playback idle races he aciviy when he sysem has no dominan workloads and as a resul conains very lile aciviy and mosly operaing sysem housekeeping asks. The dynamic performance managemen policy is based on Verigo [8] and ARM s Inelligen Manager. The disribuion of he four available performance levels (wih a highes frequency of 6MHz) among he execued asks is shown in Figure for each applicaion. As he bar graph shows, he processor spends significan ime in sleep mode, meaning ha he processor complees many asks well ahead of schedule. Mos imporanly, we observed ha during he execuion of all asks a run-hen-idle paern was seen 5% of he ime. This implies ha many asks could run a a frequency less han he minimum (5%) available on he processor if i was able o do so. By exending he lower limi of volage scaling, he amoun of idle ime can be reduced leading o more energy-efficien operaion. Based on he previous analysis, energy efficiency can increase unil i reaches he energy opimal volage. In addiion, by eliminaing he need o ener a sleep sae, any energy overhead due o swiching o and from sleep mode is also avoided, furher increasing he energy efficiency. We herefore sudy he oal energy consumpion of he processor as a funcion of he lower limi of he performance ha he processor provides, denoed by f limi. Assuming ha we have an ideal performance scheduler ha is able o se he performance exacly sufficien o jus complee every ask, we can compue he opimal energy consumpion wih differen f limi values. The oal energy is based on he proposed energy model of Secion 3 for subhreshold volage opera-

6 normalized normalized emacs fs konqueror plaympeg nescape -flimi flimi (%) Figure. - f limi for differen applicaions f limi of idle processor f (%) limi normalized.4 3 f limi (%) Figure 3. - f limi for an idle processor ion, combined wih a simple fied model for energy and delay a super-hreshold operaing volages. Noe ha we do no consider he sleep-wakeup energy overhead alhough his could be easily incorporaed in our analysis. We show he energy / f limi rade-off for he firs five applicaions in Figure. As can be seen, he energy efficiency improves as he f limi is reduced and levels off for mos applicaions below %, which corresponds o a / of 3.7% (553mV for a of.8v). Finally, we also analyze he energy / f limi rade-off for he idlemode race, in which he processor is mosly in sleep mode, waking up only o do regular housekeeping chores for he operaing sysem. Noe ha his sae can be quie common on a processor. The resuls are given in Figure 3, and show ha he energy coninues o reduce down o a performance level of.%, corresponding o a / of 3% (34mV for a of.8v). Noe ha in such low aciviy siuaions he pracical value approaches he heoreical levels of Secion 3. The energy savings of a more scalable processor over he radiional one are summarized in Table, and how ha subsanial energy savings can be obained by exending he volage range appropriaely. 6 Conclusions In his paper, we developed analyical models for he mos energy efficien supply volage ( ) for CMOS circuis. A number of ineresing conclusions can be drawn: ) shows clear minimum in he subhreshold region since he ime over which a circui is leaking Table. consumpion comparison beween aggressive DVS and radiional DVS approaches Applicaion Normalized Aggressive DVS Tradiional DVS Savings emacs % fs % konqueror % nescape % mpeg % idle sae.76e E-4 8.7% noe: In aggressive DVS, / is 3.7% for general applicaions, 3% for idle sae; in radiional DVS, / is assumed as 5%. (delay) grows exponenially in his region while leakage curren iself does no drop as rapidly wih reduced,) does no depend on V h, 3) he logic deph and swiching facor of he circui impacs since i relaes o he relaive conribuions of leakage energy and acive energy and 4) he only relevan echnology parameers o are subhreshold swing and he dependency of delay on inpu ransiion ime. The analyical models presened are shown o mach very well wih SPICE simulaions. We hen used hese models along wih workload races for an exising DVS processor o show how he pracical minimum energy volage compares o he heoreical value. We find ha under ypical workload requiremens, he operaing volage (frequency) should be scaled o approximaely 3% (%) of he maximum. Since in curren DVS-based processors is commonly 5% of he maximum, his implies ha here is room for improvemen in he energy efficiency of hese sysems. Acknowledgemens This research was suppored by ARM, NSF, SRC, GSRC-DARPA References [] Transmea Crusoe. hp:// [] Inel XScale. hp:// [3] IBM PowerPC. hp:// [4] K. Flauner, S. Reinhard, and T. Mudge, Auomaic Performance Seing for Dynamic Volage Scaling, In Proc. of he 7h Annual Inernaional Conference on Mobile Compuing and Neworking (MobiCom ), May. [5] T. Sakurai and A. Newon, Alpha-Power Law MOSFET Model and Is Applicaions o CMOS Inverer Delay and oher Formulas,IEEE JSSCC, Vol. 5, No., April 99. [6] M. Miyazaki, J. Kao, A. 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