Lecture 040 Digital Phase Lock Loops (DPLLs) (09/01/03) Page 040-1

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1 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page LECTURE 040 DIGITAL PHASE LOCK LOOPS (DPLLs) INTRODUCTION Inroducion Objecive: Undersand he operaing principles and classificaion of DPLLs. Organizaion: Sysems Perspecive Circuis Perspecive Types of PLLs and PLL Measuremens ;;;;; PLL Applicaions and Examples ;;;;; ;;;;;;;;; PLL Componens Technology ;;;;; Perspecive CMOS Technology Fig Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Ouline Building Blocks of he DPLL Dynamic Performance of he DPLL Noise Performance of he DPLL DPLL Design Procedure DPLL Sysem Simulaion

2 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page BUILDING BLOCKS OF THE DPLL Block Diagram of he DPLL v 1, ω 1 Digial Analog v f v 2, ω 2 v 2 ', ω 2 ' Phase Lowpass VCO Deecor Filer N Couner (Opional) Fig The only digial block is he phase deecor and he remaining blocks are similar o he LPLL The divide by N couner is used in frequency synhesizer applicaions. ω 2 = ω 1 = ω 2 N ω 2 = N ω 1 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page DIGITAL PHASE DETECTORS Inroducion Key assumpion in digial phase deecors: v 1 () and v 2 () are square waves. This may require amplificaion and limiing. v in () v ou v in () V OH V OH V IH V IL V IL V IH v in V OL V OL Fig Types of digial phase deecors: 1.) EXOR gae 2.) The edge-riggered JK flip-flop 3.) The phase-frequency deecor

3 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page The EXOR Gae v 1 v 2 ' Zero Phase Error: G 1 Fig v 1 v v 1 v 2 ' Posiive Phase Error: v 1 v 2 ' θ e >0 Fig Fig Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page EXOR Gae Coninued Assume ha he average value of, is shifed o zero for zero phase error, θ e. can be ploed as, V OH -π π 2 - π 2 π θ e K d = V OH-V OL π V OL Fig If v 1 and v 2 are asymmerical (have differen duy cycles), hen becomes, v 1 v 2 ' V OH V OL Fig The effec of waveform asymmery is o reduce he loop gain of he DPLL and also resuls in a smaller lock range, pull-in range, ec. -π π 2 - π 2 π θ e

4 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page JK Flip-Flop The JK Flip-Flop is no sensiive o waveform asymmery because i is edge-riggered. Zero Phase Error (Assume rising edge riggered): v 1 v 2 ' J Q FF K Q Fig v 1 v 2 Q n Q n Q n Posiive Phase Error: v 1 v 2 ' v 1 Fig v 2 ' θ e >0 Fig Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page JK Flip-Flop Phase Deecor Coninued Inpu-Oupu Characerisic: V OH -π π θ e K d = V OH-V OL 2π V OL Fig Commens: Symmery of v 1 and v 2 is unimporan Boh he EXOR and he JK flip-flop have a severely limied pull-in range if he loop filer does no have a pole a zero.

5 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page The Phase-Frequency Deecor (PFD) The PFD can deec boh he phase and frequency difference beween v 1 and v 2. Concepual diagram: PD LPF 1 V LPF1 V in ω in V ou ω ou Phase Feedback VCO Frequency Feedback FD LPF 2 V LPF2 The oupu signal of he PFD depends on he phase error in he locked sae and on he frequency error in he unlocked sae. Consequenly, he PFD will lock under any condiion, irrespecive of he ype of loop filer used. Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page The PFD Coninued PFD implemenaion: V DD v 1 v 2 ' D FF A Clk R D R FF Clk B Q Q Q A Q B Dn Up Fig No AND Gae Wih AND Gae Q A Q B Q A Q B Sae= Sae = Sae= PFD Sae Diagram: Sae II B Sae 0 A Sae I B Q A = 0 Q B = 1 Q A = 0 Q B = 0 Q A = 1 Q B = 0 A A B Fig Unlike he EXOR gaes and he R-S laches, he PFD generaes wo oupus which are no complemenary.

6 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Illusraion of a PFD PFD (ω A = ω B ): A B Q A PFD Q B (Rising edge riggered) Fig φ A >φ B : A φ A <φ B : A B B Q A Q A Q B Q B Time Time Fig Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Illusraion of he PFD- Coninued ω A <ω B : A ω A >ω B : A B B Q A Q A Q B Q B Time Time Fig

7 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page PFD Coninued Plo of he PFD oupu versus phase error: V OH -4π -2π 2π 4π θ e Fig When θ e exceeds ±2π, he PFD behaves as if he phase error recycled a zero. K d = V OH-V OL 4π A plo of he averaged duy cycle of versus ω 1 /ω 2 (ω A /ω B ) in he unlocked sae of he DPLL: V OL Average Duy Cycle Fracion of ime Q A =1 and Q B =0 (+1 sae) ω 1 /ω 2 ' Fracion of ime Q A =0 and Q B =1 (-1 sae) Fig Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page CHARGE PUMPS Wha is a Charge Pump? A charge pump consiss of wo swiched curren sources conrolled by Q A and Q B which drive a capacior or a combinaion of a resisor and a capacior o form a filer for he PLL wih a pole a he origin. V DD A I 1 B A B PFD I 1 =I 2 =I Q A Q B X Y S 1 S 2 I 2 V ou C p Q A Q B V ou Q A and Q B are simulaneously high for he duraion given by he delay of he AND gae and he rese pah of he flip-flops. ω A > ω B or ω A = ω B bu θ A > θ B : S 1 is on and V ou increases. ω A < ω B or ω A = ω B bu θ A < θ B : S 2 is on and V ou decreases. Fig

8 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page A Charge-Pump PLL Block diagram: V DD I 1 x() PFD Q A Q B S 1 S 2 C p VCO y() I 2 Fig The charge pump and capacior C p serve as he loop filer for he PLL. The charge pump can provide infinie gain for a saic phase shif. Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Sep Response of a Charge Pump PLL Assume ha he period of he inpu is T 1 and he charge pump provides a curren of ±I p o he capacior C p. A B Q A T 1 Deecor gain? V ou Slope = Since he seady-sae gain =, i is I p more meaningful o define K d as follows, Amoun of () increase per period (T 1 ) = I p θ e C p x 2π/T 1 = I p T 1 θ e 2πC p Average slope per period = I p T 1 θ e 2πC x 1 p T = I p θ e 1 2πC p I p () = Average Slope θ = 2πC p θ e µ() Taking he Laplace ransform gives, I p V d (s) = θ e 2πC p s s K d = Q B I p 2πC p C p T 1 I p T 1 θ e Increase/period = 2πC p Fig V rads θe

9 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page A Charge-Pump PLL Coninued Y(s) X(s) = V 2(s) V 1 (s) =? Y(s) = K o s V d(s) = K ok d s 2 [X(s) Y(s)] Y(s) X(s) = K o K d s 2 + K o K d which has poles a ±j K o K d. To avoid insabiliy, a zero mus be inroduced by he resisor in series wih C p. V d (s) = I 2π R+ 1 I sc = p s2πc (src p p +1) = K d s (sτ p +1) Y(s) = K o s V d (s) = K ok d s 2 (sτ p +1) [X(s) Y(s)] Y(s) 1 + K ok d s 2 (sτ p +1) = K ok d s 2 (sτ p +1)X(s) Y(s) X(s) = K o K d (sτ p +1) s 2 + K o K d τ p s + K o K d Equaing o he sandard second-order denominaor gives, ω n = K o K d and ζ = ω nτ p 2 V DD S1 S 2 I 1 I 2 V ou C p R Fig Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Nonideal Effecs of Charge-Pumps 1.) Dead zone. A dead zone occurs when Q A or Q B do no reach heir full logic levels. This is due o delay differences in he AND gae and he flipflops. I is easily removed by proper synchronizaion of he delays. Dead Zone θe 2.) Mismach beween I 1 and I 2. To eliminae he dead zone, Q A and Q B can be simulaneously high for a small ime. If I 1 I 2, he oupu varies even hough θ e = 0. (Can inroduce spurs.) A B Q A Fig Q B 3.) Charge injecion. When he S 1 and S 2 swiches urn off, hey can injec/remove charge from C p. Changes ω 2. V DD Fig ) Charge sharing. If X V DD and Y = 0 when S 1 and S 2 are off, he VCO will experience a jump when S 1 or S 2 urns on. This periodic effec inroduces sidebands (spurs) a he oupu. C x C y I 1 X S 1 S 2 Y I 2 C p Fig

10 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page DYNAMIC PERFORMANCE OF THE DPLL Types of PLLs Type I Open-loop ransfer funcion has one pole a he origin. Type II Open-loop ransfer funcion has wo poles a he origin. The above ransfer funcions may also have oher roos bu no a he origin. Model for he DPLL θ 1 (s) θ 2 '(s) PD K d LPF F(s) VCO K o s θ 2 (s) N Couner Opional Various configuraions of he DPLL: 1.) Phase deecor EXOR, J-K flip-flop, or PFD 2.) Filer Passive lag wih or wihou a charge pump Acive lag wih or wihou a charge pump Acive PI wih or wihou a charge pump 1 N Fig Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Loop Filers 1.) Passive lag- PD F(s) = 1 + sτ s(τ 1 + τ 2 ) PFD F(s) 1 + sτ 2 s(τ 1 + τ 2 ) Experimenal resuls using he PFD wih a passive lag filer show ha he gain of he passive filer is no consan. As a resul, he filer dynamics become nonlinear. 2.) Acive lag- 1 + sτ 2 PD F(s) = K a 1 + sτ 1 PFD F(s) 1 + sτ 2 sτ 1 3.) Acive PI- PD or PFD F(s) = 1 + sτ 2 sτ 1

11 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page The Hold Range, ω H The hold range, ω H, is he frequency range wihin which he PLL operaion is saically sable. The hold range for various ypes of DPLLs are: Type of PD EXOR EXOR EXOR JK-FF JK-FF JK-FF PFD Loop Filer Passive Lag Acive Lag Acive PI Passive Lag Acive Lag Acive PI All Filers ω H K o K d (π/2) ok d (π/2) K o K d π K o K d K a π N N N N Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page The Lock Range, ω L The lock range is he offse beween ω 1 and ω 2 /N ha causes he DPLL o acquire lock wih one bea noe beween ω 1 and ω 2 = ω 2 /N. 1.) PD = EXOR 0.5K d π Recall ha ω L (LPLL) = 2ζω n and ω L Range of θ e = θ e -0.5K d π ω 2 ' Bu, θ e (EXOR)=0.5π θ e (LPLL) 2π/ ω ω L = 0.5π(2ζω n ) = πζω n ω 1 K d π ω o ω ω L = πζω n 2.) PD =JK-Flip flop θ e (EXOR) = π θ e (LPLL) ω L = π(2ζω n ) -K d π ω 2 ' ω 1 2π/ ω ω o ω L = 2πζω n 3.) PD = PFD θ e (PFD) = 2π θ e (LPLL) Fig ω L = 2π(2ζω n ) ω L = 4πζω n The lock ime for all cases is T p 2π/ω n. ω 2 '() ω 2 '() Fig ω

12 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page The Pull-In Range, ω p, and he Pull-In Time, T p The pull-in range, ω p, is he larges ω = ω 1 ω 2 for which an unlocked loop will lock. The pull-in ime, T p, is he ime required for he loop o lock. EXOR as he PD: Waveformsv d 0.5K d π -0.5K d π T 1 T 2 T = 2π/ ω Fig ω 2 ' ω() ω o T = 2π/ ω T 1 > T 2 because ω is smaller when is posiive and larger when is negaive. Resuls- Type of Filer ω p (Low loop gains) ω p (High loop gains) Pull-in Time, T p Passive Lag π 2 2ζω π nk o K d - ω 2 n 2 ζω nk o K 4 o 2 d π 2 ζω 3 n Acive Lag π 2 2ζω n K o K d - ω n 2 π K a 2 ζω nk o K 4 o 2 d π 2 ζω 3 n Acive PI 4 o 2 π 2 ζω 3 n ω 1 ω 2 ' Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page The Pull-In Range, ω p, and he Pull-In Time, T p -Coninued JK Flip-Flop as he PD: Waveformsv d K d π -K d π T 1 T 2 T = 2π/ ω ω 2 ' ω o ω() T = 2π/ ω ω 1 ω 2 ' Fig T 1 > T 2 because ω is smaller when is posiive and larger when is negaive. Resuls- Type of Filer ω p (Low loop gains) ω p (High loop gains) Pull-in Time, T p Passive Lag π 2ζω n K o K d - ω 2 n π 2 ζω n K o K d 1 o 2 π 2 ζω 2 n Acive Lag π 2ζω n K o K d - ω n 2 π 2 ζω n K o K d 1 ω o 2 K a π 2 ζω 2 n Acive PI 4 ω o 2 π 2 ζω 2 n

13 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page ω p and T p for he PFD Assume ha he PFD uses a single power supply of V DD. The various waveforms are, v 1 V DD 0.5V DD v 2 ' 0 (eq.) V DD High Impedance Sae 0.5V DD (If he filer ime consan >> he duy cycle, his waveform simplifies he analysis.) 0 v f V DD 0.5V DD (eq.) is a 50% duy cycle model of he PFD o find T p. ω 1 T P ω Ko Fig Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page ω p and T p for he PFD Coninued Since ω p =, le us find T p using he following model for he passive lag filer: + V R DD 1 +R 2 v 2 d C - PFD Filer 100% Duy Cycle + v f - V DD 2 PFD + - R 1 +R 2 2C Filer + v f - 50% Duy Cycle Fig Use he 50% duy cycle model, solve for he ime necessary o increase v f by ω/k o. 1.) Loop filer = Passive lag K o V DD /2 T p = 2(τ 1 +τ 2 ) ln K o V DD /2 - ω o 2.) Loop filer = Acive lag K o K a V DD /2 T p = 2τ 1 ln K o K a V DD /2 - ω o 3.) Loop filer = Acive PI T p = 2τ 1 ω o K o V DD /2 For spli power supplies, replace V DD wih (V OH -V OL ).

14 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page The Pull-Ou Range, ω po The pull-ou range is he size of he frequency sep applied o he reference inpu ha causes he PLL o lose phase racking. 1.) EXOR: ω po 2.46ω n (ζ ) for 0.1 < ζ < 3 2.) JK Flip-flop: ω po = πω n exp ζ 1-ζ 2 an-1 1-ζ 2 ζ, ζ < 1 ω po = πω n e, ζ = 1 ω po 5.78ω n (ζ + 0.5) for all ζ ω po = πω n exp ζ 1-ζ 2 anh-1 1-ζ 2 ζ,ζ > 1 3.) PFD: ω po = 2πω n exp ζ 1-ζ 2 an-1 1-ζ 2 ζ, ζ < 1 ω po = 2πω n e, ζ = 1 ω po 11.55ω n (ζ + 0.5) for all ζ ω po = 2πω n exp ζ 1-ζ 2 anh-1 1-ζ 2 ζ, ζ > 1 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Example 1 A Simple CMOS PLL Consider he PLL shown. Assume ha: 1.) he phase deecor is a simple CMOS EXOR whose logic levels are ground and V DD = 5V, 2.) boh he inpu o he loop and he VCO oupu are square waves ha swing beween ground andv DD, and 3.) ha he VCO has a perfecly linear relaionship beween he conrol volage and oupu frequency of 10 MHz/V. The polariies are such ha an increase in conrol volage causes an increase in he VCO frequency. (a.) Derive he expression for he open-loop ransmission and he ransfer funcion θ ou (s)/θ in (s). (b.) Iniially assume R 2 = 0 and R 1 = 10kΩ. Wha value of C gives a loop crossover frequency of 100kHz? Wha is he phase margin. Assume he op amp is ideal. (c.) Wih he value of C from par (b.), wha value of R 2 will provide a phase margin of 45 while preserving a 100 khz crossover frequency. (d.) Now assume ha a frequency divider of facor N is insered ino he feedback pah. Wih he componen values of par (c.), wha is he larges value of N ha can be oleraed wihou shrinking he phase margin below 14? θ in EXOR PD R 1 V DD 2 R C Par (d.) N VCO SU03E1P2 θ ou

15 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Example 1 - Coninued Soluion (a.) θ ou (s) = K o s F(s)K d θ in (s) + θ ou(s) N = 5K o sπ F(s) θ in (s) + θ ou(s) N K d = 5V π and F(s) = - R 2+(1/sC) sr 1 C = - sr 2C+1 sr 1 C = - sτ 2+1 sτ 1, τ 1 = R 1 C and τ 2 = R 2 C θ ou (s) = - 5K o sτ sπ 2 +1 sτ 1 θ in (s) + θ ou(s) N θ ou (s) 1 + 5K o sτ 2 +1 sπn sτ 1 = 5K o sτ 2 +1 sπ sτ 1 θ in (s) 5K o πτ 1 (sτ 2 +1) θ ou (s) - θ in (s) = θ ou (s) - θ in (s) = s 2 + 5K o πn τ 2 τ 1 s + 5K o πnτ 1 5K o πτ 1 (sτ 2 +1) s2+ 5K o τ 2 πn τ 1 s + 5K and he loop gain = LG = - o πnτ 1 Assume N = 1 o ge he answer o par (a.). 5K o sτ 2 +1 snπ sτ 1 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Example 1 - Coninued (b.) Wih R 2 = 0, τ 2 = 0 so ha he loop gain becomes, 5K o LG = - s 2 τ 1 Nπ = 5 2πx107 s 2 τ 1 π = ω c 2τ = 1 τ 1 1 = (2π 10 5 ) 2 = 253.3µsec. τ 1 = R 1 C 253.3µsec. = 10kΩC C = 25.3nF The phase margin is 0. (c.) The phase margin is oally due o τ 2. I is wrien as, PM = an -1 (ω c τ 2 ) = 45 ω c τ 2 = 1 τ 2 = 1 1 ω c = 2πx10 5 = µs = R 2 C 1 R 2 = 2πx x10-9 = 62.83Ω (d.) N does no influence he phase shif so we can wrie, an -1 (ω c τ 2 ) = 14 ω c τ 2 = ω c = ω c = 156,657 rads/sec. Now he loop gain a ω c mus be uniy. LG = - N = 5K o ω c Nπ (ω c τ 2 ) 2 +1 ω 5K o c τ 1 = 1 N = (ω c )2πτ 1 (ω c τ 2 ) (156,657) x10-6 (0.2493) 2 +1 = = 16

16 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page NOISE PERFORMANCE OF THE DPLL Combinaion of Noise and Informaion In he LPLL, he noise and informaion signals are added because of he linear muliplier PD. The noise supression of DPLL s is generally beer han LPLL s bu no heory of noise exiss for he DPLL. The following pages provide some insigh ino he noise performance of he DPLL. Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Noise Performance of a DPLL wih an EXOR PD θ j v 1 v 1j v 2 ' 100% 50% 0% θ j θ j θ j θ j θ j θ j Phase noise a a given inband frequency Ideal Inpu Inpu wih phase noise superimposed (phase jier) Deecor Oupu is proporional o he phase noise. LPLL noise heory DPLL noise heory. Fig

17 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Phase Noise in a Communicaion Signal Consider he following simple noise model- Noiseless binary informaion signal: v 1 Above signal afer ransmission hrough a bandlimied sysem: v 1b Superposiion of noise: v 1n Reshaped signal: v ;;; 1r Phase Jier ;;;;;; V upper V lower Fig Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Inpu Signal-o-Noise Raio The inpu signal noise raio of a pulse wih phase jier is defined as, 1 SNR i = 2 θ 2 n1 where θ 2 n1 W2 36 where, v 1 W

18 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Phase Noise in a DPLL wih a JK Flip-Flop and a PFD The basic difference is ha he JK Flip-flop and PFD are edge-riggered. When he inpu signal fades (v 1 0), he reshaped signal can sick a a disinc logic level. Conclusion: The noise suppression of he DPLL is abou he same for all phase deecors as long as none of he edges of he reference ge los by fading. If fading occurs, he EXOR offers beer noise performance. Summary of DPLL Noise Performance: P s = inpu signal power P n = inpu noise power B i = inpu noise bandwidh B L = noise bandwidh ω n 2 ζ + 1 4ζ SNR i = SNR of he inpu signal = P s P n SNR L = SNR of he loop = SNR i B i 2B L Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page DPLL DESIGN PROCEDURE Design Procedure Objecive: Design K o, K d, ζ, and F(s) Given: Phase deecor and VCO Seps: 1.) Specify f 1 (min), f 1 (max), f 2 (min), and f 2 (max). 2.) Design N unless oherwise specified. Given: ω n (min) < ω n < ω n (max) and ζ min < ζ < ζ max For hese ranges we ge approximaely, ω n (max) ω n (min) = N max N min and ζ max ζ min = N max N min N = N mean = N max N min 3.) Deermine ζ. Typically, ζ ) If noise is of concern, coninue wih he nex sep, oherwise go o sep ) If here are missing edges in he inpu signal (fading), go o sep 6, oherwise go o sep 7. 6.) Choose an EXOR phase deecor. Coninue wih sep 8. K d = V OH-V OL π

19 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Design Procedure Coninued 7.) Choose he JK Flip-flop or PFD as he phase deecor. K d = V OH-V OL 2π (JK flip-flop) K d = V OH-V OL 4π (PFD) 8.) Specify B L. B L should be chosen so ha SNR i B i 2B L 4 θ n1 2 SNR i and B i B L If N changes, his can creae a problem because B L = ω n 2 ζ + 1 4ζ and boh ω n and ζ vary wih N. Need o check ha B L (min) is large enough. If B L is oo small, hen N should be increased. Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Design Procedure Coninued 9.) Find K o. K o = ω 2(max)-ω 2 (min) v f (max)-v f (min) 10.) Find ω n given B L and ζ. ω n = 8B Lζ 1+4ζ If N is variable, use B L and ζ correspondingly o N = N mean. 11.) Specify he loop filer. Given ω n, ζ, K o, K d, and N find τ 1, τ 2, and K a (K a >1). Go o sep ) Coninued from sep 4. Choose he PFD 13.) Find K o. K o = ω 2(max)-ω 2 (min) v f (max)-v f (min) K d = V OH-V OL 4π

20 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Design Procedure Coninued 14.) Specify he ype of loop filer. Use he passive lag filer as he ohers offer no benefis. 15.) Deermine ω n. a.) Fas swiching (T p ). Go o sep 16. b.) DPLL does no lock ou when swiching from N o f ref o (N o +1) f ref. ω po <f ref. Go o sep 20. c.) Neiher he pull-in ime nor he pull-ou range are criical. Go o sep ) Given he maximum T p allowed for he larges frequency sep, solve for τ 1 or τ 1 +τ ) Find ω n. Loop filer is passive: ω n = Acive lag filer: ω n = Acive PI filer: ω n = K o K d N(τ 1 +τ 2 ) K o K d K a Nτ 1 K o K d Nτ 1 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Design Procedure Coninued 18.) Given ω n and ζ, find τ 2. τ 2 = 2ζ ω n If he sysem canno be realized (negaive values of τ 1 or τ 2 ), modify ω n and ζ appropriaely. 19.) Given τ 1 and τ 2 (and K a ), deermine he filer componens. 20.) Given ω po and ζ, find ω n. ω po ω n 11.55(ζ+0.5) 21.) Given T L, find ω n from ω n 2π/T L. 22.) Given ω n, find τ 1 and τ 1 +τ 2. Passive lag filer: τ 1 +τ 2 = K ok d Nω 2 n Acive lag filer: τ 1 = K ok d K a Nω 2 n Acive PI filer: τ 1 = K ok d Nω 2 n Go o sep 18.).

21 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Flowchar of he DPLL Design Procedure Yes Use EXOR Yes Are here missing edges? Specify he noise bandwidh, B L Design he VCO Use B L and ζ o find ω n Specify he range of f 1 and f 2 Deermine N or range of N Deermine ζ or range of ζ No Is Noise Suppression Required? No Choose he PFD, design he VCO and he loop filer Use PFD TP Given T P, ω po, or T L ω T po L Use T P o find τ 1 or τ 1 +τ 2 Use ω po and ζ o find ω n Use T L o find ω n Esimae ω n from τ 1 Use ωn and ζ o find τ1 Selec he loop filer and deermine τ 1, τ 2, (K a ) Use ω n and ζ o find τ 2 Calculae he loop filer values Fig Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Design Example A Frequency Synhesizer Using he 74HC/HCT4076 Design a DPLL frequency synhesizer using he CMOS 74HC/HCT4076 PLL. The frequency syhesizer should be able o produce a se of frequencies in he range of 1MHz o 2MHz wih a channel spacing of 10kHz. Use a PFD and a passive lag-lead filer. Design: 1.) Deermine he ranges of he inpu and oupu frequencies. f 1 is consan a 10kHz. f 2 (min) = 1MHz and f 2 (max) = 2MHz 2.) Choose N. N max = 2MHz 10kHz = 200 and N min = 1MHz 10kHz = 100 N mean = N max N min = ) Find ζ. Sar by choosing ζ = 0.7 and find ζ max and ζ min. ζ max ζ max = N max N min = 2 and ζ = ζ max ζ min = 0.7 ζ 2 min 2 =0.49 ζ min = 0.59 and ζ max = = < ζ < 0.83 which is consisen wih our choice of ζ. 4.) Selec he PFD as he phase deecor. For he 74HC/HCT4076, V OH = 5V and V OL =0V. This gives a K d = 5V/4π = 0.4 V/rad.

22 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Design Example Coninued 5.) According o he daa shee of he f 2 (MHz) 74HC4046A, he VCO operaes linearly in he volage range of v f = 1.1V o 3.9V as shown. 2 K o = 2x106 x2π = 2.2x106 rads/v sec 1 The daa shee also requires calculaion of 1.1V 3.9V wo resisors, R 1 and R 2, and a capacior, C 1. Using he graphs from he daa shee gives, R 1 = 47kΩ, R 2 = 130kΩ, and C 1 = 100pF. 6.) Assume he loop should lock wih 1ms T L = 1ms ω n = 2π/T L = 6280 rads/sec. 7.) Using a passive loop filer we ge, τ 1 +τ 2 = K ok d Nω 2 = 2.2x n = 161µs 8.) τ 2 = 2ζ ω n = = 223µs!!! (The problem is ha τ 1+τ 2 is oo small) Go back and choose T L = 2ms ω n = 2π/T L = 3140 rads/sec. τ 1 +τ 2 = K ok d Nω 2 = 2.2x n = 633µs and τ 2 = 2ζ ω n = = 446µs τ 1 = 187µs v f (V) Fig Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Design Problem Coninued 9.) Design he loop filer. For opimum sideband supression, C should be large. Choose C = 0.33µF. R 1 = τ 1 C = 187x x10-6 = 567Ω and R 2 = τ 2 C = 446x x10-6 = 1.351Ω The daa shee requires ha R 1 +R 2 470Ω which is saisfied. Block diagram of he DPLL frequency synhesizer design of his example: C 1 =100pF v 1 (10kHz) SIGin COMPin v 2 ' PC1 (EXOR) 74HC4046A C1A C1B Daa N P0 P7 PE PC2 (PFD) PCP ou VCO VCOou CP 74HC40102 (40103) TC v 2 ' PC3 (JK) TE PL MR PC2 ou VCOin R1 R2 R 1 =567Ω R 2 =1.35kΩ R 1 = 47kΩ R 2 = 130kΩ +5V C = 0.33µF Fig

23 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Simulaion of he DPLL Example The block diagram of his example is shown below. θ 1 (s) θ 2 '(s) PD K d LPF F(s) VCO K o s θ 2 (s) N Couner Opional The PFD-charge pump combinaion can be approximaed as K d (1+sτ 2 ) K d F(s) = s(τ 1 +τ 2 ) Therefore, he loop gain becames LG(s) = K ok d (1+sτ 2 ) s 2 (τ 1 +τ 2 ) = K v (1+sτ 2 ) (s+ε) 2 (τ 1 +τ 2 ) 1 N Fig (he facor ε is used for simulaion purposes) For his problem, K d = 0.4V/rad., K o = 2.2x10 6, τ 2 = 446µs, and τ 2 +τ 2 = 633µs. Also choose ε = R.E. Bes, Phase-Locked Loops Design, Simulaion, and Applicaions, 4 h Ed., McGraw-Hill, NY, p. 103 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Simulaion of he DPLL Example Coninued PSPICE Inpu File DPLL Design Problem-Open Loop Response - Bes VS 1 0 AC 1.0 R K * Loop bandwidh = Kv =8.8x10E5 sec.-1 Tau1=187E-6 Tau2=446E-6 N=141 ELPLL 2 0 LAPLACE {V(1)}= {8.8E+6/(S+0.01)/141*(0.446E-3*S+1)/(S+0.01)/0.633E-3} R K *Seady sae AC analysis.ac DEC K.PRINT AC VDB(2) VP(2).PROBE.END 100 Simulaion Resuls: 80 Noe ha he phase is very close o 0 and LG >>1 a low frequencies which is ypical of ype II sysems. db or Degrees LG Phase 20 Phase LG 0 Margin ω c Frequency (Hz)

24 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page DPLL SYSTEM SIMULATION Examples of Case Sudies using he Bes Sofware PLL Parameers- Supply volages: Posiive supply = 5V Negaive supply = -5V Phase deecor: V + sa = 4.5V V - sa = 0.5V Loop filer: τ 1 = 500µs τ 2 = 50µs Oscillaor: K o = 130,000 rads/v sec V + sa = 4.5V V - sa = 0.5V The simulaion program will be used o verify he following calculaed values: ω n = 17,347 rads/sec. ζ = f po = 7719 Hz f p = 13,192 Hz Roland E. Bes, Phase-Locked Loops Design, Simulaion, and Applicaions, 4 h ed., McGraw-Hill Book Co., 1999, New York, NY Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Case 1 Sysem Benchmark (mv) v f (µs)

25 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Case 2 - f = 8000Hz (V) Phase error 90 v f Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Case 3 Loop Jus Locks Ou v f vf (V) vd Loop pulls ou

26 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Case 4 Pull-In Range Verificaion 4.5 v f (V) Loop will no pull back in for df > 14,200 Hz Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Case 5 PFD and Illusraion of a Virually Infinie Pull-In Range f p = ±40kHz f = 35 khz o avoid clipping of v f. v f (V) T p 1.5ms

27 Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page Case 6 EXOR wih Acive PI Filer v f (V) T p 5ms Lecure 040 Digial Phase Lock Loops (DPLLs) (09/01/03) Page SUMMARY The DPLL has a digial phase deecor and he remainder of he blocks are analog Digial phase deecors - EXOR Gae - JK Flip-Flop - Phase-Frequency Deecor Charge pump a filer implemenaion using currens sources and a capacior ha works wih he PFD Charge pumps implemen a pole a he origin o resul in zero phase error The DPLL is much more compaible wih IC echnology and is he primary form of PLL used for frequency synhesizers